Search Results (238)

Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs. Full article

As the requirements in fields such as automobile, high-frequency signal generation, and medical applications, the resolution of time-to-digital converters (TDCs) has been pushed to the picosecond and sub-picosecond levels. In this study, a Vernier TDC was investigated with a time resolution less than the signal transition in the circuit. As generally happens in TDCs or Analog-to-Digital Converters (ADCs), bubble errors are found to degrade the resolution of their output codes. The bubble errors are usually attributed to non-idealities and mismatches in the circuits. Since the input time difference in high-resolution TDCs is much smaller than the signal transition time with the existence of bubble errors, it is an issue to determine the corresponding thermometer code from the output bit string of interleaved 0 s and 1 s. In our exploration, a Xilinx FPGA was employed to implement a Vernier Delay Line (VDL) for the TDC. In this timing-sensitive design, the timing difference between the two paths mainly comes from the interconnects rather than the Look-Up Table (LUT) devices. Timing constraints and regular placement were also imposed in addition to the simple Register Transfer Level (RTL) codes. Since the nature of uncertainty, a statistical model was proposed to analyze the output bit patterns. Three methods were employed to determine the output thermometer code. The first would count the total number of 1 s in the output. The second is to detect the position of the last 1. And the third is to detect the first 0 in the output bit string. The obtained results showed that these three methods were almost equivalent in the statistical outputs. The time resolution of our FPGA-based VDL can be around 5 ps in our measurement. According to our model, the transition time in the FPGA circuit was estimated as 100 ps. This result is reasonable for a chip made of 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. For the study of the linearity of our VDL, its differential nonlinearity (DNL) was less than ±2 LSB. The code-density-like analysis also shows the nonlinearity of this VDL. It was also found that the methods detecting the last 1 and the first 0 were sensitive to bit failures. In summary, for this study, it is confirmed that the three conversion methods are equivalent, and we found that detecting the last 1 or the first 0 was sensitive to bit defects or mismatches. Full article

This paper presents a multibeam hybrid beamforming (MHBF) architecture for microwave power transfer (MPT), enabling wireless power delivery to multiple receivers with a reduced number of RF chains. The proposed architecture decouples beam control into the horizontal and vertical dimensions, where horizontal multibeams are generated in the baseband through digital precoding, while the vertical beam direction is controlled by a Butler-matrix-based analog beamformer. In particular, multibeam transmission is achieved using multi-tone signals with distinct phase weights assigned to each tone, enabling beams to be steered toward different directions, while the Butler-matrix-based analog beamformer provides vertical beam-steering capability. Compared with fully digital beamforming (DBF), MHBF enables simultaneous multibeam formation in the horizontal domain with fewer RF chains, thereby reducing hardware overhead and system complexity. To validate the proposed architecture, a 5.8 GHz prototype was designed and fabricated. The experimental results demonstrate three-beam and four-beam operation under a transmit power of 30.57 dBm, while the average received RF power in the single-beam case was 12.11 dBm at a distance of 1 m. In the three-beam and four-beam cases, average received RF power levels of 7.3 dBm and 6.1 dBm per beam were achieved, respectively. RF-to-DC conversion measurements under 430 $\Omega$ and 680 $\Omega$ load conditions further showed average PCE values of up to 38.77% and 35.05% for the three-beam and four-beam cases, respectively. These results confirm the feasibility of simultaneous multibeam wireless power delivery and its potential as an effective solution for multi-receiver operation with reduced RF-chain requirements. Full article

This paper presents a 7-bit 1.6 GS/s hybrid capacitive-to-charge-injection DAC (C-CIDAC)-based flash-assisted time-interleaved (FATI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that improves the limited input range and temperature-induced gain variation in conventional CIDAC-based SAR ADCs. In the proposed architecture, a DAC voltage common-mode (V_CM) shift up to 48 LSBs is internally generated during the coarse conversion, enabling a rail-to-rail ADC input range while improving V_CM independence. In addition, a fully on-chip background gain-calibration scheme is introduced to compensate for the gain error between the CDAC and CIDAC caused by temperature variation. By taking advantage of the pulse-activation-based CIDAC operation scheme, the proposed calibration achieves robust gain tracking without any external bias control. The proposed four-channel FATI-SAR ADC was designed using a 65 nm CMOS process and occupies 13,628 μm², including the background calibration circuitry. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.60/−0.60 LSB and +0.72/−0.76 LSB at −40 °C and 105 °C, respectively. At Nyquist input, the simulated SNDR and SFDR are 41.52 dB and 53.36 dB, respectively. The ADC consumes 8.551 mW and achieves an FoM_W of 54.6 fJ/conversion step. Comprehensive post-layout simulation results show that the proposed FATI-SAR ADC operates at 1.6 GS/s and maintains an ENOB above 6.3 across a temperature range from −40 °C to 105 °C at Nyquist input. Full article

This paper presents a passive residue-coupled discrete-time delta–sigma ($\Delta \Sigma$) modulator for low-power narrowband sensing applications. Instead of adding a fourth active integrator, the proposed architecture keeps a third-order switched-capacitor main loop and reuses the intrinsic top-plate residue of an 8-bit asynchronous successive-approximation-register (SAR) quantizer. The retained capacitive digital-to-analog converter (CDAC) residue is passively reinjected through a charge-redistribution path, introducing an additional high-pass error-propagation factor in the effective noise transfer function (NTF). Under a bounded effective coupling coefficient, the proposed loop approaches fourth-order-like in-band noise suppression while retaining third-order active-loop complexity. Behavioral simulations show that the Enhanced mode improves the peak signal-to-noise-and-distortion ratio (SNDR) by 16.9 dB over the Baseline third-order mode at an oversampling ratio (OSR) of 128. Circuit-level corner verification of the standalone SAR confirms correct bit cycling and a settled residue-retention window under typical–typical (TT), slow–slow (SS), and fast–fast (FF) conditions: with the slowest conversion window of about 21.4 ns at the SS corner and a sampling period of 39.06 ns at $f_s=25.6$ MHz, roughly 17.66 ns of timing margin remains for residue holding, passive reinjection, and clock non-overlap. The proposed method provides an architecture-level route for improving in-band noise shaping without increasing the number of active integrator stages, and is particularly attractive for low-power, narrowband, and sensor-oriented analog-to-digital converter (ADC) applications. Full article

This paper presents a column-parallel adaptive-gain single-slope (SS) analog-to-digital converter (ADC) for high-speed high-dynamic-range (HDR) CMOS image sensors. Conventional adaptive-gain approaches often rely on dual-ramp generation or duplicated column circuits, which increase area and power overhead. In contrast, the proposed architecture achieves adaptive-gain operation using a single global ramp shared across all columns. A reconfigurable capacitive attenuation network embedded inside each column comparator locally scales the ramp at the comparator input, enabling seamless transition between high-gain operation for low-level signals and unity-gain operation for large signals within a single exposure and readout cycle. To suppress mode-dependent offsets while maintaining low noise, a configurable dual-source-follower ramp buffer symmetrically buffers the ramp and reference voltages during auto-zeroing and is reconfigured as a full-sized buffer during unity-gain conversion. Switching-induced column offsets are compensated using optical black pixels and lightweight digital processing. The ADC is implemented in a 110 nm CMOS image sensor process and validated through post-layout simulations including extracted parasitics and Monte Carlo mismatch analysis. The core ADC consumes 36.8 µW per column. Simulation results demonstrate linearity error below 1% without missing codes and show that the proposed AG_x8-to-AG_x1 configuration extends the effective dynamic range up to 78.3 dB. Full article

To meet the demand for high-capacity indoor wireless access in future 6G systems, we propose and experimentally demonstrate a photonics-aided D-band wireless transmission scheme operating at 138 GHz. At the transmitter, two external-cavity lasers together with an I/Q modulator are used to generate a modulated D-band carrier. At the receiver, homodyne down-conversion is employed to directly recover the received signal to baseband, thereby relaxing the requirements on ultra-wideband analog components and high-speed sampling hardware. A 20 m indoor line-of-sight wireless link is established to transmit a 56-Gbaud-rate OFDM-QPSK signal. The transmitted and received spectra, received constellations and bit-error-rate (BER) performance are functions of optical power at different symbol rates, and the channel amplitude and phase responses are systematically analyzed. The results show that broadband D-band signal generation, transmission, and recovery can be stably achieved in the proposed system. After receiver-side digital signal processing (DSP), clear QPSK constellations are obtained. BER measurements reveal an optimal optical-power operating range, and the 32-GBaud OFDM signal outperforms the 56-Gbaud-rate signal because its narrower occupied bandwidth makes it less sensitive to frequency-selective distortion. For 56-Gbaud-rate OFDM transmission, the BER approaches the 20% low-density parity-check forward-error-correction threshold at an optical power of approximately −1 dBm. Further analysis indicates that the current link performance is mainly limited by frequency-selective amplitude and phase distortions under bandwidth-constrained conditions, together with slight nonlinear effects at high power. These results verify the feasibility of a photonics-aided D-band wireless architecture with homodyne reception for medium-range, high-symbol-rate indoor transmission and provide an experimental basis for future 6G sub-THz wireless links. Full article

A dual-mode variable gain amplifier (VGA) with a wide-dynamic-range is proposed in this paper. The VGA is designed in a 0.18 μm CMOS process, and it has a body-driven variable load cell and binary gain array structure to implement both the digitally stepped programmable gain amplifier (PGA) mode and the analog-controlled VGA mode. This design removes additional digital conversion modules when integrated into an automatic gain control (AGC) loop, which simplifies the whole system architecture significantly. The design is also able to address several limitations of conventional VGAs, such as a single control mode, low AGC compatibility, and a narrow gain range. The simulation results after post-layout indicate that at PGA mode, the design has an ultra-wide gain band of −0.03 to 126.9 dB with a constant gain step of 1 dB. And in VGA mode, it allows smooth, continuous gain adjustment over a large range of −25.3 dB to 187.4 dB. The bandwidth of −3 dB is more than 45 MHz in both modes. The whole VGA uses 1.026 mW and has a core size of 0.011 mm². The output 1-dB compression point (OP1dB) was −1.57 dBm at minimum gain in the PGA mode and −4.02 dBm in the VGA mode. Besides, PVT analysis, Monte Carlo simulations and AGC system-level verification are evident enough to prove that the suggested VGA has high immunity to PVT (Process, Voltage, Temperature) variations, stable processes and high practicality in engineering applications. Full article

This paper proposes a compact two-stage analog-to-digital converter (ADC), leveraging a nonuniform flash ADC to address sensor linearization challenges. The proposed approach reduces circuit complexity in conventional two-stage linearizing ADCs while preserving overall resolution and effective nonlinearity reduction. The compactness of the proposed two-stage ADC is achieved by reducing the number of comparators in the nonuniform flash ADC and reusing the same flash ADC across both conversion stages. Consequently, the total number of comparators is reduced by nearly 75%, while the number of resistors is reduced by 50% compared to a conventional two-stage ADC having the identical resolutions in both stages as the proposed architecture. Nonuniform quantization is implemented using a reference resistor ladder with different resistance values, generating quantization levels that approximate the inverse of the nonlinear input signal and perform linearization. Performance of the proposed two-stage ADC is evaluated through LabVIEW simulations using a Negative Temperature Coefficient (NTC) thermistor (Vishay NTCLE428E3103F400L) as a case study. Results demonstrate a reduction in measurement error from 1 °C to 0.0033 °C in the range from −20 °C to 60 °C, achieving an overall resolution of 20 bits using a 10-bit nonuniform flash ADC. Full article

In this paper, to reduce system complexity and improve performance, we propose a novel compact photonic quantization scheme based on dual-output Mach–Zehnder modulators (DOMZMs). By exploiting the complementary outputs of DOMZMs and introducing a cross-channel differential combination strategy, multiple effective quantization channels are generated without increasing the number of modulators. Furthermore, an adaptive thresholding mechanism based on intrinsic signal intersections enables direct Gray code output with improved noise tolerance. Proof-of-concept experimental results fully confirm the correctness of the principle, and 4-bit quantization is successfully demonstrated. Experimental and numerical results both demonstrate good linearity over the full-scale input range, and confirm the feasibility of the proposed scheme. More performance evaluations are provided through simulations. We also discuss challenges relating to practical deployment of the proposed approach. The presented approach provides a promising solution for compact photonic analog-to-digital conversion systems. Full article

The rapid development of smart energy infrastructures and renewable energy systems requires advanced sensing solutions that provide high accuracy, expandability, and stability under real operating conditions. However, conventional gas monitoring systems are predominantly based on resistive or voltage-output sensors, which require complex analog front-end circuits and analog-to-digital conversion, leading to increased system complexity, cost, and susceptibility to electromagnetic interference. This paper tackles this limitation by proposing a frequency-domain sensing approach for multichannel monitoring of biogas plant parameters. The objective of this study is to develop and experimentally validate an extendable sensing architecture based on autogenerator microelectronic gas transducers with direct gas concentration–frequency conversion and FPGA-based digital acquisition. The proposed method is grounded in a physical–mathematical model of the space-charge capacitance of gas-sensitive semiconductor structures derived from Poisson’s equation, facilitating analytical formulation of conversion and sensitivity functions. A multichannel FPGA-based measurement system is implemented to process frequency signals without analog conditioning or ADC stages. Experimental validation was performed for CH₄ (0–85%), CO₂ (0–60%), H₂, NH₃, and H₂S (1–20,000 ppm). The results demonstrate measurement uncertainty within 0.25–0.5%, with sensitivity reaching 350–748 Hz/ppm for H₂, 455–750 Hz/ppm for NH₃, and 253–375 Hz/ppm for H₂S, while methane and carbon dioxide sensitivities reach up to 112 kHz/% and 98.7 kHz/%, respectively. Spectral analysis in the LTE-1800 band confirms improved noise immunity (up to 4.5×) and extended transmission capabilities. A 12-channel FPGA-based monitoring system (RDM-BP-1) with a 1 s sampling interval, IP67 protection, and wireless connectivity is developed and validated. The proposed architecture eliminates analog signal conditioning, reduces hardware complexity, and provides an easily expandable and reliable sensing solution for smart buildings, renewable energy systems, and cloud-integrated energy infrastructures. Full article

High-precision time and frequency references are essential for satellite navigation, deep-space exploration, and space science missions. To address the large size, high power consumption, and limited integration of conventional Passive Hydrogen Maser (PHM) servo electronics based on discrete analog chains, this paper proposes a miniaturized digital servo architecture for PHMs based on software-defined radio (SDR) and a field-programmable gate array (FPGA). The AD9364 is used as an integrated RF front end for microwave interrogation signal generation, receiver down-conversion, and analog-to-digital conversion (ADC), while digital demodulation, discriminator construction, and closed-loop control are implemented in the FPGA. A dual-frequency interrogation and time-division multiplexing scheme is introduced to separate the atomic and cavity responses, and an oversampling-based processing method combining outlier rejection and averaging decimation is adopted to improve the observation accuracy and noise immunity of weak error signals. Experimental results demonstrate stable closed-loop locking of the atomic transition spectrum, achieving a frequency stability of 1.46 × 10⁻¹² at 1 s, while significantly improving the compactness and integration level of the servo electronics. Full article

Condiment sauces such as soy sauce, fish sauce, oyster sauce, and Worcestershire sauce play a vital role in culinary practices and cultural identity, particularly in the Philippines. These sauces are distinguished by their unique volatile organic compound profiles, which define their aroma and flavor. With the growing demand for these condiment products, there is an increasing need for accurate and efficient methods to classify them, ensuring product authenticity and strengthening quality control. However, conventional approaches such as sensory evaluation and laboratory-based chemical analysis are often expensive, time-consuming, and subjective. To address this limitation, we used an electronic nose (e-nose) system integrated with a Support Vector Machine (SVM) classifier for the classification of dark condiment sauces. The system consists of an array of MQ-series gas sensors connected to an Arduino Mega 2560 for analog-to-digital conversion, with Raspberry Pi 5 serving as the primary processing unit. Sensor data undergo preprocessing steps, including standardization and dimensionality reduction through principal component analysis, before being classified using SVM. A total of 120 samples, consisting of 40 readings per condiment type, were used for training and testing, while 60 additional samples—15 per class—were reserved for validation. The e-nose system achieved a 95% classification performance, as evaluated using a confusion matrix and overall accuracy metrics. These results demonstrate the potential of the e-nose combined with SVM as a reliable tool for condiment classification. The system offers practical applications in quality control and product authentication. Future work may extend its capabilities toward spoilage detection, the integration of different gas sensors, and the classification of a wider variety of condiment sauces. Full article

Driven by the development of next-generation wireless networks and the widespread adoption of sensing, communication is shifting from traditional bit-level transmission to intelligent, rich interactions within our digital social system. However, existing speech semantic communication frameworks predominantly focus on textual accuracy, neglecting the critical affective information (e.g., tone and emotion) that is essential for natural human-centric interactions in the real world. To address this limitation, we propose the Heterogeneous Affective Speech Semantic Communication (HASCom) framework, designed for the robust transmission of highly expressive speech over complex wireless channels. Specifically, we design a heterogeneous dual-stream transmission architecture that decouples discrete phoneme-level linguistic content from continuous emotional embeddings. For discrete semantic information, we use reliable digital coding protected by Low-Density Parity-Check (LDPC) to guarantee strict recoverability. Conversely, for emotional features, we employ Deep Joint Source-Channel Coding (JSCC) analog transmission to prevent irreversible quantization errors and the cliff effect. Additionally, we develop a prior-guided diffusion reconstruction module at the receiving end. This module leverages a structural prior network to align the decoded semantics, which then steers the reverse diffusion process conditioned on the recovered affective features. Extensive experiments under both AWGN and Rayleigh fading channels demonstrate that HASCom significantly outperforms state-of-the-art baselines. Specifically, it achieves superior objective semantic similarity and subjective Mean Opinion Score (MOS) at low Signal-to-Noise Ratios (SNRs), while the JSCC transmission modules maintain an ultra-low inference latency of less than 0.1 ms, validating its high efficiency and robustness for practical deployments. Full article

A capsule endoscope (CE) provides noninvasive access to the gastrointestinal tract, offering diagnostic information that cannot be obtained through external imaging alone. However, during the examination inside the stomach, the CE’s posture may change rapidly as it moves within a dynamically deforming organ, making it difficult to determine its orientation using only the onboard camera feedback. To address this problem, this study proposes a method that employs an external array of Hall Effect Sensors (HES) to estimate the capsule’s position and orientation in real time, based on the magnetic field generated by a permanent magnet (PM) embedded inside the capsule, without the need for any additional internal sensors. This approach introduces a unified magnetic actuation and localization framework that enables real-time 5-degree-of-freedom posture estimation using only the internal PM of the capsule. Furthermore, the proposed system features an integrated architecture capable of simultaneous actuation and localization. To enhance system practicality, the sensor module and communication board were combined into a single unit that employs a digital serial communication scheme, eliminating the need for analog to digital conversion of sensing signals. By avoiding additional onboard sensors and employing a PM-based actuation system, the proposed system simplifies hardware configuration by preserving capsule miniaturization and by eliminating the high power consumption and thermal issues associated with electromagnet-based actuation, while maintaining accurate real-time tracking performance. Through an optimization process, the system achieved a position error of less than 2 mm and an angular error within 2° over a sensing range of up to 60 mm. Repeated experiments further validated the system’s effectiveness and reliability under realistic operating conditions, demonstrating its feasibility for compact and clinically applicable active capsule endoscopy systems. Full article