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Electronics
Special Issues
Design and Application of Digital Circuit and Systems
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Design and Application of Digital Circuit and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 June 2026 | Viewed by 1612

Special Issue Editors

Dr. Yafei Ning

E-Mail Website
Guest Editor
School of Integrated Circuits, Shandong University, Jinan 250101, China
Interests: RISC-V architecture; integrated circuit (IC) design; embedded systems; IoT hardware and software development
Prof. Dr. Jie Su

E-Mail Website
Guest Editor
College of Electronic and Information Engineering, Qingdao University, Qingdao 266071, China
Interests: artificial synapse; memristor; flexible electronics; ferroelectric memory
Dr. Yanpeng Shi

E-Mail Website
Guest Editor
School of Integrated Circuits, Shandong University, Jinan 250101, China
Interests: terahertz materials and devices; terahertz sensing technology; biomedical detection
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Rapid advances in AI/ML, edge computing, robotics, autonomous systems, 5G/6G, and cloud-to-edge infrastructures are reshaping the landscape of digital hardware. Designers must continually navigate challenging trade-offs among performance, power, area, cost, programmability, reliability, security, and time-to-market—now further complicated by heterogeneous integration (chiplets, 2.5D/3D), advanced technology nodes, and sustainability targets. The main objective of this Special Issue, ‘Design and Application of Digital Circuit and Systems’ is to feature new works, recent developments, reviews, and results that advance the theory and practice of digital circuits and systems—from algorithms and architectures through RTL/GDSII to system-level deployment and on-hardware validation. We especially welcome submissions that provide quantitative comparisons to the state of the art, release artifacts (code/flows/datasets) for reproducibility, or demonstrate end-to-end case studies in real applications.

Relevant topics include but are not limited to the following:

  • Logic design, microarchitectures, and domain-specific accelerators (AI/ML, DSP, cryptography, communications).
  • FPGA/ASIC methodologies; HLS-to-RTL flows; hardware–software co-design.
  • Synthesis, physical design, timing closure, and PPA optimization, as well as low-power and energy-aware design.
  • Reconfigurable, approximate, and asynchronous digital computing.
  • RISC-V and open-hardware platforms.
  • Memory hierarchies and controllers; in-/near-memory computing; emerging NVMs.
  • On-chip interconnects and NoCs; chiplets; 2.5D/3D integration.
  • High-speed digital interfaces and SERDES; die-to-die links.
  • Hardware security, trust, and privacy; side-channel and fault injection resilience.
  • Verification and validation, including formal methods, emulation, and FPGA prototyping.
  • Design for testability, reliability, and safety-critical systems.
  • Machine learning for EDA, automated design space exploration, and open/reproducible toolchains.
  • Edge/IoT and cyber–physical systems; real-time embedding, robotics, and AR/VR case studies.
  • On-silicon or on-hardware evaluation and benchmarking.
  • Applications of specific integrated Circuits.‌

We look forward to receiving your contributions.

Dr. Yafei Ning
Prof. Dr. Jie Su
Dr. Yanpeng Shi
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA
  • DSP
  • RISC-V
  • ASIC
  • VLSI
  • applications

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Published Papers (3 papers)

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Research

20 pages, 1570 KB  
Article
Co-Design of Pipelining and Fixed-Point Quantization for SOVA-Turbo Codec IP Core
by Zijun Pan, Fujin Hou, Xiaoqing Jiang, Fangzhou Liu, Shanshan Wang, Haibin Lu, Yi Han, Jiongyuan Chen and Yafei Ning
Electronics 2026, 15(9), 1954; https://doi.org/10.3390/electronics15091954 - 5 May 2026
Viewed by 317
Abstract
With the escalating demand for high reliability, low power consumption, and high throughput baseband processing capabilities in 5G and future 6G communication systems, the channel coding and decoding IP core serves as a critical module in baseband chips, where its hardware architecture and [...] Read more.
With the escalating demand for high reliability, low power consumption, and high throughput baseband processing capabilities in 5G and future 6G communication systems, the channel coding and decoding IP core serves as a critical module in baseband chips, where its hardware architecture and numerical system design exert a decisive influence on system performance. This paper proposes a SOVA-Turbo codec IP core architecture tailored for FPGA/SoC system integration. By reconstructing the Turbo iterative decoding data flow, a pipelined architecture is designed to facilitate the parallel operation of component decoders, as well as the storage and distribution of extrinsic information. Furthermore, addressing the numerical complexity of the SOVA algorithm in hardware implementation, a customized fixed-point representation and quantization co-design scheme is proposed to support hardware-efficient implementation while preserving the relative reliability relationships required for soft-decision decoding. Additionally, bit-level soft reliability information is generated at the decoder output to support iterative reliability evaluation under controlled noisy conditions. Simulation and implementation results demonstrate the feasibility of the proposed prototype in terms of timing closure, hardware cost, and decoder-side robustness under controlled perturbation. Full article
(This article belongs to the Special Issue Design and Application of Digital Circuit and Systems)
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15 pages, 2223 KB  
Article
A Serial-Number-Level Cumulative-Risk Framework for Yield Monitoring and Inspection Prioritization in Semiconductor Manufacturing
by Seong Min Ryu, Young Shin Han, Jong Sik Lee and Bo Seung Kwon
Electronics 2026, 15(7), 1421; https://doi.org/10.3390/electronics15071421 - 29 Mar 2026
Viewed by 375
Abstract
In semiconductor fabrication, abnormal behavior may first appear in a small subset of serial numbers before it is reflected in lot-level yield metrics. We present a monitoring framework that detects measurement item outliers using Z-scores, aggregates them into a serial-level cumulative-risk score, provides [...] Read more.
In semiconductor fabrication, abnormal behavior may first appear in a small subset of serial numbers before it is reflected in lot-level yield metrics. We present a monitoring framework that detects measurement item outliers using Z-scores, aggregates them into a serial-level cumulative-risk score, provides exploratory views of lot- and site-level trends, and ranks high-risk serials for follow-up. The approach is evaluated on an industrial semiconductor manufacturing dataset comprising 14,142 unique serials (Nserial = 14,142). Because most TestResult labels are PASS, label-based yield shows little variation. In this setting, label-based yield alone is not informative enough for early monitoring, so we use outlier-based yield as the primary metric, defined as the proportion of serials with cumulative risk below the threshold (R(s)<τ, where τ=10). A sensitivity study of the outlier threshold κ (σ-multiplier) shows that yield varies widely, from 61.66% at κ=3 to above 99% at κ≥7. This result shows the trade-off between detection sensitivity and inspection workload. Case studies of top-ranked serials show two recurring patterns: cumulative risk is driven either by isolated extreme deviations or by the accumulation of moderate deviations across multiple items. These results support the use of the proposed score for inspection prioritization. Full article
(This article belongs to the Special Issue Design and Application of Digital Circuit and Systems)
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16 pages, 574 KB  
Article
Feasibility-Aware Design-Space Exploration of Transparent Coarse-Grained Reconfigurable Architectures
by Thiago R. B. S. Soares and Ivan S. Silva
Electronics 2026, 15(2), 313; https://doi.org/10.3390/electronics15020313 - 10 Jan 2026
Viewed by 470
Abstract
Coarse-Grained Reconfigurable Architectures (CGRAs) execute compute-intensive kernels on a reconfigurable processing mesh. Transparent CGRAs extend this model by generating configurations at runtime and storing them in a dedicated cache, removing compiler dependence and enabling adaptive behavior. Although prior work has explored mapping strategies [...] Read more.
Coarse-Grained Reconfigurable Architectures (CGRAs) execute compute-intensive kernels on a reconfigurable processing mesh. Transparent CGRAs extend this model by generating configurations at runtime and storing them in a dedicated cache, removing compiler dependence and enabling adaptive behavior. Although prior work has explored mapping strategies and mesh scaling, the feasibility of the configuration cache remains unaddressed, as it is commonly treated as a generic storage block. This paper presents a feasibility study of configuration cache organizations and a design-space exploration of Transparent CGRAs, introducing a parameterized cache geometry model that relates cache parameters to the processing mesh and configuration structure. The model enables realistic estimates of area, latency, and energy at the digital system level and is applied to three Transparent CGRAs from the literature and five additional designs covering a wide range of spatial and temporal organizations. The results show that mesh scaling must be balanced with cache feasibility: wide I/O paths and large configurations lead to impractical caches, whereas well-proportioned meshes achieve competitive performance with modest overheads. Under the proposed exploration, selected expanded meshes outperform a two-issue out-of-order processor by up to 1.4× while increasing area by only 14.8% and energy by 2%. These findings demonstrate that Transparent CGRAs are viable, but their scalability depends on a realistic configuration cache design. The proposed parameterized cache model provides a structured and reproducible basis for analyzing transparency overheads and guiding future CGRA designs. Full article
(This article belongs to the Special Issue Design and Application of Digital Circuit and Systems)
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