A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness

Lee, Seung-Hyeon; Seo, Yong-Seok; Seo, Jee-Taeck; Kim, Tae-Hyun; Lee, Jeong-Hun; Kim, Ryun-Yeong; Baek, Kwang-Hyun

doi:10.3390/electronics15122550

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A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness

by

Seung-Hyeon Lee

¹,

Yong-Seok Seo

¹,

Jee-Taeck Seo

¹

,

Tae-Hyun Kim

¹

,

Jeong-Hun Lee

¹

,

Ryun-Yeong Kim

¹

and

Kwang-Hyun Baek

^2,*

¹

Department of Intelligent Semiconductor Engineering, Chung-Ang University, Seoul 06974, Republic of Korea

²

School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Republic of Korea

^*

Author to whom correspondence should be addressed.

Electronics 2026, 15(12), 2550; https://doi.org/10.3390/electronics15122550 (registering DOI)

Submission received: 11 May 2026 / Revised: 6 June 2026 / Accepted: 8 June 2026 / Published: 9 June 2026

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Abstract

This paper presents a 7-bit 1.6 GS/s hybrid capacitive-to-charge-injection DAC (C-CIDAC)-based flash-assisted time-interleaved (FATI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that improves the limited input range and temperature-induced gain variation in conventional CIDAC-based SAR ADCs. In the proposed architecture, a DAC voltage common-mode (

V_{CM}

) shift up to 48 LSBs is internally generated during the coarse conversion, enabling a rail-to-rail ADC input range while improving

V_{CM}

independence. In addition, a fully on-chip background gain-calibration scheme is introduced to compensate for the gain error between the CDAC and CIDAC caused by temperature variation. By taking advantage of the pulse-activation-based CIDAC operation scheme, the proposed calibration achieves robust gain tracking without any external bias control. The proposed four-channel FATI-SAR ADC was designed using a 65 nm CMOS process and occupies 13,628

μ

m

^{2}

, including the background calibration circuitry. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.60/−0.60 LSB and +0.72/−0.76 LSB at

- 40^{\circ} C

and

105^{\circ} C

, respectively. At Nyquist input, the simulated SNDR and SFDR are 41.52 dB and 53.36 dB, respectively. The ADC consumes 8.551 mW and achieves an FoM

_{W}

of 54.6 fJ/conversion step. Comprehensive post-layout simulation results show that the proposed FATI-SAR ADC operates at 1.6 GS/s and maintains an ENOB above 6.3 across a temperature range from

- 40^{\circ} C

to

105^{\circ} C

at Nyquist input.

Keywords: time-interleaved ADC; hybrid DAC; charge-injection based DAC; background calibration; temperature robustness

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MDPI and ACS Style

Lee, S.-H.; Seo, Y.-S.; Seo, J.-T.; Kim, T.-H.; Lee, J.-H.; Kim, R.-Y.; Baek, K.-H. A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness. Electronics 2026, 15, 2550. https://doi.org/10.3390/electronics15122550

AMA Style

Lee S-H, Seo Y-S, Seo J-T, Kim T-H, Lee J-H, Kim R-Y, Baek K-H. A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness. Electronics. 2026; 15(12):2550. https://doi.org/10.3390/electronics15122550

Chicago/Turabian Style

Lee, Seung-Hyeon, Yong-Seok Seo, Jee-Taeck Seo, Tae-Hyun Kim, Jeong-Hun Lee, Ryun-Yeong Kim, and Kwang-Hyun Baek. 2026. "A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness" Electronics 15, no. 12: 2550. https://doi.org/10.3390/electronics15122550

APA Style

Lee, S.-H., Seo, Y.-S., Seo, J.-T., Kim, T.-H., Lee, J.-H., Kim, R.-Y., & Baek, K.-H. (2026). A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness. Electronics, 15(12), 2550. https://doi.org/10.3390/electronics15122550

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A 7-Bit 1.6 GS/s Hybrid Capacitive-to-Charge-Injection DAC-Based Flash-Assisted Time-Interleaved SAR ADC with Background Gain Calibration for Temperature Robustness

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