Search Results (174)

As dynamic random-access memory (DRAM) continues to scale down and achieve higher integration density, the cell layout has transitioned to 6F², resulting in narrower spacing between adjacent word lines (WLs). Consequently, cell-to-cell disturbance has become more severe. In particular, the row-hammer effect (RHE) has emerged as a critical reliability issue that must be mitigated to ensure stable operation in next-generation DRAM devices. In this study, a novel DRAM cell structure is proposed, in which a low-k dielectric material is embedded beneath the storage node (SN) to mitigate the electric field. This structural modification effectively suppresses the RHE compared to the conventional partial-isolation type buried channel array transistor (Pi-BCAT). The feasibility and performance of the proposed structure were verified through 2D Sentaurus technology computer-aided design (TCAD) simulations. The device embedding the low-k dielectric beneath the SN exhibits a mitigation of approximately 20.45% in D0 failure and about 12.12% in D1 failure. This improvement is attributed to the reduced electric field in the region underneath the SN, which suppresses stored charge leakage. These results confirm that the proposed structure not only enhances DRAM reliability in advanced process nodes but also provides an effective design guideline for highly integrated and low-power memory devices. Full article

This paper presents the design, structural optimization, and two-dimensional (2D) technology computer-aided design (TCAD) simulation of a gallium nitride (GaN) vertical Merged P-i-N/Schottky (MPS) diode incorporating a multi-drift-layer doping profile, composite SiO₂/Si₃N₄ passivation, and field-plate (FP) termination. The proposed device is constructed on an n⁺-GaN substrate with a three-sub-layer n-type drift region and a p-GaN/p⁺-GaN anode region. Systematic TCAD simulations are performed to investigate the dependences of key performance metrics—including knee voltage (V_knee), specific on-resistance (R_on), breakdown voltage (BV), reverse leakage current (J_leak), and Baliga’s figure of merit (BFOM)—on the Schottky metal work function, multi-drift-layer doping concentration, drift-layer thickness, Schottky-to-PN contact length ratio (γ_w), operating temperature, and reverse recovery switching transients. Results demonstrate that the MPS architecture effectively decouples forward conduction loss from reverse blocking capability, overcoming the conventional R_on–BV trade-off. The optimal doping profile (n_mm = 2 × 10¹⁵, n_m = 2 × 10¹⁵, n = 1 × 10¹⁶ cm⁻³) achieves a BFOM of ~31.97 GW·cm⁻² with BV ≈ 5.98 kV and R_on ≈ 1.12 mΩ·cm². Joint doping–thickness optimization further identifies a graded doping profile (n_mm = 2 × 10¹⁵, n_m = 5 × 10¹⁵, n = 1 × 10¹⁶ cm⁻³) combined with layer thicknesses (T_nmm, T_nm, T_n) = (4.49, 5, 20) μm as the overall optimum, achieving BFOM = 55.36 GW·cm⁻² (BV = 6.61 kV, R_on = 0.79 mΩ·cm²)—a +73% improvement, governed by the punch-through/field-stop design principle. The optimal contact ratio of γ_w = 1.33 yields a BFOM of 38.71 GW·cm⁻². Temperature analysis confirms a positive BV temperature coefficient due to drift-region-limited avalanche breakdown, and the BFOM improves monotonically from 33.31 to 37.82 GW·cm⁻² between 200 K and 450 K. Mixed-mode switching simulations show that increasing γ_w substantially reduces reverse recovery charge (Q_rr), demonstrating the strong potential of the proposed MPS diode for high-voltage, high-frequency, and high-temperature power electronic applications. Full article

This study systematically investigates the intrinsic vertical breakdown characteristics of 8-inch GaN-on-Si high-electron-mobility transistor (HEMT) buffer layers (extending up to the GaN channel layer) using a vertical electrode configuration. By comparing samples with different carbon doping doses, AlN insertion layers, and superlattice cycle numbers (buffer layer thickness), combined with Technology Computer-Aided Design (TCAD) simulations, the relevant mechanisms are revealed. The results show that buffer layer thickness is a critical factor determining the vertical breakdown voltage. Its increase effectively reduces the longitudinal average electric field, widens the depletion region, and increases the breakdown voltage by approximately 50%. Carbon doping compensates for carriers and suppresses leakage through deep-level acceptor traps. Inserting thin AlN layers into the superlattice has a limited effect on improving breakdown voltage. This research provides clear experimental guidance for the optimal design of high-voltage GaN HEMT buffer layers from both material and physical perspectives. Full article

Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore’s Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on–off ratio of 1.1 × 10¹¹ for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on–off ratio of 5 × 10⁸. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics. Full article

A novel 3D detector with a semi-spherical electrode detector structure is proposed in this study. The semi-spherical electrode is formed by concentric deep circular-type trenches of varying depths. These concentric trenches can be simultaneously deep-etched using DRIE (Deep Reactive-Ion Etching) depths obtained from our calculations for a certain time at a given aspect ratio. The focus of this work is the conceptualization, design considerations, 3D modeling, and electrical simulation of the proposed 3D detector. The detector’s electrical properties, including electric potential distribution, electric field distribution, electron concentration distribution, full depletion voltage, leakage current, and capacitance, were simulated using a technology computer-aided design (TCAD) tool. Simulation and analysis of the detector’s performance post-irradiation were also conducted. The small capacitance of our semi-spherical electrode detector renders it highly suitable for applications in photon sciences (e.g., X-ray). Full article

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (I_GSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental I_GSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations’ current density distribution at high voltage gate stress. Full article

The threshold voltage (Vth) of p-GaN gate enhancement-mode (E-mode) high electron mobility transistors (HEMTs) on silicon substrates grown by metal–organic chemical vapor deposition (MOCVD) is often limited to 1.0–1.5 V. Apart from the low Mg acceptor activation rate, the non-uniform vertical Mg distribution in thin p-GaN layers is also a key bottleneck limiting Vth. This work reveals that the vertical distribution (not only magnitude) of Mg doping fundamentally influences Vth by modulating the charge centroid and electric field coupling to the heterointerface. Through bis(cyclopentadienyl)magnesium (Cp₂Mg) flow modulation, surfactant-assisted growth, and growth rate adjustment, the vertical Mg doping uniformity within the 80 nm p-GaN layer was improved while effectively suppressing Mg out-diffusion. A short-cycle gate-first self-aligned process was used to fabricate the devices, and the results showed that the improved Mg vertical distribution led to a significant Vth enhancement by 0.75 V. Technology Computer-Aided Design (TCAD) simulations further demonstrated that the uniform doping profile builds a stronger negative space charge field beneath the gate, raising the energy band and increasing Vth. This work not only presents practical strategies, but also establishes a direct physical link between vertical Mg doping distribution and Vth in Si-based E-mode HEMTs. Full article

Single-event effects (SEEs) present a significant challenge to the radiation reliability of integrated circuits. Conventional SEE analysis methods for single-photon avalanche diode (SPAD) devices primarily rely on Sentaurus Technology Computer-Aided Design (TCAD) numerical simulation, which is computationally intensive and time-consuming. In this study, we propose a generalized deep learning (DL) model, using a silicon-based SPAD device with a double-junction double-buried-layer (DJDB) structure fabricated in 180 nm CMOS process as the research subject. By incorporating key parameters that influence SEEs as model inputs, the proposed approach enables rapid prediction of critical parameter metrics, including transient current peaks and dark count rates. Experimental results show that the DL model achieves a prediction accuracy of 97.32% for transient current peaks and 99.87% for dark count rates, demonstrating extremely high prediction precision. To further validate the generalization capability of the proposed network, the model is applied to predict the detection performance of the DJDB-SPAD device. The prediction accuracies for four key performance parameters all exceed 97.5%, further confirming the accuracy and robustness of the developed model. Meanwhile, compared with the conventional Sentaurus TCAD simulation method, the proposed method achieves a 336-fold improvement in computational efficiency. Overall, this method realizes the dual advantages of high precision and high efficiency, which provides an efficient and accurate technical solution for the rapid characteristic analysis and reliability evaluation of SPAD devices under single-event effects (SEEs). Full article

In this paper, an innovative design of a silicon spiral drift detector (SDD) has been proposed. In this design, gaps under the SiO₂ layer between the cathode rings are kept constant, with a minimum value to reduce the surface leakage current. The cathode pitch profile $\mathrm{P}\left(\mathrm{r}\right)$ as a function of radius $\mathrm{r}$ is allowed to change in an arbitrary way to achieve the optimum field distribution. The concept, design considerations, modeling and electrical simulations have been carried out for this novel structure with a hexagonal spiral silicon drift detector. Using one-dimensional analyses, we obtain the exact solution of the spiral design $\mathrm{r}=\mathrm{r}\left(\mathrm{\theta }\right)$ with a near-arbitrary pitch profile $\mathrm{P}\left(\mathrm{r}\right)={\mathrm{P}}_1{\left({\displaystyle \frac{\mathrm{r}}{{\mathrm{r}}_1}}\right)}^{{\displaystyle \frac{1}{\mathrm{\eta }}}}$, with $\mathrm{\eta }$ as an arbitrary real number. We also obtained the electric potential and field profiles on both surfaces of the detector. Using a Technology Computer-Aided Design (TCAD) tool, we made 3D simulations of the detector’s electrical properties. The hexagonal spiral silicon drift detector has excellent electrical properties: a uniform electric field, smooth distribution of electric potential and electron concentration, and a clear electron drift channel. The distributions of the electric field, electric potential, and electron concentration are symmetrical and smooth, which is beneficial for applications in photon sciences (X-ray) and safeguards and homeland security (particle radiation). The theoretical work and simulation results serve as solid foundations for the detector design and the expansion of semiconductor technology. Full article

This study investigates the impact of non-ideal wordline sidewall angles caused by photoresist profile variation during the wordline etching process in DRAMs employing a buried-channel array transistor (BCAT) structure. Using Technology Computer-Aided Design (TCAD), a two-dimensional (2D) BCAT-based DRAM cell was modeled to analyze the resulting variations in device characteristics as well as write and hold operations. The simulation results show that increased etch slope angles lead to degradation in device performance, including failure to meet the read pass/fail criterion and data retention during the 300 ms hold interval. To mitigate these issues, we inserted a buried oxide (BOX) layer beneath the active wordline (AWL). The incorporation of the BOX layer effectively improved overall device robustness and reduced the degradation induced by non-ideal etch slopes. Full article

Accurate and efficient modeling of AlGaN/GaN HEMTs is essential for the design of next-generation power electronics. This study introduces a hybrid Auxiliary Classifier Generative Adversarial Network (ACGAN)–mixup data augmentation framework to enhance deep neural network application in AlGaN/GaN high-electron-mobility transistor modeling with limited data. Based on only 20 distinctive devices, ACGAN uses technology computer-aided design (TCAD)-calibrated data to generate high-quality synthetic drain current ($I_{ds}$) under various electronic bias conditions. The quality of the generated data is validated via Jensen–Shannon divergence with an average of 0.0341. A one-dimensional convolutional neural network (1D-CNN) predictive model is trained on augmented data and achieves stable convergence, with a mean absolute error of 0.002 A/mm for the off-state $I_{ds}$ and 0.052 A/mm for the linear region. It also shows improved robustness over the model trained on original non-augmented data. The proposed approach offers a low-cost alternative to resource-intensive TCAD simulations, enabling accurate device modeling with limited data. Full article

This study analyzed the low-frequency noise characteristics of nanosheet field-effect transistors (NSFETs) using technology computer-aided design (TCAD) simulations. In particular, the effects of shallow trench isolation (STI) depth and gate–insulator interface trap density on the device’s flicker noise power spectral density (PSD) were systematically evaluated. The simulation results show that as STI depth increases, excessive trap charges formed in the STI oxide can deplete or invert the substrate beneath the STI layer, reducing the threshold voltage of parasitic transistors and thereby increasing flicker noise. In contrast, the shallow STI structure’s trapped charge density was found to be lower than in thicker structures. Additionally, when an HfO₂–ZrO₂ (HZO)-based ferroelectric insulator is applied, improved gate–field control and reduced trap-induced noise are observed compared to HfO₂. Optimization results indicate that the optimal noise performance is achieved with an STI depth of 3 nm and a SiO₂/silicon interface trap density of 1 × 10¹⁰ eV⁻¹cm⁻². This study provides a design direction for low-noise NSFETs through structural (STI) and material (interface traps and HZO) optimization and is expected to contribute to the development of next-generation low-power, high-reliability logic devices. Full article

In this work, we report the first systematic examination of how the In composition in the intrinsic In_xGa_1-xAs layer and the p-type doping concentration in the p-type GaAsSb layer affect the device performance of side-gate p-GaAs_0.5Sb_0.5/i-In_xGa_1-xAs/n-In_0.53Ga_0.47As TFETs, using the technology computer-aided design (TCAD) simulations with a non-local band-to-band model. By tuning these two parameters, a moderate staggered alignment is achieved, enabling self-off operation at zero gate bias while maintaining high on-current. This tunability is an intrinsic and significant advantage of the p-GaAsSb/i-In_xGa_1-xAs heterojunction that has not been previously explored. It is found that the best device performance does not occur in the TFET with an In composition of 0.53 in the intrinsic layer, which is lattice-matched to the InP substrate, but rather occurs in the device with a higher In composition of around 0.59 in the InGaAs layer, which has been verified by experimental data to some extent. Optimal parameter combinations yield a minimum subthreshold swing of 13.51 mV/dec and an ON-state current of 35.39 μA/μm at V_DS = V_GS = 0.5 V due to the enhanced tunneling capability. Full article

This study investigates the impact of the self-heating effect (SHE) on single-event transient (SET) sensitivity in triple-layer stacked nanosheet transistors, using technology computer-aided design (TCAD) simulations. The results demonstrate that SHE significantly elevates the channel lattice temperature under DC bias, leading to notable degradation in DC performance metrics, including the drive current (I_ON) and the on/off current ratio. By employing a finer time resolution in the AC simulation, we observed that the device reaches thermal equilibrium on a picosecond timescale. Crucially, SHE is found to exacerbate SET sensitivity markedly. Compared to simulations without SHE, the presence of self-heating increases both the peak transient current and the collected charge at the drain terminal following heavy-ion strikes. Furthermore, the transient response is shown to depend on the thermal history; longer pre-strike heating times amplify the SET peak magnitude, whereas longer cooling times attenuate it. These findings underscore the critical importance of co-optimizing thermal management and radiation hardening in the design of advanced nanosheet technologies. Full article

This study explores the temperature dependence of reverse-recovery behavior in superjunction metal-oxide-semiconductor field-effect-transistors (MOSFETs) using experiments and Technology Computer-Aided Design (TCAD) simulations. Results show that at 145 °C, switching failure occurs due to severe reverse-recovery degradation. The main cause is the temperature-induced increase in carrier lifetime, leading to a higher reverse-recovery charge, current, and time. A practical solution is proposed by adding a small parallel capacitor, which effectively suppresses reverse recovery and improves switching reliability. This work provides physical insight and a simple strategy for optimizing superjunction MOSFET performance in high-temperature power electronics. Full article