Search Results (20)

To enhance the RF power properties of CMOS-compatible gold-free GaN devices, this work introduces a kind of GaN-on-Si HEMT with a low parasitic regrown ohmic contact technology. Attributed to the highly doped n⁺ InGaN regrown layer and smooth morphology of gold-free ohmic stacks, the lowest ohmic contact resistance (R_c) was presented as 0.072 Ω·mm. More importantly, low RF loss and low total dislocation density (TDD) of the Si-based GaN epitaxy were achieved by a designed two-step-graded (TSG) transition structure for the use of scaling-down devices in high-frequency applications. Finally, the fabricated GaN HEMTs on the Si substrate presented a maximum drain current (I_drain) of 1206 mA/mm, a peak transconductance (G_m) of 391 mS/mm, and a breakdown voltage (V_BR) of 169 V. The outstanding material and DC performances strongly encourage a maximum output power density (P_out) of 10.2 W/mm at 8 GHz and drain voltage (V_drain) of 50 V in active pulse mode, which, to our best knowledge, updates the highest power level for gold-free GaN devices on Si substrates. The power results reflect the reliable potential of low parasitic regrown ohmic contact technology for future large-scale CMOS-integrated circuits in RF applications. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

Schottky barrier thin-film transistors (SBTFTs) are promising for low-power electronics due to advantages such as low saturation voltage and high stability. In this study, we developed a high-performance bilayer IGZO SBTFT by combining a 4.7 nm atomic layer deposition (ALD) IGZO layer with an 11.8 nm sputtering IGZO layer, using platinum (Pt) and molybdenum (Mo) electrodes. The device exhibits dual-mode operation. In Schottky barrier TFT (SB-TFT) mode (Pt as source), the bilayer structure reduces defect density, achieving a very low saturation voltage (~0.4 V), high field-effect mobility (up to 20 cm²/V·s), and enhanced stability under stress conditions, including positive/negative bias and negative illumination. In quasi-Ohmic TFT (QO-TFT) mode (Pt as drain), the device retains conventional saturation behavior in output characteristics while delivering similar mobility and robust stability. This work provides a novel bilayer SBTFT design with dual functionality, enabling a higher current drive, improved stability, and flexibility for energy-efficient applications. Full article

We investigate the inorganic/organic hybrid vertical phototransistor (VPT) by integrating an atomic layer deposition-processed ZnO (ALD-ZnO) transistor with a prototype poly(3-hexylthiophene):[6,6]-phenyl-C₆₁-butyric acid methyl ester (P3HT:PC₆₁BM) blend organic photodiode (OPD) based on an encapsulated source electrode geometry, and discuss the device mechanism. Our preliminary studies on reference P3HT:PC₆₁BM OPDs show non-ohmic electron injection between the ALD-ZnO and P3HT:PC₆₁BM layers. However, the ALD-ZnO layer enables the accumulation of photogenerated holes under negative bias, which facilitates electron injection upon illumination and thereby enhances the external quantum efficiency (EQE). This mechanism underpins the photoresponse in the VPT. Furthermore, we demonstrate that the gate field in the VPT effectively modulates electron injection from the ALD-ZnO layer to the top OPD, resulting in the VPT operating as a non-ohmic OPD in the OFF state and as an ohmic OPD in the ON state. Benefiting from the unique transistor geometry and gate modulation capability, this hybrid VPT can achieve an EQE of 45,917%, a responsivity of 197 A/W, and a specific detectivity of 3.4 × 10¹² Jones under 532 nm illumination and low drain-source voltage (V_ds = 3 V) conditions. This transistor geometry also facilitates integration with various OPDs and the miniaturization of the ZnO channel area, offering an ideal basis for the development of highly efficient VPTs and high-resolution image sensors. Full article

In this paper, the contact resistance of AlGaN/GaN high electron mobility transistor (HEMT) was improved by introducing nanoscale hole arrays in ohmic regions, and the DC characteristics of the conventional structure and nanohole etching structure for HEMTs were measured for comparison. Sub-10 nm nanoholes were patterned on the ohmic area surface of AlGaN using electron beam lithography and a low-temperature short-time development. Various dwell times of e-beam exposure from 5 to 30 μs were investigated and the corresponding contact resistance of the nano hole etching structure and planar structure were compared by the transmission line model (TLM) method. We observed a reduced contact resistance from 1.82 to 0.47 Ω-mm by performing a dwell time of 5 μs of exposure for nanohole formation compared to the conventional structure. Furthermore, the DC characteristics demonstrate that the maximum drain current for HEMTs was enhanced from 319 to 496 mA/mm by utilizing this optimized ohmic contact. These results show that devices with sub-10 nm nanohole ohmic contacts exhibit an improved contact resistance over the conventional structure, optimizing device performance for HEMTs, including a lower on-resistance and higher maximum drain current. Full article

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆V_th) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (C_rss), while maintaining a similar low ON-resistance. Full article

Among various polymorphic phases of gallium oxide (Ga₂O₃), α-phase Ga₂O₃ has clear advantages such as its heteroepitaxial growth as well as wide bandgap, which is promising for use in power devices. In this work, we demonstrate α-Ga₂O₃ MOSFETs with hybrid Schottky drain (HSD) contact, comprising both Ohmic and Schottky electrode regions. In comparison with conventional Ohmic drain (OD) contact, a lower on-resistance (R_on) of 2.1 kΩ mm is achieved for variable channel lengths. Physics-based TCAD simulation is performed to validate the turn-on characteristics of the Schottky electrode region and the improved R_on. Electric-field analysis in the off-state is conducted for both the OD and HSD devices. Furthermore, a record breakdown voltage (BV) of 2.8 kV is achieved, which is superior to the 1.7 kV of the compared OD device. Our results show that the proposed HSD contact with a further optimized design can be a promising drain electrode scheme for α-Ga₂O₃ power MOSFETs. Full article

In this paper, AlGaN/GaN high-electron-mobility transistors (HEMTs) with ohmic etching patterns (OEPs) “fabricated to improve device radio frequency (RF) performance for Ka-band applications” are reported. The fabricated AlGaN/GaN HEMTs with OEP structures were used to reduce the source and drain resistances (R_s and R_d) for RF performance improvements. Within the proposed study using 1 μm hole, 3 μm hole, 1 μm line, and 3 μm line OEP HEMTs with 2 × 25 μm gate widths, the small signal performance, large signal performance, and minimum noise figure (NF_min) with optimized values were measured for 1 μm line OEP HEMTs. The cut-off frequency (f_T) and maximum oscillation frequency (f_max) value of the 1 μm line OEP device exhibited optimized values of 36.4 GHz and 158.29 GHz, respectively. The load–pull results show that the 1 μm line OEP HEMTs exhibited an optimized maximum output power density (P_{out, max}) of 1.94 W/mm at 28 GHz. The 1 μm line OEP HEMTs also exhibited an optimized NF_min of 1.75 dB at 28 GHz. The increase in the contact area between the ohmic metal and the AlGaN barrier layer was used to reduce the contact resistance of the OEP HEMTs, and the results show that the 1 μm line OEP HEMT could be fabricated, producing the best improvement in RF performance for Ka-band applications. Full article

Passivation is commonly used to suppress current collapse in AlGaN/GaN HEMTs. However, the conventional PECV-fabricated SiN_x passivation layer is incompatible with the latest process, like the “passivation-prior-to-ohmic” method. Research attention has therefore turned to high-temperature passivation schemes. In this paper, we systematically investigated the differences between the SiN_x/GaN interface of two high-temperature passivation schemes, MOCVD-SiN_x and LPCVD-SiN_x, and investigated their effects on the ohmic contact mechanism. By characterizing the device interface using TEM, we reveal that during the process of MOCVD-SiN_x, etching damage and Si diffuses into the semiconductor to form a leakage path and reduce the breakdown voltage of the AlGaN/GaN HEMTs. Moreover, N enrichment at the edge of the ohmic region of the LPCVD-SiN_x device indicates that the device is more favorable for TiN formation, thus reducing the ohmic contact resistance, which is beneficial to improving the PAE of the device. Through the CW load-pull test with drain voltage V_DS = 20V, LPCVD-SiN_x devices obtain a high PAE of 66.35%, which is about 6% higher than MOCVD-SiN_x devices. This excellent result indicates that the prospect of LPCVD-SiN_x passivation devices used in 5G small terminals will be attractive. Full article

β-Ga₂O₃, with excellent bandgap, breakdown field, and thermal stability properties, is considered to be one of the most promising candidates for power devices including field-effect transistors (FETs) and for other applications such as Schottky barrier diodes (SBDs) and solar-blind ultraviolet photodetectors. Ohmic contact is one of the key steps in the β-Ga₂O₃ device fabrication process for power applications. Ohmic contact techniques have been developed in recent years, and they are summarized in this review. First, the basic theory of metal–semiconductor contact is introduced. After that, the representative literature related to Ohmic contact with β-Ga₂O₃ is summarized and analyzed, including the electrical properties, interface microstructure, Ohmic contact formation mechanism, and contact reliability. In addition, the promising alternative schemes, including novel annealing techniques and Au-free contact materials, which are compatible with the CMOS process, are discussed. This review will help our theoretical understanding of Ohmic contact in β-Ga₂O₃ devices as well as the development trends of Ohmic contact schemes. Full article

This work reports, for the first time, the phenomenon of lateral Poole–Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current–voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole–Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole–Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires. Full article

AlGaN/GaN high electron mobility transistors (HEMTs) are regarded as promising candidates for a 5G communication system, which demands higher frequency and power. Source/drain ohmic contact is one of the key fabrication processes crucial to the device performance. Firstly, Au-contained metal stacks combined with RTA high-temperature ohmic contact schemes were presented and analyzed, including process conditions and contact formation mechanisms. Considering the issues with the Au-contained technique, the overview of a sequence of Au-free schemes is given and comprehensively discussed. In addition, in order to solve various problems caused by high-temperature conditions, novel annealing techniques including microwave annealing (MWA) and laser annealing (LA) were proposed to form Au-free low-temperature ohmic contact to AlGaN/GaN HEMT. The effects of the annealing method on surface morphology, gate leakage, dynamic on-resistance (R_ON), and other device characteristics are investigated and presented in this paper. By using a low-temperature annealing atmosphere or selective annealing method, gate-first Si-CMOS compatible AlGaN/GaN HEMT technology can be realized for high frequency and power application. Full article

An inter-layer dielectric (ILD) deposition process to simultaneously form the conductive regions of self-aligned (SA) coplanar In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) is demonstrated. N⁺-IGZO regions and excellent ohmic contact can be obtained without additional steps by using a magnetron sputtering process to deposit a SiO_x ILD. The fabricated IGZO TFTs show a subthreshold swing (SS) of 94.16 mV/decade and a linear-region field-effect mobility (μ_FE) of 23.06 cm²/Vs. The channel-width-normalized source/drain series resistance (R_SDW) extracted using the transmission line method (TLM) is approximately as low as 9.4 Ω·cm. The fabricated ring oscillator (RO) with a maximum oscillation frequency of 1.75 MHz also verifies the applicability of the TFTs. Full article

This paper presents a new field-effect sensor called open-gate junction gate field-effect transistor (OG-JFET) for biosensing applications. The OG-JFET consists of a p-type channel on top of an n-type layer in which the p-type serves as the sensing conductive layer between two ohmic contacted sources and drain electrodes. The structure is novel as it is based on a junction field-effect transistor with a subtle difference in that the top gate (n-type contact) has been removed to open the space for introducing the biomaterial and solution. The channel can be controlled through a back gate, enabling the sensor’s operation without a bulky electrode inside the solution. In this research, in order to demonstrate the sensor’s functionality for chemical and biosensing, we tested OG-JFET with varying pH solutions, cell adhesion (human oral neutrophils), human exhalation, and DNA molecules. Moreover, the sensor was simulated with COMSOL Multiphysics to gain insight into the sensor operation and its ion-sensitive capability. The complete simulation procedures and the physics of pH modeling is presented here, being numerically solved in COMSOL Multiphysics software. The outcome of the current study puts forward OG-JFET as a new platform for biosensing applications. Full article

The oxygen plasma surface treatment prior to ohmic metal deposition was developed to reduce the ohmic contact resistance (R_C) for AlGaN/GaN high electron mobility transistors (HEMTs) on a high-resistive Si substrate. The oxygen plasma, which was produced by an inductively coupled plasma (ICP) etching system, has been optimized by varying the combination of radio frequency (RF) and ICP power. By using the transmission line method (TLM) measurement, an ohmic contact resistance of 0.34 Ω∙mm and a specific contact resistivity (ρ_C) of 3.29 × 10^–6 Ω∙cm² was obtained with the optimized oxygen plasma conditions (ICP power of 250 W, RF power of 75 W, 0.8 Pa, O₂ flow of 30 cm³/min, 5 min), which was about 74% lower than that of the reference sample. Atomic force microscopy (AFM), energy dispersive X-ray spectroscopy (EDX), and photoluminescence (PL) measurements revealed that a large nitrogen vacancy, which was induced near the surface by the oxygen plasma treatment, was the primary factor in the formation of low ohmic contact. Finally, this plasma treatment has been integrated into the HEMTs process, with a maximum drain saturation current of 0.77 A/mm obtained using gate bias at 2 V on AlGaN/GaN HEMTs. Oxygen plasma treatment is a simple and efficient approach, without the requirement of an additional mask or etch process, and shows promise to improve the Direct Current (DC) and RF performance for AlGaN/GaN HEMTs. Full article