Optimization of Contact Resistance and DC Characteristics for AlGaN/GaN HEMTs Utilizing Sub-10 nm Nanohole Etching

Abstract

In this paper, the contact resistance of AlGaN/GaN high electron mobility transistor (HEMT) was improved by introducing nanoscale hole arrays in ohmic regions, and the DC characteristics of the conventional structure and nanohole etching structure for HEMTs were measured for comparison. Sub-10 nm nanoholes were patterned on the ohmic area surface of AlGaN using electron beam lithography and a low-temperature short-time development. Various dwell times of e-beam exposure from 5 to 30 μs were investigated and the corresponding contact resistance of the nano hole etching structure and planar structure were compared by the transmission line model (TLM) method. We observed a reduced contact resistance from 1.82 to 0.47 Ω-mm by performing a dwell time of 5 μs of exposure for nanohole formation compared to the conventional structure. Furthermore, the DC characteristics demonstrate that the maximum drain current for HEMTs was enhanced from 319 to 496 mA/mm by utilizing this optimized ohmic contact. These results show that devices with sub-10 nm nanohole ohmic contacts exhibit an improved contact resistance over the conventional structure, optimizing device performance for HEMTs, including a lower on-resistance and higher maximum drain current.

1. Introduction

AlGaN/GaN HEMT, one of the representative structured transistors in the third-generation semiconductor technology, provides many advantageous properties over silicon technology, such as a large critical electric field, high electron mobility, high saturation current, and an excellent temperature capability [1,2,3,4], due to its wide band gap and two-dimension electron gas (2DEG) density. Such outstanding performance makes the HEMT device a highly anticipated candidate in future high-power and high-frequency applications [5,6,7,8].

Low contact resistance is vital for HEMTs and ensures that the device meets the desired performance, including a high current density, low on-resistance, lower resistance heating, and low power loss, particularly regarding power electronics and high-frequency applications [9,10]. For RF devices, frequency characteristics are related to the connect resistance and transconductance in transistors [11]. For power devices, the low channel resistance of the on-state is essential to reduce the power device loss, which is strongly correlated with the series resistance induced by ohmic contacts [12]. To reduce the contact resistance of GaN-based HEMTs, various metallization stacks have been proposed for ohmic contact such as Ti/Al/Ti/Au, Ti/Al/Ni/Au, Ti/Al/Mo/Au, and Ti/Au/Al/Ni/Au [13,14,15,16]. Performing ion implantation to dope source and drain regions has also been found to be an effective strategy to reduce contact resistance [17]. To achieve a low contact resistance and high-frequency characteristics, a regrown n+ GaN contact with Si doping on the ohmic region has been demonstrated with a contact resistance of 0.16 Ω-mm [18]. However, reducing resistance for GaN devices is still challenging because of the complex fabrication process and the high annealed temperature required for doping techniques. In recent years, a new structure incorporating etching patterns in the ohmic area was proposed to reduce ohmic contact resistance. In 2015, Takei et al. proposed an uneven AlGaN structure to reduce ohmic contact resistance on HEMTs. Through 2D device simulations, an increase in 2DEG concentration can be observed near the edge regions of the uneven AlGaN structure due to the fringing effect [19]. They experimentally confirm that lower contact resistance can be achieved by introducing ohmic contacts with uneven structures.

In general, an increase in the thickness of the AlGaN layer in AlGaN/GaN HEMTs leads to an enhancement in the sheet carrier density of the 2DEG in the GaN channel. This enhancement subsequently results in a decrease in the contact resistance associated with the 2DEG (R_c2DEG) [20]. However, a thicker AlGaN layer also contributes to an increase in the contact resistance of the AlGaN layer itself (R_cAlGaN), thereby elevating the overall contact resistance. Consequently, an optimal thickness range for the AlGaN layer, typically between 10 and 25 nm [21], is essential for AlGaN/GaN HEMTs. By implementing an uneven AlGaN structure in ohmic regions characterized by various etching patterns, this inherent trade-off regarding the AlGaN layer thickness can be effectively mitigated compared to conventional flat AlGaN structures. To analyze the effect of pattern size on device performance, Wang et al. fabricated HEMT devices with patterned etching holes with apertures of 0.8, 1.6, and 3 μm [22], and found that 0.8 μm exhibited the lowest contact resistance. It can be explained by forming more side areas on the surface of AlGaN and N-vacancies, which enhances the tunneling current and reduces the contact resistance between the AlGaN and electrodes. Benakaprasad et al. performed extensive investigation on contact resistance and surface roughness with varying parameters including etching pattern, etching depth, annealed temperature, and a planar/nonplanar ohmic metallization [23]. You et al. investigated the influence of different recess hole array arrangements on ohmic contact and found that the device with a gradually increasing hole pattern of 1/3/5 μm demonstrates a superior improvement in contact resistance [24]. To enhance the frequency characteristics, Lee et al. recently fabricated AlGaN/GaN HEMTs with 1 μm line ohmic etching patterns and optimized the RF performance for Ka-band applications [25].

In contrast to the studies mentioned above that utilized microscale patterned uneven structures, this work introduces the technique of sub-10 nm nanohole etching within the ohmic region to reduce contact resistance for HEMTs. The nanohole etching pattern was designed with dimensions smaller than 20 nm, which aims to ensure that the hole sizes are smaller than the spacing between interface traps. These interface traps, with a density of 10¹² eV⁻¹cm⁻² [26], generally arise from threading dislocations caused by the epitaxial growth process and the mismatch between GaN and sapphire [27]. The schematic diagram of nanohole etching patterns is shown in Figure 1.

The nanoscale hole patterns were formed utilizing electron beam lithography and low-temperature short-time development technology. The nanohole apertures can be shrunk effectively by lowering the development rate in a low-temperature environment [28] using various dwell times of e-beam exposure. We performed the TLM method to investigate the contact resistance of the conventional structure and the nanohole etching structure for comparison. Finally, the DC characteristics of AlGaN/GaN HEMTs were measured to verify the effectiveness of the sub-10 nm nanohole ohmic contacts. The results indicated that with the 5 μs dwell times for forming the nanohole etching structure, the contact resistance showed the best improvement from 1.82 to 0.47 Ω-mm. The fabricated HEMT demonstrated a higher drain current density and lower on-resistance.

2. Materials and Methods

The Al_0.18Ga_0.82N/GaN HEMT heterostructure wafer was grown by metal-organic chemical vapor deposition (MOCVD) on a 2-inch (0001) sapphire substrate. The well-established manufacturing processes, chemical stability, and cost-effectiveness of sapphire substrates make them a prevalent choice for optoelectronic devices and electronic devices [29,30]. Epitaxial layers consisted of a GaN buffer layer (25 nm), an un-doped GaN (3 μm), an AlGaN barrier layer (19 nm), and a GaN cap layer (2 nm) from bottom to top. All contact resistance and DC characteristics of samples using different pattern design parameters were measured from the substrate having the same structural arrangement. Mesa isolation was carried out using inductively coupled plasma-reactive ion etching (ICP-RIE) for electrical isolation between devices.

Prior to the nanohole etching process, the wafer was cleaned with acetone, methanol, and deionized water, each for 5 min, to remove surface impurities and organic residues. Subsequently, it was dried by baking for 1 min on a hot plate. In the context of preparing the surface, it is relevant to note the influence of the epitaxial process used for growing GaN on sapphire substrates. The interface defect density, which is typically around 10¹² eV⁻¹cm⁻² as per Ref. [26], leads to an average area of approximately 10² nm² between interface defects. This density is crucial for understanding the impact of threading dislocations and their role in the efficacy of the etching process. In our experiment, we aim to design the size of nanoholes to be less than 20 nm to improve the contact resistance. To generate the sub-10 nm nanoscale hole patterns at the source and drain ohmic regions, e-beam lithography, and low-temperature short-interval development technology were utilized in subsequent experiments. Firstly, ZEP520A (Zeon Corp., Tokyo, Japan), a positive tone resist, was diluted in ZEP-A with a ratio of 1:1. The diluted ZEP520A had a thickness of 100 nm. The resist was then spin-coated on the substrate and baked at 180 °C for 2 min. Then, nanohole patterns that were symmetrically arranged with a period of 60 nm were designed and written on the resist using e-beam lithography. The dwell times of the e-beam were set to 5 μs, 10 μs, 15 μs, 20 μs, 25 μs, and 30 μs, respectively, which determine the size of the pattern after the development process. In addition to precisely controlling the dwell times of electron beams to create nanoscale hole patterns smaller than 20 nm, it is also crucial to slow down the development rate of the resist in the developer. A prior study has shown that low-temperature conditions can effectively decrease the development rate of ZEP520A resists when using ZEP-N50 developers (Zeon Corp., Tokyo, Japan). Line widths of less than 15 nm have been achieved by implementing a development process at a temperature of −10 °C for a duration of 5 s, in which each line was written by a single column of the incident e-beam spot [28]. Therefore, in this work, we utilized ZEP-N50 to develop the ZEP520A resist at −10 °C for 5 s to obtain a sub-10 nm nanohole pattern. The AlGaN layer at ohmic regions was then etched by the ICP-RIE system using the Cl₂/BCl₃ gas mixtures for 10 s to form recess holes. The remaining thickness of AlGaN was 10 nm. The fabrication of nanohole etching patterns was completed and the wafer was put in ZDMAC (Zeon Corp., Tokyo, Japan) to strip resist followed by a cleaning process with acetone and deionized water. Before the ohmic metallization, a diluted hydrochloric acid (HCl) solution was used to remove the native oxide layer on the AlGaN surface.

To form ohmic metals, the metal stack of Ge/Ti/Al/Ti/Au was deposited using an e-beam evaporation system (E-gun) with a thickness of 10/20/100/55/105 nm. The source and drain ohmic contacts were then completed by Rapid thermal annealing (RTA) at 850 °C for 30 s in N₂ ambient. Finally, Ni/Au was deposited for gate metal with a thickness of 30/80 nm. The gate length (L_G), gate-to-drain distance (L_GD), and gate-to-source distance (L_GS) of the HEMTs were 1.5 µm, 2 µm, and 2.5 µm, respectively. The schematic cross-section of AlGaN/GaN HEMTs with nanohole etching ohmic contacts is depicted in Figure 2.

3. Results and Discussion

3.1. Sub-10 nm Nanohole Patterns

Figure 3a demonstrates the scanning electron microscope (SEM) image of nanohole patterns on the surface of AlGaN using a dwell time of 35 µs after performing e-beam lithography and development at a low temperature of −10 °C for 5 s. It can be seen that the size of the nanoholes ranged from 11.5 to 15.5 nm. It indicated that the sub-10 nm nanohole patterns can be generated successfully on the AlGaN surface by selecting appropriate dwell times and developing rapidly in a low-temperature environment.

Due to the substantial lattice mismatch and differential thermal expansion coefficients between the sapphire substrate and GaN, an elevated defect density is typically induced at the interface of the GaN epitaxial layer, estimated between 10¹² and 10¹³ eV⁻¹cm⁻² [31,32,33]. Assuming the interface trap density represents the number of traps per square centimeter, and considering only the planar dimensions, the average area A occupied by each trap is the reciprocal of the trap density, yielding A = 10⁻¹² cm² for a trap density of 10¹² cm⁻². Further, if we assume that the area occupied by each trap is equated to a square, the distance between each trap, defined as the side length of the square, can be derived from the square root of the area A. Let s denote the side length, with s = $\sqrt{A}$= 10⁻⁶ cm, indicating that the average distance between each trap is approximately 0.1 μm. This spacing is critical as it influences the sparsity or density of the interface traps, which in turn significantly impacts the electrical performance of semiconductor devices. Conversely, when the density of interface traps reaches 10¹³ cm⁻², the average distance between individual traps diminishes to about 0.0316 μm, or equivalently 31.6 nm. This reduction in distance indicates a higher density of traps, potentially leading to different electronic properties.

Therefore, we adjusted the dwell times of the electron beam exposure to a range of 5 to 30 μs and combined this with low-temperature short-interval development technology to fabricate etching holes smaller than 31.6 nm. These nanoscale etching holes formed in the ohmic regions on the AlGaN surface, due to their sub-10 nm dimensions being smaller than the average distance between interface traps, thereby enhancing the efficiency of electron tunneling to the metal electrodes, further reducing contact resistance and improving the electrical properties of the devices. In subsequent sections, we will explore the effects of different dwell times on improving sample contact resistance using the TLM method.

3.2. Contact Resistance Evaluation with TLM Measurement

The contact resistance measurement was determined using TLM patterns with spacings ($d$) of 12, 14, 18, and 26 µm, and the width ($W$) was 100 µm. Measurements of total resistance ($R_T$) across each contact pair were measured to construct the TLM graph [34] using a four-point probe arrangement, as shown in Figure 4. The measured $R_T$ can be expressed by Equation (1) as follows:

$$R_T=\frac{{\rho }_{s}d}{W}+2R_c\approx \frac{{\rho }_{s}d}{W}+2\frac{{\rho }_s{L}_T}{W}=\frac{{\rho }_s}{W}\left(d+2L_T\right)$$

(1)

$${L_T}^2=\frac{{\rho }_c}{{\rho }_s}$$

where ${\rho }_s$ is the sheet resistance, $L_T$ is the transfer length, and R_c and ${\rho }_c$ are contact resistance and specific contact resistance, respectively. From the graph, the parameter 2R_c can be obtained from the intercept of the y-axis by extrapolating back to $d$ = 0. The comparison of the R_c and ${\rho }_c$ extracted from the TLM data between the conventional structure and patterned etching structures on different dwell times is listed in

Table 1. Contact resistance and specific contact resistance of samples using different dwell times.

Dwell Time (µs)	Rc (Ω-mm)	ρc (Ω-cm2)
Conventional	1.82	5.86 × 10−4
5	0.47	1.36 × 10−5
10	0.52	1.65 × 10−5
15	0.49	1.47 × 10−5
20	0.54	1.66 × 10−5
25	0.72	1.89 × 10−5
30	0.69	1.81 × 10−5

.

From measurement results listed in Table 1, the sample using a dwell time of 5 µs exhibited the lowest contact resistance of 0.47 Ω-mm and a specific contact resistance of 1.36 × 10⁻⁵ Ω-cm², which was significantly reduced compared to the sample without etching holes (1.82 Ω-mm and 5.86 × 10⁻⁴ Ω-cm²). Furthermore, it can be seen that the contact resistance was reduced when the dwell times were modulated from 30 to 5 µs. These measurement outcomes demonstrate the efficacy of implementing sub-10 nm nanohole etching within the ohmic regions, which significantly contributes to lowering the contact resistance. Figure 5 illustrates the contact resistance for all the samples using dwell times of 5, 10, 15, 20, 25, and 30 µs. It can be found that when the nanohole pattern was fabricated using dwell times of 25 and 30 µs, the contact resistance was obtained at 0.72 and 0.69 Ω-mm, respectively, which decreased by 60% compared to the conventional structure. To form nanohole patterns with smaller sizes to improve contact resistance further, the dwell times were reduced to under 20 µs. The results showed that when the dwell times were reduced to 10 from 20 µs, the contact resistance could be further improved to 0.49–0.54 Ω-mm, demonstrating an improvement of about 71%. The best performance in contact resistance was found to be 0.47 Ω-mm from the sample using a dwell time of 5 µs as described above. The contact resistance and specific contact resistance of samples using 5 µs dwell times improved by 74% and 97%, respectively, compared to the conventional structure without patterned ohmic contacts.

The observed improvement in contact resistance can be attributed to the significant increase in the sidewall area between the ohmic metal and AlGaN. Facilitated by the nanoscale etching holes, an enormous amount of Ti can chemically react with the AlGaN surface during the thermal annealing of the ohmic metal, forming an increased quantity of TiN and N vacancies [22]. This lowers the barrier height between the ohmic metal and semiconductor, enhancing the electron transport capability and tunneling current, thereby reducing contact resistance. Furthermore, we consider the threading dislocations that occur during the growth of GaN layers on sapphire substrates. These dislocations tend to extend to the surface during the epitaxial growth, thus, when metal-semiconductor contacts are formed, a high density of interface defects is created [26,27]. Such positively charged defect states can capture electrons during their transport, significantly reducing current flow and adversely affecting the contact resistance of the device. Therefore, by fabricating sub-10 nm nanoscale etching holes in the ohmic region and designing a pattern with a density of nanoholes greater than that of the interface defects, we aim to mitigate the negative impact of interface defect density on electron transport and ohmic contact resistance. In this experiment, we leveraged the findings from previous research [28], which demonstrated the formation of a single spot in the photoresist of ZEP520A within a mere 5 µs development duration time. By developing the resist in a low-temperature environment at −10 °C and combining this with dwell times ranging from 5 to 30 µs, we successfully fabricated sub-10 nm nanohole patterns in the AlGaN ohmic region and significantly improved the contact resistance between ohmic metal and AlGaN.

3.3. Effect of Etching Holes on Different Substrate Materials

We further investigated the impact of different etch hole sizes on the reduction of R_c in samples when using different substrate materials (Si, Sapphire, SiC). Figure 6a displays the R_c of AlGaN/GaN devices with varying etch hole sizes (0.8, 1.6, and 3.0 μm) grown on sapphire substrates [22]. The conventional structure had an R_c of 0.46 Ω-mm. It was observed that the R_c was 0.218 Ω-mm for etch hole sizes of 3.0 μm, and when the etch hole size was further reduced to 0.8 μm, the R_c was 0.187 Ω-mm. Thus, reducing the hole size from 3.0 μm to 0.8 μm led to an additional 14% decrease in the R_c, effectively reducing the ohmic contact value by 56% compared to the conventional structure. Figure 6b illustrates the R_c of AlGaN/GaN devices grown on Si substrates [24] with various etch hole sizes (1, 2, 3, 4, 5, and 6 μm). The traditional structure had an R_c of 2.66 Ω-mm. It can be seen that the R_c was 2.10 Ω-mm for etch pit sizes of 3 μm. When reduced further to 1 μm, the Rc was 1.66 Ω-mm, indicating a 21% further reduction in the R_c. Compared to the traditional structure, this effectively reduced the ohmic contact value by about 38%. Additionally, only minor changes in contact resistance were observed when the etch hole sizes were 4, 5, and 6 μm. Significant reductions in contact resistance occurred only when the etch hole sizes were below 3 μm.

Figure 6c shows the R_c of AlGaN/GaN devices grown on SiC substrates [35] with etch hole sizes 0.5, 1, 2, and 3 μm. The conventional structure had an R_c of 0.4 Ω-mm. Notably, the R_c was 0.35 Ω-mm for etch holes of 3 μm and decreased to 0.14 Ω-mm when reduced to 1 μm, indicating a substantial 60% reduction. This was an effective 65% decrease in the ohmic contact value compared to the traditional structure. It can be seen that AlGaN/GaN devices with etched ohmic contacts grown on SiC substrates demonstrated a greater reduction in ohmic contact resistance when hole sizes were reduced, compared to those grown on Si and Sapphire substrates. Therefore, we consider that the reduction in etch hole size and the increase in sidewall area are not the only factors in reducing device ohmic contact. The interface defect density produced when growing GaN epitaxial layers on different substrates also affects the effectiveness of introducing etch holes in reducing contact resistance.

From the discussion in Section 3.1, it can be deduced that assuming a GaN epitaxial layer grown on Sapphire has an interface trap density of 10¹³ cm⁻², the average distance between defects is approximately 31.6 nm. Generally, GaN layers grown on SiC, due to better lattice matching, have lower interface defect densities compared to Si and Sapphire [36,37]. Thus, micrometer-level etch holes can significantly enhance the electrical resistance properties of HEMT-on-SiC devices. However, for HEMT-on-Si or HEMT-on-Sapphire devices, further reduction in etch pit sizes to the nanometer scale is necessary to mitigate the impact of higher interface defect densities on electron transport capabilities, maximizing the benefits of introducing etched ohmic contacts in improving the electrical performance of HEMT devices.

Figure 6d presents the R_c of AlGaN/GaN devices grown on Sapphire substrates with proposed sub-10 nm etch holes. This study investigates the effects of different electron beam dwell times on improving device contact resistance. The conventional structure had an R_c of 1.82 Ω-mm. It was observed that when the dwell time was 30 and 25 μs, the R_c ranged between 0.69 and 0.72 Ω-mm. When the dwell time was reduced to 5 μs, the Rc was 0.47 Ω-mm, indicating a further reduction of approximately 32%. Compared to the traditional structure, this represents a significant reduction of about 74% in ohmic contact value. The results suggest that utilizing sub-10 nm nano-etched holes in the ohmic regions can further improve the resistance characteristics of HEMT-on-Sapphire devices.

3.4. DC Characteristics of AlGaN/GaN HEMTs Utilizing Sub-10 nm Nanohole Etching

Due to the superior improvement in contact resistance, the sample with a dwell time of 5 µs was adopted to fabricate the HEMT device to optimize the performance. The electrical characteristics for AlGaN/GaN HEMTs fabricated in this work were measured using the Keysight B1500A semiconductor parameter analyzer, sourced from Keysight Technologies, Inc., Santa Rosa, CA, USA. As shown in Figure 7, the I_DS-V_DS Characteristics of the optimal nanohole etching condition (5 µs dwell time) and the conventional device were demonstrated together for comparison. The maximum drain current density (I_D,max) was 496 mA/mm for the patterned etching and 319 mA/mm for the conventional structure, respectively. An enhancement in the drain current density by 55% was observed, which can be attributed to the reduction in the device’s contact resistance. Furthermore, the on-resistance (R_on) of the device was reduced from 1.03 Ω-mm to 0.90 Ω-mm. These results show that introducing etching patterns in the ohmic region can help enhance the fringing effect and augment the side area interaction between the metal and AlGaN [19,22]. This modification is beneficial in reducing the contact resistance, contributing to a higher drain current density and a lower on-resistance of AlGaN/GaN HEMTs.

Figure 7b shows the I_DS(log)-V_GS characteristics of devices utilizing nanohole etching and conventional structures. It was observed that the leakage current of the device designed with nanoscale contacts decreased by nearly an order of magnitude. However, since an oxide or insulating layer had not yet been applied at the gate region, the leakage current remained excessively high. Thus, future efforts should focus on developing MOS or MIS-HEMT devices to further mitigate the leakage current issue. Figure 8a shows the I_D-V_GS characteristics of the devices at V_DS = 6 V. The threshold voltage exhibited a slightly negative shift and was obtained at −3.54 V for the nanohole etching device. It was found that compared with the conventional structure, the transduction characteristics (g_m) of the device greatly improved, from a gm of 80 mS/mm to 135 mS/mm with an increase of 68%, as shown in Figure 8b. This indicates that devices with sub-10 nm nanohole etching have better gate voltage control of the drain current. As high-frequency applications continue to proliferate, optimizing the g_m is crucial for enhancing the operating frequencies of HEMT devices. The RF performance enhancement of HEMTs, facilitated by patterned etching of ohmic contacts, has been experimentally validated in previous studies [25,32]. It demonstrates that a higher cut-off frequency (f_T) and maximum oscillation frequency (fmax) [25], along with an enhanced power-added efficiency (PAE) [35], can be achieved by patterned etching in the ohmic region.

To maximize the effectiveness of patterned etching ohmic contact for reducing contact resistance and thus enhancing the performance and stability of HEMT devices, it is crucial to identify the optimal etching pattern morphology and process parameters. To date, the exploration of etching patterns to minimize ohmic contact resistance has pursued several directions, including the analysis of various pattern morphologies and arrangements [19,23,24,25], pattern dimensions [22,24,25,32], and etching depths [22,23,24]. Among the diverse etching pattern morphologies paired with different arrangements, commonly utilized ones are symmetrically arranged holes [19,22,23,24,32,34], closely packed holes [38], and lines in the direction of current flow [19,25]. Additionally, some groups have crafted grid-like patterns composed of horizontal and vertical lines [23] and patterns where the holes gradually increase in size from small to large [24], in which You et al. investigated the effects of various hole array arrangements on ohmic contact, confirming that devices with gradually increasing hole patterns of 1/3/5 μm demonstrated lower contact resistance compared to those with uniformly sized patterns. This reduction in contact resistance may be related to the shorter electron transport lengths (L_T) facilitated by the increasing hole size, enabling current to reach electrodes via the shortest path [24].

Regarding the selection of pattern dimensions, patterned etching ohmic contact structures are predominantly in the micrometer scale, with hole diameters or side lengths mostly falling between 0.5 and 1.5 μm, while the widths of line patterns range from 1 to 5 μm. The study in [22], examining the impact of three different hole sizes (0.8, 1.6, 3 μm) on contact resistance, attributed the lowest contact resistance value of 0.46 Ω-mm for 0.8 μm holes to the increased sidewall area created by patterned etching on the AlGaN surface. This increased sidewall area facilitates more extensive chemical reactions between the ohmic metal and AlGaN during the annealing process, resulting in more TiN and N vacancies, thus enhancing the tunneling current and reducing contact resistance. To achieve a high RF performance in AlGaN/GaN HEMT-on SiC, Lu et al. analyzed the effect of six different hole diameters (0.5, 1.0, 1.5, 2.0, 2.5, and 3.0 μm) on contact resistance, demonstrating a significant reduction in contact resistance with decreasing dimensions. The smallest 0.5 μm holes achieved the lowest contact resistance of 0.12 Ω-mm, marking a 70% improvement and effectively enhancing RF efficiency and power characteristics [35].

Table 2. Comparison of DC characteristics of AlGaN/GaN HEMTs.

HEMT	ID,max (mA/mm)	Ron (Ω-mm)	gm (mS/mm)
conventional	319	1.03	80
nanohole etching	496	0.90	135

lists the pattern and contact resistance of previous studies using a patterned ohmic contact (POC) structure in AlGaN/GaN heterostructures. Different from previous studies that focused on micro-patterned ohmic structures, in this work, we fabricated symmetrically arranged etching nanohole structures on the sub-10 nm scale and improved the contact resistance from 1.82 to 0.47 Ω-mm, achieving a 74% improvement. Further optimization of the etching depth and hole arrangement in nanohole etching patterns is still required. To further reduce contact resistance by ohmic etching patterns, designing optimal etching pattern morphologies is essential and can be achieved with etching patterns that can increase the contact side area between the metal and AlGaN, arrangements that optimize the current path to reach the electrodes, and optimal etching depths to enhance fringing effects.

Furthermore, selecting optimized process parameters is also required to form effective ohmic contacts between the metal and the semiconductor. Generally, annealing temperatures range between 800 and 900 °C to facilitate good diffusion and chemical reactions between the metal and AlGaN/GaN heterostructure [38]. Nonetheless, the morphology of both surfaces and sidewalls often deteriorates during the annealing process, and the annealing temperature critically affects the size and density distribution of the TiN phase grains. Therefore, optimizing the annealing temperature for uneven AlGaN structures is indispensable. Most devices with patterned etching AlGaN ohmic contacts use a Ti/Al/Ni/Au metal stack, with annealing temperatures set between 790 and 850 °C. In [23,38], the impact of annealing temperature on patterned etching ohmic contacts was investigated by using different annealing temperatures after ohmic metallization. The results showed that the optimized annealing temperature for AlGaN/GaN heterostructures with etched hole arrays was 40 °C lower than that for conventional structures [38]. Additionally, to address the issue of current collapse, some groups have used an Au-free Ti/Al/Ti for ohmic contacts with a low annealing temperature of 550 °C, creating AlGaN/GaN HEMTs with a low thermal budget and reduced contact resistance [33,34]. In this work, we used an 850 °C annealing temperature for the ohmic metal for 30 s. Given that the annealing temperature can significantly impact contact resistance increased from 0.2 to around 0.35 Ω-mm when the annealing temperature increased from 800 to 820 °C, further optimization of the annealing temperature and annealing time for nanoscale patterned ohmic contacts is necessary to allow the ohmic metal to effectively infiltrate the etched holes in AlGaN and achieve better TiN phase formation. For the use of a patterned etching ohmic contact to reduce contact resistance, further investigations on the optimization of etching pattern morphology and process parameters are indispensable to enhancing the performance and stability of devices and unlocking the potential of AlGaN/GaN HEMTs in high-power and high-frequency applications.

Table 3. The pattern and contact resistance of previous works using patterned ohmic contact (POC).

Pattern	Size (μm)	Conventional Rc (Ω-mm)	POC Structure Rc (Ω-mm)	Ref.	Year
Horizontal line	5	-	5.86	[19]	2015
Close hole	1	-	0.20	[38]	2017
Square hole	0.8	0.46	0.18	[22]	2017
Square hole	0.5	0.40	0.12	[35]	2018
Grid line	2	0.368	0.278	[23]	2020
Graded hole	1/3/5	-	0.89	[24]	2021
Square hole	1.5	1.57	0.56	[39,40]	2021
Horizontal line	1	0.429	0.154	[25]	2024
Square hole	<0.02 × 0.02	1.82	0.47	this work

lists the optimal contact resistance of previous works using patterned ohmic contact with different patterns and dimensions.

4. Conclusions

In conclusion, this study demonstrates a significant improvement in the contact resistance of AlGaN/GaN HEMTs through the introduction of nanoscale hole arrays in the ohmic area. Comparative analyses between the conventional structure and the nanohole etching structure were conducted, revealing notable enhancements in the DC characteristics of the HEMTs. The implementation of sub-10 nm nanoholes, patterned using electron beam lithography and low-temperature short-time development, was instrumental in this advancement. Our investigation into various dwell times for e-beam exposure, ranging from 5 to 30 μs, indicated that a dwell time of 5 μs for nanohole formation was optimal. This resulted in a reduction in contact resistance from 1.82 to 0.47 Ω-mm, compared to the conventional structure. The DC characteristics of the HEMTs showed an increase in the maximum drain current from 319 to 496 mA/mm and transconductance from 80 to 135 mS/mm. These findings highlight that devices with sub-10 nm nanohole ohmic contacts not only exhibit a lower contact resistance but also enhance overall device performance, including a lower on-resistance and a higher maximum drain current.