Search Results (28)

Spin–Orbit Torque Magnetic Random-Access Memory (SOT-MRAM)-based in-memory computing (IMC) offers a transformative solution for energy-efficient edge intelligence, yet the deployment of robust online learning remains challenging due to memristive non-idealities and the “memory wall” inherent in Von Neumann architectures. In this work, we propose a Tiki-Taka-inspired SOT-MRAM IMC architecture with a cross-layer co-design that decouples gradient accumulation and weight storage. A time-multiplexing (Time-MUX) strategy is introduced to alleviate interconnect overhead, achieving over 28 times area reduction while maintaining comparable energy consumption to spatial mapping schemes. By integrating a canted-type x SOT-MTJ compact model into the NeuroSim framework, we perform system-level evaluation under realistic constraints. The results reveal that the proposed approach enables an effective trade-off between area, latency, and accuracy. Furthermore, the 1-bit/4-bit hybrid precision scheme achieves accuracy comparable to 8-bit configurations with reduced hardware cost while supporting a five-year cumulative write load of 1.87 × 10⁷ cycles, significantly surpassing the endurance limits of conventional memristor devices. This work provides key insights into cross-layer optimization and establishes a practical design framework for resource-constrained edge learning systems. Full article

As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) of the magnetic tunnel junction (MTJ) in STT-MRAM can limit the achievable read accuracy. We implemented 2-bit channel quantization for error-correcting code (ECC) schemes and explored the trade-offs between improved read accuracy and factors such as circuit area, power consumption, and latency. The proposed quantization scheme consists of a sensing amplifier-based 2-bit quantizer and MTJ resistor-based soft-decision thresholds. Compared to 1-bit channel quantization using the Bose–Chaudhuri–Hocquenghem (BCH) code, the proposed 2-bit quantization architecture achieves a fourfold reduction in frame error rate (FER) from $8.0\times {10}^{-4}$ to $2.0\times {10}^{-4}$ when paired with polar codes and successive cancellation (SC) decoding. Additionally, this approach results in decoding complexity that is only 1/13th of that required for BCH at a 0.7 code rate. Full article

Asymmetric error characteristics in spin-transfer torque magnetic random-access memory (STT-MRAM), particularly the imbalance between logical ‘0’ and ‘1’ error probabilities, can significantly degrade system reliability under conventional modulation and error-correcting schemes. This issue is especially critical in sensor network applications, where STT-MRAM is widely adopted for its non-volatility, low standby power, and robustness under energy-constrained and intermittently active operation. Existing approaches typically optimize the detection threshold under the assumption of a fixed or equiprobable bit distribution, while sparse coding techniques impose a predefined imbalance without explicitly accounting for its interaction with threshold detection. In this paper, we formulate the bit error rate (BER) minimization problem as a joint optimization of the codeword bit distribution and the detection threshold over an asymmetric cascaded STT-MRAM channel. Analytical results reveal that the minimum BER is achieved when the error probabilities associated with transmitted ‘0’ and ‘1’ bits are balanced, which induces an intrinsic coupling between the optimal detection threshold and the codeword composition. Motivated by this insight, we propose a new family of threshold-matched probability codes (TMPCs), in which the proportion of logical ‘1’s in each codeword is explicitly designed to match the optimal detection threshold of the underlying channel. The proposed coding framework generalizes conventional sparse modulation by enabling adjustable bit distributions while preserving low-complexity linear encoding and syndrome-based decoding. Numerical evaluations demonstrate that the TMPC achieves consistently lower BERs than existing sparse and fixed-distribution coding schemes across a wide range of STT-MRAM operating conditions, particularly under severe write asymmetry and resistance variation. These results indicate that the proposed joint design offers a principled and flexible approach for improving reliability in STT-MRAM-based sensor networks and non-volatile memory systems. Full article

Defect categorization is essential to product quality assurance during the production of magnetic random access memory (MRAM). Nevertheless, traditional defect detection techniques continue to face difficulties in large-scale deployments, such as a lack of labeled examples with complicated defect shapes, which results in inadequate identification accuracy. In order to overcome these problems, we create the MARMset dataset, which consists of 39,822 photos and covers 14 common defect types for MRAM defect detection and classification. Furthermore, we present a baseline framework (GAGBnet) for MRAM defect classification, including a global attention module (GAM) and an attention-guided block (AGB). Firstly, the GAM is introduced to enhance the model’s feature extraction capability. Secondly, inspired by the feature enhancement strategy, the AGB is designed to incorporate an attention-guided mechanism during feature fusion to remove redundant information and focus on critical features. Finally, the experimental results show that the average accuracy rate of this method on the MARMset reaches 92.90%. In addition, we test on the NEU-CLS dataset to evaluate cross-dataset generalization, achieving an average accuracy of 98.60%. Full article

As an emerging type of non-volatile memory, magneto-resistive random access memory (MRAM) stands out for its exceptional reliability and rapid read–write speeds, thereby garnering considerable attention within the industry. The memory cell architecture of MRAM is centered around the magnetic tunnel junction (MTJ), which, however, is prone to interference from external magnetic fields—a limitation that restricts its application in demanding environments. To address this challenge, we propose an innovative open magnetic shielding structure. This design demonstrates remarkable shielding efficacy against both in-plane and perpendicular magnetic fields, effectively catering to the magnetic shielding demands of both spin-transfer torque (STT) and spin–orbit torque (SOT) MRAM. Finite element magnetic simulations reveal that when subjected to an in-plane magnetic field of 40 mT, the magnetic field intensity at the chip level is reduced to nearly 1‰ of its original value. Similarly, under a perpendicular magnetic field of 40 mT, the magnetic field at the chip is reduced to 2‰ of its initial strength. Such reductions significantly enhance the anti-magnetic capabilities of MRAM. Moreover, the magnetic shielding performance remains unaffected by the height of the packaging structure, ensuring compatibility with various chip stack packaging requirements across different layers. The research presented in this paper holds immense significance for the realization of highly reliable magnetic shielding packaging solutions for MRAM. Full article

With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases. Full article

In this work, we analyze the thermodynamic principles underlying modern data storage systems, including Random Access Memory (RAM), hard disk drive (HDD), flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and phase-change RAM (PCRAM), as well as other less well-known data storage mechanisms. The analysis is conducted in the context of data storage and processing in relation to Landauer’s principle, with special emphasis on hysteresis. Analogous to how heat engines are characterized by thermodynamic cycles, data storage systems are examined in terms of the hysteresis loop of their fundamental data unit. We explore the role of heat in data storage systems. Afterward, we introduce the concept of temperature gradient memory (TeGraM) along with a detailed layout of a realizable device. Experimental results demonstrating this technology are also presented. Full article

The exchange bias (EB) effect denotes a magnetic bias phenomenon originating from the interfacial exchange coupling at the ferromagnetic/antiferromagnetic materials, which plays an indispensable role in the functionality of various devices, such as magnetic random-access memory (MRAM) and sensors. Voltage control of exchange bias offers a promising pathway to significantly reduce device power consumption, effectively fostering the evolution of low-energy spintronic devices. The “magneto-ionic” mechanism, characterized by its operational efficiency, low energy consumption, reversibility, and non-volatility, provides innovative approaches for voltage control of exchange bias and has led to a series of significant advancements. This review systematically synthesizes the research progress on voltage control of exchange bias based on the magneto-ionic mechanism from the perspectives of ionic species, material systems, underlying mechanisms, and performance parameters. Furthermore, it undertakes a comparative evaluation of the voltage-controlled exchange bias by different ions, ultimately providing a forward-looking perspective on the future trajectory of this research domain. Full article

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article

Defects in the free layer are considered to be the main cause of the balloon effect, but there is little insight into the synthetic antiferromagnetic (SAF) layer. To address this shortcoming, in this work, an optimized SAF layer was introduced in the perpendicular magnetic tunneling junction (pMTJ) stack to eliminate the low-probability bifurcated-switching phenomenon. The results indicated that the Hf field in the film stack improved significantly from ~5700 Oe to ~7500 Oe. A magnetoresistive random access memory (MRAM) test chip was also fabricated with a 300 mm process, resulting in a significantly improved ballooning effect. The results also indicated that the switching voltage decreased by 18.6% and the writing energy decreased by 33.7%. In addition, the low-probability stray field along the x-axis was thought to be the main cause of the ballooning effect, and was experimentally optimized for the first time by enhancing the SAF layer. This work provides a new perspective on spin-flipping dynamics, facilitating a deeper comprehension of the internal mechanism and helping to secure improvements in MRAM performance. Full article

With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is $\times 2.43$. Full article

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area. Full article

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation. Full article

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin. Full article

We employ a fully three-dimensional model coupling magnetization, charge, spin, and temperature dynamics to study temperature effects in spin-orbit torque (SOT) magnetoresistive random access memory (MRAM). SOTs are included by considering spin currents generated through the spin Hall effect. We scale the magnetization parameters with the temperature. Numerical experiments show several time scales for temperature dynamics. The relatively slow temperature increase, after a rapid initial temperature rise, introduces an incubation time to the switching. Such a behavior cannot be reproduced with a constant temperature model. Furthermore, the critical SOT switching voltage is significantly reduced by the increased temperature. We demonstrate this phenomenon for switching of field-free SOT-MRAM. In addition, with an external-field-assisted switching, the critical SOT voltage shows a parabolic decrease with respect to the voltage applied across the magnetic tunnel junction (MTJ) of the SOT-MRAM cell, in agreement with recent experimental data. Full article