Search Results (16)

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the $g_m/I_D$ method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The $g_m/I_D$ method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design. Full article

The controller area network (CAN) protocol, widely used for in-vehicle communication, lacks built-in security features and is inherently vulnerable to various attacks. Numerous attack techniques against CAN have been reported, leading to intrusion detection systems (IDSs) tailored for in-vehicle networks. In this study, we propose a novel lightweight unsupervised IDS for CAN networks, designed for real-time, on-device implementation. The proposed autoencoder model was trained exclusively on normal data. A portion of the attack data was utilized to determine the optimal detection threshold using a Gaussian kernel density estimation function, while the frame count was selected based on error rate analysis. Subsequently, the model was evaluated using four types of attack data that were not seen during training. Notably, the model employs a single threshold across all attack types, enabling detection using a single model. Furthermore, the designed software model was optimized for hardware implementation and validated on an FPGA under a real-time CAN communication environment. When evaluated, the proposed system achieved an average accuracy of 99.2%, precision of 99.2%, recall of 99.1%, and F1-score of 99.2%. Furthermore, compared to existing FPGA-based IDS models, our model reduced the usage of LUTs, flip-flops, and power by average factors of 1/5, 1/6, and 1/11. Full article

The use of multi-output look-up tables (LUTs) is a widely adopted approach in contemporary commercial field-programmable gate arrays (FPGAs). Larger LUT configurations (e.g., six-input LUTs) can be partitioned into smaller LUTs (e.g., two five-input LUTs, maintaining a total input count of less than six). This capability of generating a second output from a larger LUT is not only crucial for reducing logic cell count and enhancing the utilization efficiency of logic resources—thus conserving area—but also plays a key role in optimizing system-level delays and energy consumption. In this paper, we propose an efficient multi-output LUT mapping technique, incorporating several highly efficient technology mapping algorithms, which focus on optimizing the mapping from an interconnection perspective as alternatives to directly merging smaller LUTs. These algorithms include a side-fanout insertion algorithm, and a runtime multi-output cut generation algorithm. The proposed methods improve mapping efficiency and enhance performance. The benchmarking results demonstrate that the dual-output mapping algorithms achieve LUT area reductions of up to 35% and 6%, compared to the state-of-the-art ABC six-input, single-output LUT mapping technique and previous work focusing on dual-output LUT mapping techniques that optimize cut generation parameters. Moreover, FPGA system-level simulations also show that area, delay, and energy can all be optimized based on this multi-output mapping technique. Full article

A new state assignment method focusing on Mealy finite state machines (FSMs) is proposed. The proposed codes are an alternative to composite state codes (CSCs). CSCs are represented as concatenations of group codes and partial state codes. Both group and partial state codes are maximum binary codes. We propose encoding groups using one-hot codes. The main goal of this method is improving the value of the FSM cycle time without a significant degradation of the spatial characteristics. The method can be applied if FSM circuits are implemented using the look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes three logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot group codes. The partial codes are assigned in a way minimizing the number of arguments in the partial functions. This allows for the generation of most partial functions by single-LUT circuits. The second block generates the final values of the input memory functions and FSM outputs. This block does not require group codes to generate functions, as in CSC-based FSMs. The third block transforms maximum binary group codes into their one-hot equivalents. The proposed approach allows for a reduction in the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics of an FSM circuit are improved. This paper includes an example of FSM synthesis applying the proposed method. The experiments were conducted using standard benchmark FSMs. The results of the experiments show that the proposed method allowed for an improvement in the cycle time of an average of 8.81%. Moreover, in relation to CSC-based FSMs, the LUT counts decreased by an average of 4.00%. Full article

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems. Full article

In this paper, a feasibility study of a shuntless coulomb counting method for estimating the state of charge (SOC) of a battery is presented. Contrary to conventional coulomb counting, the proposed method does not require an external resistive shunt; it instead only requires voltage measurements performed on the battery under test while it is operating. The current is measured indirectly using the battery’s equivalent series resistance (ESR). The method consists of a preliminary calibration phase where the ESR and the open-circuit voltage of the battery are measured for different SOCs and stored in look-up tables (LUTs). Then, in the subsequent operational phase, the method uses these LUTs together with the measured voltage at the battery terminals to estimate the SOC. The performance of the proposed method is evaluated on a sample lithium polymer (LiPo) battery, using a realistic current profile derived from the Worldwide Harmonized Light-Duty Vehicles Test Procedure (WLTP). The results of this experimental evaluation demonstrate a SOC estimation root-mean-square error of 0.82% and a maximum SOC error of 1.45%. These results prove that the proposed method is feasible in a practical scenario. Full article

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states. Full article

A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible. Full article

A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes. The second core uses extended state codes. Such an approach allows reducing the number of LUTs in the block of state codes’ transformation. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each partial function for any core is represented by a single-LUT circuit. A formal method is proposed for redistribution of states between these cores. An example of synthesis is shown to explain peculiarities of the proposed method. An example of state redistribution is given. The results of experiments conducted with standard benchmarks show that the double-core approach produces LUT-based FSM circuits with better area-temporal characteristics than they are for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and twofold state assignment). Both the LUT counts and maximum operating frequencies are improved. The gain in LUT counts varies from 5.74% to 36.92%, and the gain in frequency varies from 5.42% to 12.4%. These improvements are connected with a very small growth of the power consumption (less than 1%). The advantages of the proposed approach increase as the number of FSM inputs and states increases. Full article

The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs. Full article

Wake steering control can significantly improve the overall power production of wind farms. However, it also increases fatigue damage on downstream wind turbines. Therefore, optimizing fatigue loads in wake steering control has become a hot research topic. Accurately predicting farm fatigue loads has always been challenging. The current interpolation method for farm-level fatigue loads estimation is also known as the look-up table (LUT) method. However, the LUT method is less accurate because it is challenging to map the highly nonlinear characteristics of fatigue load. This paper proposes a machine-learning algorithm based on the Gaussian process (GP) to predict the farm-level fatigue load under yaw misalignment. Firstly, a series of simulations with yaw misalignment were designed to obtain the original load data, which considered the wake interaction between turbines. Secondly, the rainflow counting and Palmgren miner rules were introduced to transfer the original load to damage equivalent load. Finally, the GP model trained by inputs and outputs predicts the fatigue load. GP has more accurate predictions because it is suitable for mapping the nonlinear between fatigue load and yaw misalignment. The case study shows that compared to LUT, the accuracy of GP improves by 17% ($RMSE$) and 0.6% ($MAE$) at the blade root edgewise moment and 51.87% ($RMSE$) and 1.78% ($MAE$) at the blade root flapwise moment. Full article

A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs. Full article

A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementing digital parts of CPSs. In this article, we discuss a case when Mealy finite state machines (FSMs) represent behaviour of sequential devices. The proposed method is aimed at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The method aims to reduce the LUT count of Mealy FSMs with extended state codes. The method is based on finding a partition of the set of internal states by classes of compatible states. To reduce LUT count, we propose a special kind of state codes named composite state codes. The composite codes include two parts. The first part includes the binary codes of states as elements of some partition class. The second part consists of the code of corresponding partition class. Using composite state codes allows us to obtain FPGA-based FSM circuits with exactly two levels of logic. If some conditions hold, then any FSM function from the first level is implemented by a single LUT. The second level is represented as a network of multiplexers. Each multiplexer generates either an FSM output or input memory function. An example of synthesis is shown. The experiments prove that the proposed approach allows us to reduce hardware compared with two methods from Vivado, JEDI-based FSMs, and extended state assignment. Depending on the complexity of an FSM, the LUT count is reduced on average from 15.46 to 68.59 percent. The advantages of the proposed approach grow with the growth of FSM complexness. An additional positive effect of the proposed method is a decrease in the latency time. Full article

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the binary codes of a state as the element of some partition class. The second part consists of the code of corresponding partition class. Using complex state codes allows obtaining FPGA-based FSM circuits with exactly four logic blocks. If some conditions hold, then any FSM function from the first and second blocks is implemented by a single LUT. The third level is represented as a network of multiplexers. These multiplexers generate either additional variable encoding collections of outputs or input memory functions. The fourth level generates FSM outputs. An example of synthesis and experimental results is shown and discussed. The experiments prove that the proposed approach allows reducing hardware compared to such methods as auto and one-hot of Vivado, JEDI. Further, the proposed approach produces circuits with fewer LUTs than for three-level Mealy FSMs based on joint use of several methods of structural decomposition. The experiments show that our approach allows reducing the LUT counts on average from 11 to 77 percent. As the complexity of an FSM increases, the gain from the application of the proposed method grows; the same is true for both the FSM performance and power consumption. Full article

Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteristic of an FSM circuit. In the article, we propose a method which allows increasing the operating frequency of multi-level look-up table (LUT)-based Mealy FSMs. The main idea of the proposed approach is to use together two methods of structural decomposition. They are: (1) the known method of transformation of codes of collections of outputs into FSM state codes and (2) a new method of extension of state codes. The proposed approach allows producing FPGA-based FSMs having three levels of logic combined through the system of regular interconnections. Each function for every level of logic was implemented using a single LUT. An example of the synthesis of Mealy FSM with the proposed architecture is shown. The effectiveness of the proposed method was confirmed by the results of experimental studies based on standard benchmark FSMs. The research results show that FSM circuits based on the proposed approach have a higher operating frequency than can be obtained using other investigated methods. The maximum operating frequency is improved by an average of 3.18 to 12.57 percent. These improvements are accompanied by a small growth of LUT count. Full article