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Article

Improving Hardware in LUT-Based Mealy FSMs

1
Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, Ul. Licealna 9, 65-417 Zielona Gora, Poland
2
Department of Computer Science and Information Technology, Vasyl Stus’ Donetsk National University, 600-Richya Str. 21, 21021 Vinnytsia, Ukraine
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Department of Infocommunication Engineering, Faculty of Infocommunications, Kharkiv National University of Radio Electronics, Nauky Avenue 14, 61166 Kharkiv, Ukraine
4
Department of Technology, The Jacob of Paradies University, Ul. Teatralna 25, 66-400 Gorzow Wielkopolski, Poland
*
Authors to whom correspondence should be addressed.
Academic Editor: Amalia Miliou
Appl. Sci. 2022, 12(16), 8065; https://doi.org/10.3390/app12168065
Received: 18 July 2022 / Revised: 5 August 2022 / Accepted: 10 August 2022 / Published: 11 August 2022
(This article belongs to the Section Electrical, Electronics and Communications Engineering)
The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs. View Full-Text
Keywords: Mealy FSM; FPGA; LUT count; synthesis; collection of outputs Mealy FSM; FPGA; LUT count; synthesis; collection of outputs
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MDPI and ACS Style

Barkalov, A.; Titarenko, L.; Krzywicki, K. Improving Hardware in LUT-Based Mealy FSMs. Appl. Sci. 2022, 12, 8065. https://doi.org/10.3390/app12168065

AMA Style

Barkalov A, Titarenko L, Krzywicki K. Improving Hardware in LUT-Based Mealy FSMs. Applied Sciences. 2022; 12(16):8065. https://doi.org/10.3390/app12168065

Chicago/Turabian Style

Barkalov, Alexander, Larysa Titarenko, and Kazimierz Krzywicki. 2022. "Improving Hardware in LUT-Based Mealy FSMs" Applied Sciences 12, no. 16: 8065. https://doi.org/10.3390/app12168065

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