Search Results (26)

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

The motivation of this work is to enable the use of piezoelectric micromachined ultrasonic transducer (PMUT)-based implants within the human body for biomedical applications, particularly for power and data transfer for implanted medical devices. To protect surrounding tissue and ensure PMUT functionality over time, biocompatible and hermetic encapsulation is essential. This study investigates the impact of Parylene F-VT4 layers of various thicknesses as well as the effect of multilayer stacks of Parylene F-VT4 combined with atomic layer-deposited nanolayers of Al₂O₃ and HfO₂ on the mechanical and acoustic properties of PMUTs. PMUTs with various diameters (40 µm, 60 µm, and 80 µm) are fabricated and tested both as stand-alone devices and as arrays. The mechanical behavior of single stand-alone PMUT devices is characterized in air and in water using laser Doppler vibrometry (LDV), while the acoustic output of arrays is evaluated by pressure measurements in water. Experimental results reveal a non-monotonic change in resonance frequency as a function of increasing encapsulation thickness due to the competing effects of added mass and increased stiffness. The performance of PMUT arrays is clearly influenced by the encapsulation. For certain array designs, the encapsulation significantly improved the arrays’ pressure output, a change that is attributed to the change in the acoustic wavelength and inter-element coupling. These findings highlight the impact of encapsulation in modifying and potentially enhancing PMUT performance. Full article

Besides the intensity and wavelength, the ability to analyze the optical polarization of detected light can provide a new degree of freedom for numerous applications, such as object recognition, biomedical applications, environmental monitoring, and remote sensing imaging. However, conventional filter-integrated polarimetric sensing systems require complex optical components and a complicated fabrication process, severely limiting their on-chip miniaturization and functionalities. Herein, the reconfigurable polarimetric photodetection with photovoltaic mode is developed based on a few-layer MoS₂/PdSe₂ heterostructure channel and a charge-trap structure composed of Al₂O₃/HfO₂/Al₂O₃ (AHA)-stacked dielectrics. Because of the remarkable charge-trapping ability of carriers in the AHA stack, the MoS₂/PdSe₂ channel exhibits a high program/erase current ratio of 10⁵ and a memory window exceeding 20 V. Moreover, the photovoltaic mode of the MoS₂/PdSe₂ Schottky diode can be operated and manipulable, resulting in high and distinct responsivities in the visible broadband. Interestingly, the linear polarization of the device can be modulated under program/erase states, enabling the reconfigurable capability of linearly polarized photodetection. This study demonstrates a new prototype heterostructure-based photodetector with the capability of both tunable responsivity and linear polarization, demonstrating great potential application toward reconfigurable photosensing and polarization-resolved imaging applications. Full article

The last decade has seen dramatic progress in research on FETs with 2D channels. Starting from the single devices fabricated using exfoliated flakes in the early 2010s, by the early 2020s, 2D FETs being trialed for mass production and vertical stacking of 2D channels made by leading semiconductor companies. However, the industry is focused solely on transition metal dichalcogenide (TMD) channels coupled with conventional 3D oxide insulators such as Al₂O₃ and HfO₂. This has resulted in numerous challenges, such as poor-quality interfaces and reliability limitations due to oxide traps. At the same time, the alternative routes for 2D FETs offered by laboratory (LAB) research have not been appreciated until now, even though the use of the native oxides of 2D channels has recently resulted in the first 2D FinFETs. Considering the research progress achieved in the last decade, from this perspective, we will discuss the main challenges for industry integration of 2D FETs and also suggest possible future steps which could propel these emerging technologies towards market applications. Full article

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (W_fin) and the neighboring gate oxide width (t_ox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell–Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO₂, Si₃N₄, Al₂O₃, HfO₂, La₂O₃, and TiO₂ perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (I_OFF) reduced down to 6.45 × 10⁻¹⁵ A for the Al₂O₃: TiO₂ combination and a gate leakage current (I_G) reaching down to 2.04 × 10⁻¹¹ A for the Al₂O₃: HfO₂: La₂O₃ combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities. Full article

The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO₂) with a stacked gate oxide of 0.5 nm of SiO₂ with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si₃N₄, Al₂O₃, ZrO_2, and HfO₂. It was found that the use of strained silicon and replacing only the SiO₂ device with the stacked SiO₂ and HfO₂ device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. Full article

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO₂/Al₂O₃-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO₂ is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO₂/Al₂O₃-based stacks. Full article

Resistive random-access memory (RRAM) is a promising candidate for next-generation non-volatile memory. However, due to the random formation and rupture of conductive filaments, RRMS still has disadvantages, such as small storage windows and poor stability. Therefore, the performance of RRAM can be improved by optimizing the formation and rupture of conductive filaments. In this study, a hafnium oxide-/aluminum-doped zinc oxide/hafnium oxide (HfO₂/Al-ZnO/HfO₂) tri-layer structure device was prepared using the sol–gel method. The oxygen-rich vacancy Al-ZnO layer was inserted into the HfO₂ layers. The device had excellent RS properties, such as an excellent switch ratio of 10⁴, retention of 10⁴ s, and multi-level storage capability of six resistance states (one low-resistance state and five high-resistance states) and four resistance states (three low-resistance states and one high-resistance state) which were obtained by controlling stop voltage and compliance current, respectively. Mechanism analysis revealed that the device is dominated by ohmic conduction and space-charge-limited current (SCLC). We believe that the oxygen-rich vacancy concentration of the Al-ZnO insertion layer can improve the formation and rupture behaviors of conductive filaments, thereby enhancing the resistive switching (RS) performance of the device. Full article

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS₂ NCFET is fabricated using a single Hf_0.5−xZr_0.5−xAl_2xO_y (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf_0.5Zr_0.5O₂ (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 10⁶. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al₂O₃ stack gates. Full article

Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO₂/Al₂O₃ nanolaminates and Al-doped HfO₂, are used as the charge trapping layer, and SiO₂ (of different thickness) or Al₂O₃ is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO₂ tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O₂ significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O₂ annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO₂, while electron traps are related to Al₂O₃. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM. Full article

The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. Full article

Group IV quantum dots (QDs) in HfO₂ are attractive for non-volatile memories (NVMs) due to complementary metal-oxide semiconductor (CMOS) compatibility. Besides the role of charge storage centers, SiGeSn QDs have the advantage of a low thermal budget for formation, because Sn presence decreases crystallization temperature, while Si ensures higher thermal stability. In this paper, we prepare MOS capacitors based on 3-layer stacks of gate HfO₂/floating gate of SiGeSn QDs in HfO₂/tunnel HfO₂/p-Si obtained by magnetron sputtering deposition followed by rapid thermal annealing (RTA) for nanocrystallization. Crystalline structure, morphology, and composition studies by cross-section transmission electron microscopy and X-ray diffraction correlated with Raman spectroscopy and C–V measurements are carried out for understanding RTA temperature effects on charge storage behavior. 3-layer morphology and Sn content trends with RTA temperature are explained by the strongly temperature-dependent Sn segregation and diffusion processes. We show that the memory properties measured on Al/3-layer stack/p-Si/Al capacitors are controlled by SiGeSn-related trapping states (deep electronic levels) and low-ordering clusters for RTA at 325–450 °C, and by crystalline SiGeSn QDs for 520 and 530 °C RTA. Specific to the structures annealed at 520 and 530 °C is the formation of two kinds of crystalline SiGeSn QDs, i.e., QDs with low Sn content (2 at.%) that are positioned inside the floating gate, and QDs with high Sn content (up to 12.5 at.%) located at the interface of floating gate with adjacent HfO₂ layers. The presence of Sn in the SiGe intermediate layer decreases the SiGe crystallization temperature and induces the easier crystallization of the diamond structure in comparison with 3-layer stacks with Ge-HfO₂ intermediate layer. High frequency-independent memory windows of 3–4 V and stored electron densities of 1–2 × 10¹³ electrons/cm² are achieved. Full article

The application of micro-Raman spectroscopy was used for characterization of structural features of the high-k stack (h-k) layer of “silicon-on-insulator” (SOI) nanowire (NW) chip (h-k-SOI-NW chip), including Al₂O₃ and HfO₂ in various combinations after heat treatment from 425 to 1000 °C. After that, the NW structures h-k-SOI-NW chip was created using gas plasma etching optical lithography. The stability of the signals from the monocrine phase of HfO₂ was shown. Significant differences were found in the elastic stresses of the silicon layers for very thick (>200 nm) Al₂O₃ layers. In the UV spectra of SOI layers of a silicon substrate with HfO₂, shoulders in the Raman spectrum were observed at 480–490 cm⁻¹ of single-phonon scattering. The h-k-SOI-NW chip created in this way has been used for the detection of DNA-oligonucleotide sequences (oDNA), that became a synthetic analog of circular RNA–circ-SHKBP1 associated with the development of glioma at a concentration of 1.1 × 10⁻¹⁶ M. The possibility of using such h-k-SOI NW chips for the detection of circ-SHKBP1 in blood plasma of patients diagnosed with neoplasm of uncertain nature of the brain and central nervous system was shown. Full article

The interface passivation of the HfO₂/Si_0.7Ge_0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al₂O₃/Si_0.7Ge_0.3 stack, the dispersive feature and interface state density (D_it) of the HfO₂/Si_0.7Ge_0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeO_x in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO₂ and cause the HfO₂/Si_0.7Ge_0.3 interface to deteriorate. Moreover, a post-HfO₂-deposition (post-O) ozone indirect oxidation is proposed for the HfO₂/Si_0.7Ge_0.3 stack; it is found that compared with pre-O sample, the D_it of the post-O sample decreases by about 50% due to less GeO_x available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO₂/Si_0.7Ge_0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the D_it of the HfO₂/Si_0.7Ge_0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO₂/Si_0.7Ge_0.3 interface with D_it of 1.53 × 10¹¹ eV⁻¹cm⁻² @ E−E_v = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO₂/IL/Si-cap/Si_0.7Ge_0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO₂/Si_0.7Ge_0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO₂ and Si_0.7Ge_0.3 substrate. Full article

For improving retention characteristics in the NOR flash array, aluminum oxide (Al₂O₃, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO₂/Al₂O₃/SiO₂, which take advantage of higher permittivity and higher bandgap of Al₂O₃ compared to SiO₂ and silicon nitride (Si₃N₄). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO₂/Si₃N₄/SiO₂ tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO₂ as a charge-trapping layer in NOR flash application is opened. Full article