Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.


Introduction
Flash memory is an electronic, non-volatile information storage device that can be electrically erased and reprogrammed.Ideally, the information stored in such a device should be preserved for long when the power is switched off.Flash memories are the primary means to realize low-cost and high-density data storage needed for all major end-user gadgets (smartphones, PCs, USBs, medical devices, electronic games, etc.).The ever-widening field of possible applications made flash memories the fastest-growing product in the history of the semiconductor market (Figure 1).
For a long time, the dominant flash NVM technology was the floating gate (FG) memory cell [4,5].The idea for the FG memory cell was proposed by Kahng and S.M. Sze in 1967 [6].Its operation principle is based on charge storage in an electrically isolated floating poly-Si gate.This floating gate is stacked in between a thin tunnelling (6-7 nm) oxide and interpoly dielectric (10-13 nm) (Figure 2a).By applying a pulse to the control gate, the electrons are injected from the transistor's channel to the floating gate and stored there until the pulse with opposite polarity forces them out of the floating gate.The presence/absence of electrons on the floating gate changes the threshold voltage, thus forming the memory window.The charges stored in the electrically isolated floating gate remain there for a long time, thus defining the non-volatile character of memory.The increasing demands for larger volumes of stored data cause an aggressive down-scaling of FG cell sizes.As a consequence, some of the intrinsic limitations of floating gate technology have been reached, e.g.,: (i) the thickness scaling of tunnel oxide and inter-poly dielectric layer compromises the reliability; (ii) a significant decrease in the number of electrons accumulated in FG as its dimensions decrease; (iii) it is difficult to maintain a high coefficient of capacitive coupling of the control gate to the floating gate; (iv) the parasitic capacitance between adjacent cells leading to data interference becomes important, etc.  [1], from 2007 to 2012 from [2] and from 2013 to 2021 by [3].
For a long time, the dominant flash NVM technology was the floating gate (FG) memory cell [4,5].The idea for the FG memory cell was proposed by Kahng and S.M. Sze in 1967 [6].Its operation principle is based on charge storage in an electrically isolated floating poly-Si gate.This floating gate is stacked in between a thin tunnelling (6-7 nm) oxide and interpoly dielectric (10-13 nm) (Figure 2a).By applying a pulse to the control gate, the electrons are injected from the transistor's channel to the floating gate and stored there until the pulse with opposite polarity forces them out of the floating gate.The presence/absence of electrons on the floating gate changes the threshold voltage, thus forming the memory window.The charges stored in the electrically isolated floating gate remain there for a long time, thus defining the non-volatile character of memory.The increasing demands for larger volumes of stored data cause an aggressive down-scaling of FG cell sizes.As a consequence, some of the intrinsic limitations of floating gate technology have been reached, e.g.,: (i) the thickness scaling of tunnel oxide and inter-poly dielectric layer compromises the reliability; (ii) a significant decrease in the number of electrons accumulated in FG as its dimensions decrease; (iii) it is difficult to maintain a high coefficient of capacitive coupling of the control gate to the floating gate; (iv) the parasitic capacitance between adjacent cells leading to data interference becomes important, etc.Therefore, several new approaches to achieve a non-volatile programmable memory effect have been proposed: ferroelectric field effect transistor, resistive switching memory, nanoelectromechanical memory, spin-transfer torque memory, phase change memory,  [1], from 2007 to 2012 from [2] and from 2013 to 2021 by [3].[1], from 2007 to 2012 from [2] and from 2013 to 2021 by [3].
For a long time, the dominant flash NVM technology was the floating gate (FG) memory cell [4,5].The idea for the FG memory cell was proposed by Kahng and S.M. Sze in 1967 [6].Its operation principle is based on charge storage in an electrically isolated floating poly-Si gate.This floating gate is stacked in between a thin tunnelling (6-7 nm) oxide and interpoly dielectric (10-13 nm) (Figure 2a).By applying a pulse to the control gate, the electrons are injected from the transistor's channel to the floating gate and stored there until the pulse with opposite polarity forces them out of the floating gate.The presence/absence of electrons on the floating gate changes the threshold voltage, thus forming the memory window.The charges stored in the electrically isolated floating gate remain there for a long time, thus defining the non-volatile character of memory.The increasing demands for larger volumes of stored data cause an aggressive down-scaling of FG cell sizes.As a consequence, some of the intrinsic limitations of floating gate technology have been reached, e.g.,: (i) the thickness scaling of tunnel oxide and inter-poly dielectric layer compromises the reliability; (ii) a significant decrease in the number of electrons accumulated in FG as its dimensions decrease; (iii) it is difficult to maintain a high coefficient of capacitive coupling of the control gate to the floating gate; (iv) the parasitic capacitance between adjacent cells leading to data interference becomes important, etc.Therefore, several new approaches to achieve a non-volatile programmable memory effect have been proposed: ferroelectric field effect transistor, resistive switching memory, nanoelectromechanical memory, spin-transfer torque memory, phase change memory, etc.All these new memory concepts are classified as emerging memories and rely on distinctly different physical phenomena and principles than currently used.For most of them, the architecture of the device/memory cell, as well as the materials, are quite differ- Therefore, several new approaches to achieve a non-volatile programmable memory effect have been proposed: ferroelectric field effect transistor, resistive switching memory, nanoelectromechanical memory, spin-transfer torque memory, phase change memory, etc.All these new memory concepts are classified as emerging memories and rely on distinctly different physical phenomena and principles than currently used.For most of them, the architecture of the device/memory cell, as well as the materials, are quite different than those already adopted in the microelectronic industry, and there are a lot of problems with making them compatible with the current technology, which eventually requires abandoning the CMOS paradigm.A comprehensive review of the operation principles, advantages, and shortcomings of these new NVM concepts can be found in [7].Still, none of the above-mentioned innovative devices and technologies has been identified as the most prospective and clear winner to replace CMOS-based memory cells.
In summary, new computing and data storage paradigms (like neuromorphic or quantum), novel architectures and devices using charges or, in the longer term, alternative state variables (e.g., spin, magnon, phonon, photon, etc.) are required to scale information processing technology substantially beyond that attainable by the ultimately scaled CMOS [8].While developing these new technological approaches and paving the way for their adoption by the industry, there are still innovations within the current technology paradigm, which have been implemented to increase the bit density of NVM.These are, for example, an increase in the number of up to 4 bits per memory cell and replacing the floating gate cell with a charge trap cell [9].
Charge trapping flash (CTF) NVMs (Figure 2b) are a promising alternative to the conventional floating gate technology because they involve a more simplified process flow accompanied by better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed [10][11][12].The charge-trapping memory is proposed by H. A. R. Wegner et al. [13].CTF operation is similar to the floating gate cell, but the charge in CTF is stored in spatially discrete traps in the band-gap of the dielectric layer instead of the conducting floating poly-Si gate.This mode of charge storage offers a significant advantage over FG because the discharge of the whole stored charge is prevented in the case of an isolated defect in the tunnel oxide (hence the leakage path), and only charges stored in traps adjacent to the leakage path may be lost.The architecture of CT memory is very similar to MOSFET.Hence, it is compatible with CMOS technology.The importance of CTF became undeniable when flash memories switched from scaling horizontally to stacking vertically.Flash products have already overcome the 2D limitations by aggressively implementing 3D memory cell structures-72-96 layers of NAND memory cells have already been demonstrated [8].The use of CT-NVM is also favourable in Vertical-NAND flash memory technology as it is more easily stacked vertically [14].
The most important part of the CT memory is the charge-trapping stack (Figure 2b).It consists of three layers-a charge trapping layer (CTL), where the charges are stored in traps.CTL is stacked in between the tunnelling and blocking oxides.Tunnelling oxide (TO) is used for more efficient injection of charges from the substrate/FET channel to CTL to prevent the trapped charges from back tunnelling to the substrate and to improve the retention characteristics.On the other hand, to form a potential barrier against the undesirable movement of electrical charges (holes/electrons) to and from the gate electrode, a thick enough blocking oxide (BO) should be introduced, and its band offset with the CTL should be of sufficient height.Therefore, the use of SiO 2 with its band-gap Eg of about 9.1 eV both as a blocking and a tunnelling oxide is a natural choice.
Moreover, recent technology allows SiO 2 to be grown with very low densities of defects and traps, which may participate in the process of charge loss.In the current CTFs, Si 3 N 4 is used as a CTL because Si 3 N 4 provides a sufficiently high density of trapping sites.This charge trapping stack consisting of SiO 2 (TO)-Si 3 N 4 (CTL)-SiO 2 (BO) tri-layer is usually referred to as an ONO stack.The ONO suffers from the trade-off between programming speed and retention.On the one hand, to enhance program/erase (P/E) speed, a thinner TO is required.On the other hand, thicker TO ensures better retention.The implementation of high-k materials in CTF is expected to overcome some of the problems arising from the down-scaling of CTF and extend the applicability of this technology [15].
In this review, we summarize and give a more general view of our systematic studies of metal/blocking oxide (BO)/high-k charge trapping layer (CTL)/tunnel oxide (TO)/Si (MOHOS) structures with HfO 2 /Al 2 O 3 -based CTL prepared by ALD considered for application in CTF memories.The work is organized as follows.Section 2 results on the density and energy location of traps, charge trapping and storage characteristics, leakage currents in HfO 2 /Al 2 O 3 -based CTLs, and their dependence on the composition of CTL and annealing in O 2 are summarized.Section 3 considers the introduction of tunnelling and blocking oxide in the stack and their influence on the electrical behaviour of memory cells.Finally, in Section 4, the main conclusions of the study, as well as perspectives for further improvement and future applications of HfO 2 /Al 2 O 3 -based charge trapping stacks, are outlined.

Charge Trapping Layer
As mentioned above, high-k dielectric materials have been considered to replace Si 3 N 4 in conventional CTFs [15,16].HfO 2 -based high-k dielectric layers attracted much attention in the last two decades due to their importance as gate dielectrics.Respectively, the intensive studies of their properties and technology approaches to improve them resulted in their adoption by CMOS technology and successful application in Intel Penryn and Samsung A7 processors.Generally, HfO 2 is a trap-rich material-a property that is undesired for high-performance logic applications (such as CPUs).Therefore, dedicated measures should be undertaken to reduce the density of electrically active defects to meet performance requirements.However, the high density of traps next to the relatively high dielectric constant, large conduction band offsets with Si and tunnel oxide, as CMOS compatibility made HfO 2 -based dielectrics a very attractive alternative to supersede the conventional Si 3 N 4 as CTL in CTFs.The higher dielectric constant ensures robust data storage because it enables the storage of more electrons without increasing the applied field.It was shown that the 2 nm HfO 2 layer has a better charge trapping efficiency than 7 nm Si 3 N 4 [17].Another advantage of using high-k dielectrics as CTL is that there is a large room to modify and tailor their properties toward meeting the specific requirements of the given application.For example, the charge storage characteristics could be significantly boosted by proper treatments, e.g., annealing steps, UV irradiation, etc. [18][19][20].Doping/mixing with other elements was a very efficient way to modify the density and spatial and energy location of electrically active defects.Bandgap engineering of the CTL by introducing Al in HfO 2 or stacking HfO 2 with Al 2 O 3 has been suggested [21][22][23][24], resulting in an enhancement in memory performance and reliability.
Moreover, the introduction of Al in high-k dielectrics is known to increase crystallization temperature [25].CTL needs to be amorphous as the grain boundaries in crystalline layers may result in increased leakage currents.The increase in the number of the HfO 2 /Al 2 O 3 interfaces has been reported to improve the charge-trapping ability of devices assigned to interdiffusion at the HfO 2 /Al 2 O 3 interface and the creation of additional defects [26].However, it appeared that the thickness of the layers and the number of interfaces should be carefully optimized as the performance of the cell could deteriorate by the electrostatic repulsion between the trapped charges [27].The possibility to combine the HfO 2 /Al 2 O 3 dielectric stacks with high-mobility channel materials (e.g., SiGe [28], GaAs [29,30], InP [31], In 2 Ga 2 ZnO 7 [32]) as well as with 2D materials, (e.g., black phosphorous [33] and MoS 2 [24,34]) opens up new horizons for their implementation in emerging applications such as thin film transistors, non-volatile memory devices for flexible and transparent electronics, etc.
For efficient and reliable trapping, a high density of traps is important, but these traps should be deep enough.Therefore, to get control and optimize the operation of CTF memory cells, a thorough understanding of the origin of traps and their spatial and energy location in the charge trapping layer should be acquired.The deep insight into the trapping kinetics and storage paves the way to successful process optimization and robust memory cell performance.In addition, the leakage current has to be low-a requirement that is quite challenging to satisfy simultaneously with the high density of intrinsic traps.Therefore, our efforts have aimed to produce charge-trapping layers with a high density of deep traps while preserving a low leakage current.

Density and Energy Location of Traps
As a first step in the optimization process, the impact of Al introduction in HfO 2 on traps' density and energy location has been investigated [18].Several samples with different thicknesses and Al content have been deposited by ALD and compared to pure HfO 2 .The charge-trapping and the ability of a stack to store a charge is evaluated by measuring the C-V hysteresis ∆V C-V in dependence on the end voltage V end of the measured C-V curves (Figure 3a).∆V C-V is usually called a memory window.The detailed investigations and analysis of the obtained results [18] reveal two kinds of trapping processes: (i) The first process is irreversible trapping due to traps generated by the high electric field stress.This process is undesired because it results in permanent damage and progressive structure degradation.It has been established that it is independent of doping, which allows the conclusion that it occurs in HfO 2 -related defects; (ii) The second process is reversible trapping, i.e., the charges could be reversibly captured in and erased from the traps under proper biasing conditions.This is the reversible program/erase cycle, which defines the main principle of operation of CTFs.
As a first step in the optimization process, the impact of Al introduction in HfO2 on traps' density and energy location has been investigated [18].Several samples with different thicknesses and Al content have been deposited by ALD and compared to pure HfO2.The charge-trapping and the ability of a stack to store a charge is evaluated by measuring the C-V hysteresis ΔVC-V in dependence on the end voltage Vend of the measured C-V curves (Figure 3a).ΔVC-V is usually called a memory window.The detailed investigations and analysis of the obtained results [18] reveal two kinds of trapping processes: (i) The first process is irreversible trapping due to traps generated by the high electric field stress.This process is undesired because it results in permanent damage and progressive structure degradation.It has been established that it is independent of doping, which allows the conclusion that it occurs in HfO2-related defects; (ii) The second process is reversible trapping, i.e., the charges could be reversibly captured in and erased from the traps under proper biasing conditions.This is the reversible program/erase cycle, which defines the main principle of operation of CTFs.The results have revealed that the C-V hysteresis, hence the density of trapped charge, depends very strongly on the layer thickness and a doping level (Figure 3b), and the findings could be summarized as follows: (i) The trapping is stronger in the thicker samples; (ii) lightly doped (2 cy Al2O3) layers have lower trap density compared to pure HfO2; and, more highly doped (4 or 5 cy Al2O3) layers reveal higher trap density, which is one of the condition for the efficient charge trapping and storage.The density of traps for more highly doped layers has been estimated in the range of Nt = (4-5) × 10 19 cm −3 ; which is higher than the reported density of deep traps in Si3N4 of about 10 19 cm −3 and required for a robust operation of CTF cell [35].The centroid of the trapped charge is estimated at 4.95 nm, which coincides with the location of Al doping.
The energy location of the traps and how it is affected by Al introduction into HfO2 have been assessed by performing temperature-dependent I−V measurements and detailed analysis of conduction mechanisms.A comprehensive review of the approach to assessing important trap parameters from investigating dominant conduction mechanisms could be found in [36].In Figure 4, the observed conduction mechanisms, and trap levels in line with the Al-doping profile in the different samples are schematically represented.It has been found [18] that in pure HfO2 the trap level is located at about 0.7 eV The results have revealed that the C-V hysteresis, hence the density of trapped charge, depends very strongly on the layer thickness and a doping level (Figure 3b), and the findings could be summarized as follows: (i) The trapping is stronger in the thicker samples; (ii) lightly doped (2 cy Al 2 O 3 ) layers have lower trap density compared to pure HfO 2 ; and, more highly doped (4 or 5 cy Al 2 O 3 ) layers reveal higher trap density, which is one of the condition for the efficient charge trapping and storage.The density of traps for more highly doped layers has been estimated in the range of N t = (4-5) × 10 19 cm −3 ; which is higher than the reported density of deep traps in Si 3 N 4 of about 10 19 cm −3 and required for a robust operation of CTF cell [35].The centroid of the trapped charge is estimated at 4.95 nm, which coincides with the location of Al doping.
The energy location of the traps and how it is affected by Al introduction into HfO 2 have been assessed by performing temperature-dependent I−V measurements and detailed analysis of conduction mechanisms.A comprehensive review of the approach to assessing important trap parameters from investigating dominant conduction mechanisms could be found in [36].In Figure 4, the observed conduction mechanisms, and trap levels in line with the Al-doping profile in the different samples are schematically represented.It has been found [18] that in pure HfO 2 the trap level is located at about 0.7 eV below the conduction band (Figure 4a), which is consistent with the theoretical calculations of the energy position of O-vacancies in HfO 2 [26,37].This level has not been observed in the Al-doped films, where traps have been estimated at 1.3 eV (Figure 4b,c).Similar results have also been observed by Molas et al. [38], who found a trap level at about 1.35 eV below the conduction band for HfAlO layers with Hf:Al(9:1) and at about 1.55 eV for Hf:Al(1:9).Therefore, the obtained results give evidence that doping with Al of HfO 2 layers has two effects: (i) it reduces oxygen vacancies in HfO 2 , and (ii) introduces deep traps, which are involved in reversible trap processes.It will be shown below that these traps do not increase the leakage currents, and all Al-doped HfO 2 layers have lower leakage currents than their HfO 2 counterpart.
below the conduction band (Figure 4a), which is consistent with the theoretical calculations of the energy position of O-vacancies in HfO2 [26,37].This level has not been observed in the Al-doped films, where traps have been estimated at 1.3 eV (Figure 4b,c).Similar results have also been observed by Molas et al. [38], who found a trap level at about 1.35 eV below the conduction band for HfAlO layers with Hf:Al(9:1) and at about 1.55 eV for Hf:Al(1:9).Therefore, the obtained results give evidence that doping with Al of HfO2 layers has two effects: (i) it reduces oxygen vacancies in HfO2, and (ii) introduces deep traps, which are involved in reversible trap processes.It will be shown below that these traps do not increase the leakage currents, and all Al-doped HfO2 layers have lower leakage currents than their HfO2 counterpart.

Composition of Charge Trapping Layer
Considering the results presented in Section 2.1, more detailed investigations on the CTL composition and how it affects charge trapping and storage characteristics have been performed [39].Several nanolaminated dielectric structures have been prepared with different deposition cycles, respectively thickness, of HfO2 and Al2O3.Also, structures with different numbers of repetitions of the HfO2/Al2O3 bi-layer stack have been studied.For simplicity, the composition of the stack is designated as n×(x:y), where x is the number of HfO2 ALD deposition cycles, y-is the number of Al2O3 deposition cycles and n-is the number of repetitions of the HfO2/Al2O3 bi-layer stack (Figure 5).It should be mentioned that the deposition temperature is low-135 °C.More details for the deposition of samples can be found in [39].These structures have no TO and BO to study the trapping efficiency of the charge trapping layer.Part of the samples have been subjected to RTA in O2 at 800 °C for 1 min.It should be mentioned that no crystallization of samples occurs after this annealing [40].

Composition of Charge Trapping Layer
Considering the results presented in Section 2.1, more detailed investigations on the CTL composition and how it affects charge trapping and storage characteristics have been performed [39].Several nanolaminated dielectric structures have been prepared with different deposition cycles, respectively thickness, of HfO 2 and Al 2 O 3 .Also, structures with different numbers of repetitions of the HfO 2 /Al 2 O 3 bi-layer stack have been studied.For simplicity, the composition of the stack is designated as n×(x:y), where x is the number of HfO 2 ALD deposition cycles, y-is the number of Al 2 O 3 deposition cycles and n-is the number of repetitions of the HfO 2 /Al 2 O 3 bi-layer stack (Figure 5).It should be mentioned that the deposition temperature is low-135 • C.More details for the deposition of samples can be found in [39].These structures have no TO and BO to study the trapping efficiency of the charge trapping layer.Part of the samples have been subjected to RTA in O 2 at 800 • C for 1 min.It should be mentioned that no crystallization of samples occurs after this annealing [40].Generally, the results have demonstrated that memory window is strongly affected by: annealing ambient, total thickness and Al2O3 content in the films.For as-deposited stacks, strong positive charge trapping is observed, while electron trapping is observed only at relatively low pulse voltages, Vp (Figure 6a).At higher voltages, positive charge build-up dominates even when electrons are injected into the stack.Such behaviour has Generally, the results have demonstrated that memory window is strongly affected by: annealing ambient, total thickness and Al 2 O 3 content in the films.For as-deposited stacks, strong positive charge trapping is observed, while electron trapping is observed only at relatively low pulse voltages, V p (Figure 6a).At higher voltages, positive charge build-up dominates even when electrons are injected into the stack.Such behaviour has been assigned to the existence of two competing processes-reversible electron trapping at existent traps and irreversible stress generation of positive charge; the latter outweighs electron trapping at higher V p .This result reveals that as-deposited samples are susceptible to high electric field stress.In addition, samples with the thickest HfO 2 demonstrate the largest positive charge trapping, which is nearly unaffected by the Al 2 O 3 amount in the films.Generally, the results have demonstrated that memory window is strongly affected by: annealing ambient, total thickness and Al2O3 content in the films.For as-deposited stacks, strong positive charge trapping is observed, while electron trapping is observed only at relatively low pulse voltages, Vp (Figure 6a).At higher voltages, positive charge build-up dominates even when electrons are injected into the stack.Such behaviour has been assigned to the existence of two competing processes-reversible electron trapping at existent traps and irreversible stress generation of positive charge; the latter outweighs electron trapping at higher Vp.This result reveals that as-deposited samples are susceptible to high electric field stress.In addition, samples with the thickest HfO2 demonstrate the largest positive charge trapping, which is nearly unaffected by the Al2O3 amount in the films.RTA in O2 substantially improves the memory window-stable electron trapping, which increases with increasing +Vp is observed (Figure 6b).It should be mentioned that no such effect has been observed after RTA in N2 at 800 °C [39].Therefore, the increase in electron trapping is assigned to the impact of O2 than the high temperature.In addition, electron trapping is stronger in samples with more Al2O3 cycles; hence, the electron traps are related to the presence of Al atoms in HfO2, consistent with the results obtained in the previous section.It has been found that O2 annealing increases the density of electron traps but does not change their energy position, which has been estimated to lie at about RTA in O 2 substantially improves the memory window-stable electron trapping, which increases with increasing +V p is observed (Figure 6b).It should be mentioned that no such effect has been observed after RTA in N 2 at 800 • C [39].Therefore, the increase in electron trapping is assigned to the impact of O 2 than the high temperature.In addition, electron trapping is stronger in samples with more Al 2 O 3 cycles; hence, the electron traps are related to the presence of Al atoms in HfO 2 , consistent with the results obtained in the previous section.It has been found that O 2 annealing increases the density of electron traps but does not change their energy position, which has been estimated to lie at about 1.3 eV below CB of dielectric (also consistent with the results obtained in Section 2.1) [41].After RTA in O 2 , positive charge trapping for all samples is weaker than before annealing and tends to saturation (Figure 6b).Therefore, it is concluded that RTA in O 2 enhances the charge storage ability of the stacks and anneals defects in HfO 2, which are precursors of stress-induced positive charge.The number of Al 2 O 3 deposition cycles is also very important-it should be small as the samples with thicker (30 cy) Al 2 O 3 reveal strong degradation after O 2 annealing [41].
Retention characteristics of the annealed 5×(30:10) sample after a single P/E operation are presented in Figure 7a.These structures demonstrate good retention characteristics, considering they have no TO and BO.The approximation shows that more than 50% of the initial shift ∆V (hence stored charge) will be retained after ten years.The results also suggest that the negative charge (electrons) de-trapping rate is higher than that of the positive charge (holes).The detrapping of positive charge is well described by a logarithmic time dependence, which could be explained with the detrapping governed by tunnelling processes, that is, electrons/holes tunnel from the dielectric into the substrate (so-called first-order tunneling front model) [42,43].The time dependence of negative charge loss is well described by a ln 2 (t) dependence.It was shown that using the simple model of a capacitor discharging through an impedance [44] based on Poole-Frenkel conduction leads to an expression close to the observed one.More rigorously, the square logarithm retention dependence was derived in [45].Therefore, the charge loss mechanisms of electrons and holes in the stacks are different, which could be assigned to a different origin of the electron and hole charge traps.Stable endurance characteristics corresponding to positive charge build-up have been observed (Figure 7b).The negative charge trapping exhibits larger instabilities-the voltage shift resulting from electron trapping decreases with the number of cycles.The degradation of the memory window during the repeated write/erase operations is most likely due to wear-out mechanisms such as the generation of new bulk shallow traps and charges and interface state generation at the Si interface [46].are presented in Figure 7a.These structures demonstrate good retention characteristics, considering they have no TO and BO.The approximation shows that more than 50% of the initial shift ΔV (hence stored charge) will be retained after ten years.The results also suggest that the negative charge (electrons) de-trapping rate is higher than that of the positive charge (holes).The detrapping of positive charge is well described by a logarithmic time dependence, which could be explained with the detrapping governed by tunnelling processes, that is, electrons/holes tunnel from the dielectric into the substrate (so-called first-order tunneling front model) [42,43].The time dependence of negative charge loss is well described by a ln 2 (t) dependence.It was shown that using the simple model of a capacitor discharging through an impedance [44] based on Poole-Frenkel conduction leads to an expression close to the observed one.More rigorously, the square logarithm retention dependence was derived in [45].Therefore, the charge loss mechanisms of electrons and holes in the stacks are different, which could be assigned to a different origin of the electron and hole charge traps.Stable endurance characteristics corresponding to positive charge build-up have been observed (Figure 7b).The negative charge trapping exhibits larger instabilities-the voltage shift resulting from electron trapping decreases with the number of cycles.The degradation of the memory window during the repeated write/erase operations is most likely due to wear-out mechanisms such as the generation of new bulk shallow traps and charges and interface state generation at the Si interface [46].We have also investigated the radiation hardness of HfO2/Al2O3 CTL [47].For this aim, the as-deposited and annealed 5×(30:10) stacks were subjected to 60 Co γ -irradiation with two radiation doses (10 and 100 kGy).During irradiation, no bias was applied to the We have also investigated the radiation hardness of HfO 2 /Al 2 O 3 CTL [47].For this aim, the as-deposited and annealed 5×(30:10) stacks were subjected to 60 Co γ -irradiation with two radiation doses (10 and 100 kGy).During irradiation, no bias was applied to the device.For both as-grown and O 2 -annealed samples, irradiation does not change the positive charge build-up behavior (Figure 8a,b).On the contrary, it significantly boosts electron trapping in both stacks.The stronger is the increase for as-deposited stacks.Based on these results, one may conclude that γ -irradiation is a viable way to increase the charge storage ability of the stacks.However, the investigation of retention characteristics revealed that despite the increased negative charge trapping, as-deposited stacks have poor retention (Figure 8c).
On the contrary, γ-radiation does not deteriorate the charge retention in oxygen-treated stacks (Figure 8d).The difference in the retention characteristics and the higher detrapping rate of the as-deposited stacks show evidence that radiation-induced traps have different natures than those produced by O 2 annealing and are unsuitable for reliable storage.On the other hand, results demonstrate that the stacks after O 2 annealing have good radiation tolerance to γ-rays up to very high doses of 100 kGy and can be successfully used in CTF devices working in a radiation-intensive environment.
On the contrary, γ-radiation does not deteriorate the charge retention in oxygentreated stacks (Figure 8d).The difference in the retention characteristics and the higher detrapping rate of the as-deposited stacks show evidence that radiation-induced traps have different natures than those produced by O2 annealing and are unsuitable for reliable storage.On the other hand, results demonstrate that the stacks after O2 annealing have good radiation tolerance to γ-rays up to very high doses of 100 kGy and can be successfully used in CTF devices working in a radiation-intensive environment.

Leakage Currents
As mentioned above, the introduction of the Al in the stack does not deteriorate and even reduces the leakage currents for higher Al content in the films (Figure 9a).It has been established that oxygen annealing also decreases the leakage current of the stacks (Figure 9b).(Note that RTA in N2 (Figure 9b) does not improve the leakage current.)The reduction of leakage currents upon various oxygen annealing treatments is frequently reported for

Leakage Currents
As mentioned above, the introduction of the Al in the stack does not deteriorate and even reduces the leakage currents for higher Al content in the films (Figure 9a).It has been established that oxygen annealing also decreases the leakage current of the stacks (Figure 9b).(Note that RTA in N 2 (Figure 9b) does not improve the leakage current.)The reduction of leakage currents upon various oxygen annealing treatments is frequently reported for high-k materials.It is usually associated with the removal of oxygen vacancies accompanied by an elimination of the residuals (mainly carbon groups) from the precursors in the case of CVD and ALD processes.The decrease of the leakage current due to the Al-introduction could be related to some kind of band gap engineering, i.e., increasing the band gap of the stacks.However, the strong correlation between oxygen annealing, Al-content, and charge trapping suggests that there could be an alternative explanation for the leakage data-the leakage current reduction is most likely due to the effect of the trapped charges that modify the internal electric field of the stack.Since the introduction of Al into HfO 2 creates specific trapping centres and oxygen treatment further enhances it, this would lead to leakage reduction.
duction could be related to some kind of band gap engineering, i.e., increasing the band gap of the stacks.However, the strong correlation between oxygen annealing, Al-content, and charge trapping suggests that there could be an alternative explanation for the leakage data-the leakage current reduction is most likely due to the effect of the trapped charges that modify the internal electric field of the stack.Since the introduction of Al into HfO2 creates specific trapping centres and oxygen treatment further enhances it, this would lead to leakage reduction.

Tunneling and Blocking Oxides
Blocking and tunnelling oxides are also important parts of the charge trapping stack.As mentioned above, in the current CTFs, SiO2 is used both as TO and BO.However, with the scaling of CTF cell dimensions, the thickness of TO and BO are also scaled-down, and the direct tunneling current through the thin tunnel SiO2 layer deteriorates the retention characteristics.High-k dielectrics are also considered to replace SiO2 as BO and TO.The use of material with a higher dielectric constant as a blocking layer ensures a lower electric field.Hence, carrier back-injection will be reduced.Substitution of tunnel SiO2 by the high-k dielectric enables the use of physically thicker TO, which can improve retention performance.However, the TO should also be trap-free to avoid trap-assisted tunnelling of the stored charges through the TO.This requirement is not easy to satisfy as the highk dielectrics are trap-rich materials.Among the high-k dielectrics, Al2O3 has the largest band gap (more than 8 eV).Hence, the band-offsets with the CTL and Si will be the largest, which ensures more efficient storage in the quantum well formed by the tri-layer (BO-CTL-TO).Al2O3 also has good chemical and thermal stability and it is CMOS compatible.Several studies have shown that Al2O3 as BO improves the memory window, retention parameters and P/E efficiency and mitigates the problem of erase saturation [48-50].Recently, all-AlOx CTF stack in which BO, TO and CTL are engineered using different gas ratios and pulse times of the ALD process to obtain AlOx layers with different thicknesses and oxygen content has been demonstrated [51].
To investigate the influence of TO and BO on charge storage and reliability of CTF cells, we have prepared full charge trapping stacks consisting of CTL, tunnel and blocking oxides [40].Two different CTLs were used in this case-nanolaminated stacks with 20 cy

Tunneling and Blocking Oxides
Blocking and tunnelling oxides are also important parts of the charge trapping stack.As mentioned above, in the current CTFs, SiO 2 is used both as TO and BO.However, with the scaling of CTF cell dimensions, the thickness of TO and BO are also scaled-down, and the direct tunneling current through the thin tunnel SiO 2 layer deteriorates the retention characteristics.High-k dielectrics are also considered to replace SiO 2 as BO and TO.The use of material with a higher dielectric constant as a blocking layer ensures a lower electric field.Hence, carrier back-injection will be reduced.Substitution of tunnel SiO 2 by the high-k dielectric enables the use of physically thicker TO, which can improve retention performance.However, the TO should also be trap-free to avoid trap-assisted tunnelling of the stored charges through the TO.This requirement is not easy to satisfy as the high-k dielectrics are trap-rich materials.Among the high-k dielectrics, Al 2 O 3 has the largest band gap (more than 8 eV).Hence, the band-offsets with the CTL and Si will be the largest, which ensures more efficient storage in the quantum well formed by the tri-layer (BO-CTL-TO).Al 2 O 3 also has good chemical and thermal stability and it is CMOS compatible.Several studies have shown that Al 2 O 3 as BO improves the memory window, retention parameters and P/E efficiency and mitigates the problem of erase saturation [48][49][50].Recently, all-AlO x CTF stack in which BO, TO and CTL are engineered using different gas ratios and pulse times of the ALD process to obtain AlO x layers with different thicknesses and oxygen content has been demonstrated [51].
To investigate the influence of TO and BO on charge storage and reliability of CTF cells, we have prepared full charge trapping stacks consisting of CTL, tunnel and blocking oxides [40].Two different CTLs were used in this case-nanolaminated stacks with 20 cy HfO 2 and 5 cy Al 2 O 3 repeated five times (5×(20:5)) (Figure 10a) and doped samples with 4 cy HfO 2 and 1 cy Al 2 O 3 repeated 25 times (25×(4:1)) (Figure 10b).As a tunnelling oxide, we used SiO 2 with two thicknesses-2.4 and 3.5 nm, grown by standard thermal oxidation of Si.Stacks with 3 nm Al 2 O 3 as TO, prepared by ALD, are also considered.As a blocking oxide, we used Al 2 O 3 (about 20 nm) deposited under the same ALD conditions as those used for CTL and TO depositions.Al 2 O 3, as a tunnel and blocking oxide, enables the entire charge-trapping stack to be obtained in a single ALD deposition process, significantly simplifying the technology.The as-grown stacks with TO and BO, unlike stacks without TO and BO, demonstrate significant electron trapping.Hence, the memory window substantially increases (Figure 11a).It is seen that positive charge trapping depends on the tunnel oxide (and its thickness) and is weakly affected by the CTL.
On the contrary, the capture of electrons depends on the dielectric-it is stronger in the nanolaminated structures.It should be noticed that similarly to the as-deposited stacks without any TO and BO (Figure 6), the positive charge trapping increases progressively (almost linearly) with Vp, reaching very large values with no tendency for saturation.As discussed, such behaviour is explained by generating stress-induced positively charged defects.In structures with Al2O3 TO, regardless of the CTL, electron trapping is very weak, which makes them unsuitable as memory cells in CTF.On the contrary, the capture of electrons depends on the dielectric-it is stronger in the nanolaminated structures.It should be noticed that similarly to the as-deposited stacks without any TO and BO (Figure 6), the positive charge trapping increases progressively (almost linearly) with Vp, reaching very large values with no tendency for saturation.As discussed, such behaviour is explained by generating stress-induced positively charged defects.In structures with Al2O3 TO, regardless of the CTL, electron trapping is very weak, which makes them unsuitable as memory cells in CTF.On the contrary, the capture of electrons depends on the dielectric-it is stronger in the nanolaminated structures.It should be noticed that similarly to the as-deposited stacks without any TO and BO (Figure 6), the positive charge trapping increases progressively (almost linearly) with V p, reaching very large values with no tendency for saturation.As discussed, such behaviour is explained by generating stress-induced positively charged defects.In structures with Al 2 O 3 TO, regardless of the CTL, electron trapping is very weak, which makes them unsuitable as memory cells in CTF.
The impact of O 2 annealing (Figure 11b) is very similar to that observed for the structures without TO and BO-the trapping of electrons increases significantly, and the positive charge trapping decreases and exhibits a saturation.In other words, these results confirm that after RTA in O 2, the stacks are more resistant to high-electric-field degradation and no positive charge is generated.Consequently, the net positive charge trapping decreases, the net negative charge trapping increases and the two branches of the trapping characteristics become more symmetrical.It should also be noted that compared to as-deposited stacks, the electron and hole trappings start at lower V p .Hence, the CTF can operate at lower voltages, which is one of the requirements the CTFs have to satisfy.The spatial density of trapped electrons, ρ e , and holes, ρ h , for various structures after RTA are calculated to be in the range ρ h = (0.95-1.58) × 10 19 cm −3 and ρ e = (1.2-1.5)× 10 19 cm −3 [40].
The retention characteristics of as-deposited stacks (Figure 12a) indicate that (i) the positive charge retention depends on the TO thickness and is independent of the dielectric stack; (ii) the discharge of positive charge follows a linear law which implies trap-to-band tunnelling mechanism; (iii) the discharge rate of positive charge is higher for stacks with thinner SiO 2 , while for 3.5 nm SiO 2, the discharge rate is very low, i.e., 3.5 nm SiO 2 provides a good barrier to back-tunnelling of holes; (iv) the electron discharge follows different laws for the samples with 2.4 and 3.5 nm SiO 2 .For thinner TO, retention characteristics are linear.Hence, the discharge is performed via trap-to-band tunnelling.For the thicker TO, the characteristics are well fitted by ln 2 (t), which implies electron detrapping via the Poole-Frenkel mechanism; (v) the electron discharge curves of the two types of CTL are parallel to each other at an equal thickness of TO.Hence, the electron traps in the two kinds of charge trapping layers have the same origin, but their density is higher in multilayered 5×(20:5) stacks.The obtained program and erase speeds are illustrated in Figure 14 for capacitors with 2.4 nm TO before and after oxygen annealing.The capacitors exhibit almost negligible electron trapping at pulses shorter than 10 −4 s for the as-grown samples and 10 −3 s for the annealed ones.In both cases, after the threshold pulse time, the electron accumulation in the CTL is rapid.The increase of pulse duration, tp, within one decade results in the Very significant changes in the discharge characteristics and their dependence on the parameters of the structure are provoked by O 2 annealing (Figure 12b).It should be mentioned that these changes are unexpected.Generally, the retention characteristics of stacks are deteriorated after annealing.In addition, the electron discharge rate is higher in structures with a thicker 3.5 nm SiO 2 than stacks with thinner 2.4 nm TO and slightly depends on the CTL.The discharge rate of holes is also higher after RTA and for thicker TO.Considering the obtained results [40] leads to the conclusion that the deteriorated characteristics are most likely due to a high-temperature-induced interaction between the HfO 2 /Al 2 O 3 charge trapping layer and the TO and the formation of defects due to this interaction.These defects, located at the CTL/TO interface and/or in the TO itself, cause a faster discharge of the charges stored in the CTL [52].Defects generated by the annealing in the Al 2 O 3 blocking oxide as a possible leakage path could not be rejected as well.As commented in [51], in Al 2 O 3 deposited by ALD with H 2 O as oxidant, different species such as Al-OH, Al-O-H, Al-Al could be formed, resulting in increased density of defects.In [41], we have demonstrated that annealing in O 2 creates different electrically active defects depending on the Al 2 O 3 thickness in HfO 2 /Al 2 O 3 stacks.In the case of thick (30 cy) Al 2 O 3 , the generation of a negative charge has been observed, accompanied by a substantial increase in leakage current.The retention characteristics of the annealed 5×(20:5) stacks without any intentionally grown TO and BO (Figure 12c) support this conclusion-they are very similar to the retention in stacks with a thicker SiO 2 TO and BO before annealing.The endurance characteristics (Figure 13a) before annealing reveal instabilities, especially in electron trapping.Substantial degradation and progressive accumulation of positive charge have been observed for P/E cycles > 600.This supports the conclusion that the structures before RTA are vulnerable to high electric field stress degradation.After RTA in O 2, the structures demonstrate better endurance and can withstand more than 10 4 P/E cycles without coming to breakdown (BD) (Figure 13b).(~10 times) needed to program the capacitor and return it to its initial state.This result agrees with the degradation of the retention characteristics after annealing and could be related to the defect generation in both the TO and BO layers.However, we should mention that the program/erase speeds obtained with a capacitor type of structure could be affected by the availability of inversion carriers in the Si substrate.As demonstrated in [53], the inversion current of tunnel MOS capacitors on p-type substrates is dominated by the thermal generation rate of minority electrons via traps at the Si/SiO2 interface and in the deep depletion region.Since the thermal generation at room temperature is slow, the measurements are conducted under illumination to neutralize this effect.The obtained program and erase speeds are illustrated in Figure 14 for capacitors with 2.4 nm TO before and after oxygen annealing.The capacitors exhibit almost negligible electron trapping at pulses shorter than 10 −4 s for the as-grown samples and 10 −3 s for the annealed ones.In both cases, after the threshold pulse time, the electron accumulation in the CTL is rapid.The increase of pulse duration, t p, within one decade results in the accumulation of more than 70% of the stored negative charge measured at t p = 1 s.(The overall shape of the dependence ∆V fb vs. t p before and after annealing is the same-steep increase followed by a gradual increment with a tendency of saturation for t p > 1 s).The detrapping of the captured electrons under negative V p does not show abrupt change with the value of t p .The more efficient electron release is observed at t p above 10 −5 s, and the full discharge state is reached at ~10 −2 s and 10 −1 s, for the as-grown and annealed stacks, respectively.The accumulation of positive charge in the CTL ("over-erasing") requires pulse times about 100 times higher than the ones for the electron trapping under the same V p magnitude.Hence, it can be concluded that the annealing increases the pulse duration (~10 times) needed to program the capacitor and return it to its initial state.This result agrees with the degradation of the retention characteristics after annealing and could be related to the defect generation in both the TO and BO layers.However, we should mention that the program/erase speeds obtained with a capacitor type of structure could be affected by the availability of inversion carriers in the Si substrate.As demonstrated in [53], the inversion current of tunnel MOS capacitors on p-type substrates is dominated by the thermal generation rate of minority electrons via traps at the Si/SiO 2 interface and in the deep depletion region.Since the thermal generation at room temperature is slow, the measurements are conducted under illumination to neutralize this effect.
affected by the availability of inversion carriers in the Si substrate.As demonstrated in [53], the inversion current of tunnel MOS capacitors on p-type substrates is dominated by the thermal generation rate of minority electrons via traps at the Si/SiO2 interface and in the deep depletion region.Since the thermal generation at room temperature is slow, the measurements are conducted under illumination to neutralize this effect.It is helpful to compare the obtained results with the performance of conventional CT memory cells with the ONO stack.Ramkumar [15] reported very good endurance characteristics of poly-Si/oxide/nitride/oxide/Si (SONOS) cells with very small shifts of threshold voltage after 10 6 P/E cycles.The retention in the erase state is also very good.However, in the program state at 85 • C, a significant loss of stored charge is observed (more than 50% at ten years).Similar stable retention performance in the erase state and faster detrapping rate in the program state demonstrate our stacks in Figure 12a.In Table 1, memory windows, program speeds and the time needed to reach the full window of ONO stacks reported in different works are given.The memory windows of ONO structures are smaller than those of our HfO 2 /Al 2 O 3 stacks.The program speed of ONO stacks, however, is better-10 −5 s.It should be mentioned that the excellent program speed of cylindrical cells with ONO stacks reported in [59,60] (Table 1) is due to hyperbolic dependence of the electric field along the radial coordinate, which enhances the field at the TO interface while decreasing it at BO interface.In other words, programming speed depends strongly on the device geometry as well as on how the carriers are injected (faster speeds are achieved in the case of hot carrier injection (in the order of µs) as compared to ms in the case of Fowler-Nordheim tunnelling [15] also used in our samples).As mentioned, scaling rules and integration compatibility with CMOS process flow require the replacement of SONOS cells with MOHOS.Many works study charge trapping and storage in different MOHOS structures.Comparison of their properties could be considered only qualitatively because all performance characteristics depend very strongly on the materials used for the different layers in the charge trapping stack and the technology (including deposition technique, deposition parameters and annealing steps).For example, as shown by Agrawal et al. [51], even changing parameters of the deposition process (gas flow ratio and pulse deposition time of precursors) results in Al-oxide layers with substantially different properties in this way allowing the engineering of band-gap of the layer.What concerns ALD, the most widely used technology for highquality quality, very thin high-k dielectric layers, the precursors used for the deposition process are also of utmost importance.Here, we will compare our results with results obtained on similar HfO 2 /Al 2 O 3 stacks prepared by ALD.Consistent with our work, the memory windows reported by other authors [61,62] for CT-NVM with HfO 2 /Al 2 O 3 CTL are substantially larger (8-12 V) than those of ONO stacks.The work of Yoo, et al. [61] confirms the enhancement of the memory window after O 2 annealing.Very good retention of more than 76% at ten years is reported in [62] for samples with optimized Hf:Al ratio.In this work, it is also demonstrated by XPS that Al incorporation reduces oxygen vacancies in HfO 2 -the result is also inferred from our consideration of I-V characteristics of Al-doped HfO 2 (Section 2.1).
All-AlO x CT stacks reported in [51] reveal better retention than the respective stacks with SiN x CTL, further improved by a low-temperature N 2 annealing.These stacks also demonstrate stable erase retention and faster discharge in the program state, consistent with our results and results reported in [15] for ONO.Hou et al. [63] reported very good charge trapping and storage characteristics of HfO 2 /Al 2 O 3 CTL, where better performance is obtained for structures annealed at 1000 • C in N 2.This result is assigned to better intermixing between HfO 2 and Al 2 O 3 at high temperatures and the formation of Hf-rich HfAlO nanocrystals.These authors also suggested [50] short O 3 treatment of Si to obtain better Al 2 O 3 /Si interfacial properties.Improvement of retention by the engineering of tunnelling oxide is suggested in the work of Song et al. [64].They demonstrated by using Synopsis simulations that incorporation of Al 2 O 3 in the tunnelling oxide (i.e., SiO 2 /Al 2 O 3 /SiO 2 stack) results in a significant improvement in retention.All the investigations reported by other authors have been performed on stacks deposited at substantially higher temperatures (250-350 • C) compared to 135 • C, which is used for the deposition of our samples.This low-temperature deposition may be the reason for increased defect density and insufficient performance of Al 2 O 3 as blocking oxide in our samples.Therefore, an increase in the deposition temperature of Al 2 O 3 BO is a possible way to improve its insulating properties.

Conclusions and Perspectives
We have demonstrated that the charge trapping ability of HfO 2 /Al 2 O 3 charge trapping layers could be tailored and enhanced by optimization of stack parameters as well as annealing steps.Aluminium introduces deep traps with high density without compromising the leakage currents.Electron trapping in HfO 2 /Al 2 O 3 stacks is also substantially increased by O 2 annealing.On the other hand, both Al introduction and O 2 annealing reduce oxygen vacancies in HfO 2, thus decreasing the density of shallow traps.They also improve the vulnerability of the stacks to high electric field stress.Therefore, the combination of Al-introduction in HfO 2 and O 2 annealing resulted in improved trapping and storage ability, which manifested as large memory windows and good retention and endurance of CT stacks without any tunnel and blocking layers.The introduction of BO and TO, quite unexpectedly, turns out to be very challenging.Despite the increased electron trapping and improved susceptibility to high-field stress, the structures after high-temperature O 2 annealing demonstrate degraded retention characteristics and increased program time (due most likely to defects generated in the blocking Al 2 O 3 and the interfacial reaction between CTL and TO).The retention of stacks with TO and BO before annealing is good, but their endurance is compromised by the high electric field vulnerability of HfO 2 /Al 2 O 3 stacks without O 2 annealing.
From this point of view, the results (Figure 15) obtained for thicker 10×(30:10) samples without BO and TO, which were subjected to standard thermal annealing in O 2 at lower (600 • C) temperature [41], give some promise.As is seen, the retention and endurance characteristics are significantly better than that of the as-deposited samples with TO and BO (Figure 15a)-more than 75% of charge is retained after 10 6 s and the linear extrapolation shows that after ten years, a significant amount of charge (65%) will still be stored.The structures also show good endurance-∆V changes by ~6% after 2.5 × 10 4 P/E cycles (Figure 15b).In addition, the program speed is faster than an order of magnitude (Figure 15c).(However, we have to note that apart from technological conditions and stack geometry, better programming speed can also be influenced by the initial fixed oxide charge, which is positive with high density for the stack in Figure 15c and negative for stacks in Figure 14, i.e., more detailed investigation is needed).Therefore, the decrease of annealing temperature could be a feasible way toward further optimization and improvement of the performance of CTF cells.Even more fascinating is the idea to design a CTF cell without BO and TO.A CTF without TO and BO is reported in [65] and is considered a viable way for designing a new class of scalable flash memory devices.The device reported in [65] is realized with aluminium oxide phosphate dielectric deposited by spin-coating and processed at low (<200 • C) temperature.Our 10×(30:10) stacks outperform in most parameters the one reported in [65].
Another technology approach that could benefit from the implementation of HfO 2 /Al 2 O 3 CTL stacks is the recently suggested hybrid CT memories, which combine CT functionality with the ferroelectric (FE)/antiferroelectric (AFE) properties of HfO 2 .In this case, combinations of dielectric, FE and AFE variations of HfO 2 are used to tailor voltage distribution across the stack (e.g., enforcing a large electric field on a tunnel barrier and reducing the internal field in CTL).FE/AFE HfO 2 -based layer could be introduced as a part of CTL or even as a BO, and the modulation of an electric field is achieved by the dipole switching, which results in an enhancement of performance characteristics-increased switching speed and robust retention and endurance [66,67].These devices take advantage of the faster polarization switching mechanisms compared to electron injection through TO, which results in increased P/E speed.However, the technology of these multi-layered stacks comprising FE/AFE states is more complicated, and the thermal budget is much higher as it involves high-temperature steps for the crystallization of films.
In the present work, we focused on HfO 2 /Al 2 O 3 stacks from the viewpoint of their implementation in charge-trapping flash memories.It should be mentioned that these stacks are also intensively investigated as a functional part of other computational and memory concepts.The first to mention is the resistive random-access memories (RRAM), which have emerged as one of the most promising alternatives for future NVMs.Moreover, RRAM devices can demonstrate neuronal dynamics.Hence, they are considered for neuromorphic computational applications.RRAM outperforms transistor-type memories regarding high-speed operation, low power consumption and high integration density.Recently, multi-level switching and synaptic behaviour of HfO 2 /Al 2 O 3 stacks have been reported in several papers [68][69][70][71].The enhanced switching performance of these stacks is assigned to the migration of oxygen vacancies due to their different density in HfO 2 and Al 2 O 3 layers [72,73].
multi-layered stacks comprising FE/AFE states is more complicated, and the thermal budget is much higher as it involves high-temperature steps for the crystallization of films.In the present work, we focused on HfO2/Al2O3 stacks from the viewpoint of their implementation in charge-trapping flash memories.It should be mentioned that these stacks are also intensively investigated as a functional part of other computational and memory concepts.The first to mention is the resistive random-access memories (RRAM), which have emerged as one of the most promising alternatives for future NVMs.Moreover, RRAM devices can demonstrate neuronal dynamics.Hence, they are considered for neuromorphic computational applications.RRAM outperforms transistor-type memories regarding high-speed operation, low power consumption and high integration density.Recently, multi-level switching and synaptic behaviour of HfO2/Al2O3 stacks have been reported in several papers [68][69][70][71].The enhanced switching performance of these stacks is assigned to the migration of oxygen vacancies due to their different density in HfO2 and Al2O3 layers [72,73].
In recent years, flexible electronics have become a special interest because of their importance for wearable health management devices, flexible displays, sensors and even artificial skin and soft robotics.The possibility to deposit HfO2-based high-k dielectrics at relatively low temperatures by ALD opens up new horizons for manufacturing devices  In recent years, flexible electronics have become a special interest because of their importance for wearable health management devices, flexible displays, sensors and even artificial skin and soft robotics.The possibility to deposit HfO 2 -based high-k dielectrics at relatively low temperatures by ALD opens up new horizons for manufacturing devices with high stability and mechanical resilience on flexible substrates for application in flexible electronics [74,75].In this regard, thin film transistors (TFT) with active channel material of InGaZnO (IGZO) are considered especially promising [76,77].It has been shown that HfO 2 /Al 2 O 3 stacks can boost the performance of IGZO-based TFTs [78].Integration of HfO 2 /Al 2 O 3 stacks in recently reported synaptic transistors based on IGZO nanofibers [79,80] could be a feasible way to enhance their retention characteristics.It could open new opportunities to realize bio-inspired in-memory computing.Very promising electrical characteristics of bendable and biodegradable metal-oxide-semiconductor field-effect transistors and capacitors fabricated by integrating HfO 2 /Al 2 O 3 high-k bilayers on silicon nanomembranes (Si NMs) and utilizing polymeric substrates have been reported in [81].This demonstrates the potential of these stacks to be utilized in on-demand water-soluble Si NM-based devices toward futuristic applications in disposable electronics and temporary biomedical implants.

Figure 2 .
Figure 2. Schematic comparison between basic MOS transistor structures in floating gate (a) and charge trapping memory devices (b).

Figure 2 .
Figure 2. Schematic comparison between basic MOS transistor structures in floating gate (a) and charge trapping memory devices (b).

Figure 2 .
Figure 2. Schematic comparison between basic MOS transistor structures in floating gate (a) and charge trapping memory devices (b).

Figure 3 .
Figure 3. (a) C-V curves of HAH (36/5/36) sample measured in different voltage ranges (−Vend → +Vend → −Vend).The memory window ΔVC-V is shown.(b) Dependence of memory window ΔVC-V on Vend for different sample structures (Reprinted with permission from [18].Copyright 2015 American Chemical Society).(H denotes the HfO2 sublayer, and A denotes the Al2O3 one.For each sublayer, the number of ALD cycles is given).

Figure 3 .
Figure 3. (a) C-V curves of HAH (36/5/36) sample measured in different voltage ranges (−V end → +V end → −V end ).The memory window ∆V C-V is shown.(b) Dependence of memory window ∆V C-V on V end for different sample structures (Reprinted with permission from [18].Copyright 2015 American Chemical Society).(H denotes the HfO 2 sublayer, and A denotes the Al 2 O 3 one.For each sublayer, the number of ALD cycles is given).

Figure 5 .
Figure 5. Schematic diagram of the HfO 2 /Al 2 O 3 nanolaminated stacks.The used number of repetitions, n of the HfO 2 /Al 2 O 3 bilayer structure is 5 or 10; HfO 2 ALD cycles, x are 20 or 30, and Al 2 O 3 ALD cycles, y, are 2, 5, 10 or 30.The overall stack thicknesses are varied between 15 nm and 65 nm.

Figure 6 .
Figure 6.Evolution of C-V curve position at C = 20 pF with respect to its initial position V0 versus the voltage pulse magnitude: (a) as-grown samples; (b) RTA in O2.Solid symbols correspond to +Vp; hollow to −Vp.(Reprinted with permission from [39].Copyright 2018 John Wiley and Sons).

Figure 6 .
Figure 6.Evolution of C-V curve position at C = 20 pF with respect to its initial position V 0 versus the voltage pulse magnitude: (a) as-grown samples; (b) RTA in O 2 .Solid symbols correspond to +V p ; hollow to −V p .(Reprinted with permission from [39].Copyright 2018 John Wiley and Sons).

Figure 7 .
Figure 7. Retention (a) and endurance (b) characteristics of capacitors with 5×(30:10) stack annealed in O2.Solid lines in (a) represent linear fit of data in erased (after −Vp) state and to c + pln 2 (t), where c and p are constants for the program (+Vp) state.The black line (online colour) is the memory window evolution (right axis scale) (Reprinted with permission from [39].Copyright 2018 John Wiley and Sons).

Figure 7 .
Figure 7. Retention (a) and endurance (b) characteristics of capacitors with 5×(30:10) stack annealed in O 2 .Solid lines in (a) represent linear fit of data in erased (after −V p ) state and to c + pln 2 (t), where c and p are constants for the program (+V p ) state.The black line (online colour) is the memory window evolution (right axis scale) (Reprinted with permission from [39].Copyright 2018 John Wiley and Sons).

Figure 8 .
Figure 8.The evolution of the flat-band voltage changes on applying voltage pulses with different Vp and retention characteristics of the as-grown (a,c) and the O2 annealed stacks (b,d) before and after irradiation [47].

Figure 8 .
Figure 8.The evolution of the flat-band voltage changes on applying voltage pulses with different V p and retention characteristics of the as-grown (a,c) and the O 2 annealed stacks (b,d) before and after irradiation [47].

Figure 11 .
Figure 11.The flat band voltage shifts as a function of voltage pulse amplitude for different memory capacitor types: (a) before annealing; (b) after RTA in O2.Red symbols correspond to +Vp and the blue symbols to −Vp [40].

Figure 11 .
Figure 11.The flat band voltage shifts as a function of voltage pulse amplitude for different memory capacitor types: (a) before annealing; (b) after RTA in O2.Red symbols correspond to +Vp and the blue symbols to −Vp [40].

Figure 11 .
Figure 11.The flat band voltage shifts as a function of voltage pulse amplitude for different memory capacitor types: (a) before annealing; (b) after RTA in O 2 .Red symbols correspond to +V p and the blue symbols to −V p [40].

Nanomaterials 2023 , 21 Figure 12 .
Figure 12.Charge retention characteristics in capacitors with various HfO2/Al2O3 stacks: (a) before and (b) after RTA in O2; (c) 5×(20:5) stack without BO and TO after RTA.The red symbols correspond to a negative charge (respectively, positive values of Vfb) and the blue ones correspond to a positive charge (negative values of Vfb) [40].

Figure 12 .
Figure 12.Charge retention characteristics in capacitors with various HfO 2 /Al 2 O 3 stacks: (a) before and (b) after RTA in O 2 ; (c) 5×(20:5) stack without BO and TO after RTA.The red symbols correspond to a negative charge (respectively, positive values of V fb ) and the blue ones correspond to a positive charge (negative values of V fb ) [40].

Figure 14 .
Figure 14.Dependence of the flat band voltage shifts for program and erase operations on the voltage pulse width, tp for capacitors with BO and 2.4 nm TO, before and after annealing.The programming voltage is +25 V, and the erasing is −25 V.

Figure 14 .
Figure 14.Dependence of the flat band voltage shifts for program and erase operations on the voltage pulse width, t p for capacitors with BO and 2.4 nm TO, before and after annealing.The programming voltage is +25 V, and the erasing is −25 V.

Table 1 .
Comparison of memory windows, program speeds and time to reach the full window of ONO stacks reported in different works.

Table 1 .
Comparison of memory windows, program speeds and time to reach the full window of ONO stacks reported in different works.