Steep-Slope and Hysteresis-Free MoS₂ Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric

Abstract

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS₂ NCFET is fabricated using a single Hf_0.5−xZr_0.5−xAl_2xO_y (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf_0.5Zr_0.5O₂ (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 10⁶. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al₂O₃ stack gates.

1. Introduction

As the size of MOSFETs continues to decrease, it has become increasingly difficult to reduce the size of the device below 10 nm. One reason for this is that the power consumption of the device is difficult to reduce. In traditional MOSFETs, the sub-threshold swing (SS) of the device is limited by the Boltzmann limit, resulting in the chip power consumption failing to reach the expected target [1,2,3,4,5]. To reduce the device power consumption, several novel device models have been proposed to achieve a sub-threshold swing (SS) lower than 60 mV/dec at room temperature. The first type proposed is the nano-electromechanical switch (NEM) [6,7]. The NEM is small and low in power consumption. Its SS can even reach single digits, to much lower than 60 mV/dec. However, the reliability of NEM devices is relatively low and the lack of expandable preparation technology is not conducive to large-scale process production. Another low-power device model is the tunnel field-effect transistor (TFET) [8,9,10,11]. In 2017, Adrian Jonescu proposed using the quantum tunneling effect to make TFETs. TFETs can significantly reduce the driving voltage imposed by the gate and have a very low turn-off current. Their SS can be lower than 60 mV/dec, with greatly reduced power consumption. However, the turn-on current is relatively low and the choice of materials, and the presence of defects in these, significantly impact the development of TFETs. The negative-capacitance field-effect transistor (NCFET) is considered an ideal choice for ultra-low power applications [1,2,4,12,13,14]. It only requires addition of a ferroelectric material as an additional layer to the gate dielectric layer of a traditional MOSFET to act as a negative capacitor to achieve voltage amplification of the channel surface potential, thus breaking the Boltzmann limit such that an SS less than 60 mV/dec can be achieved. At the same time, materials with high dielectric constants, such as HfO₂ and ZrO₂, having much higher dielectric constants than SiO₂, wide band gaps and good thermal stability, are considered excellent gate dielectric materials and have been applied in process mass production. However, in Germany, Johannes Muller et al. reported that ferroelectric properties would appear when different elements, such as Si, Y, Al and Zr, were doped into HfO₂ thin films, [15,16,17]. This discovery resulted in ferroelectric materials and NCFET becoming an international research craze [18,19,20,21]. Using HZO thin film as the ferroelectric layer, HZO NCFETs have become one of the solutions to achieving ultra-low-power CMOS technology. HZO NCFETs have the following advantages: (1) high conduction current; (2) symmetrical circuit layout; and (3) CMOS process compatibility. However, these NCFETs contain at least two layers as the gate stack, which complicates the fabrication process and is not conducive to the scaling down of devices.

In this investigation, a single-layer (HfZr)_0.5−0.5xAl_xO_y (HZAO) thin film was found to have both negative capacitance and positive capacitance due to its ferroelectricity, and, thus, capacitance matching could be realized by itself. A single HZAO layer was used as the gate dielectric to fabricate the relevant MoS₂ NCFETs. By optimizing the Al content and the annealing temperature of the HZAO thin film, excellent electrical properties for NCFETs have been achieved, including a low SS of 22.3 mV/dec over almost four orders of drain-current magnitude, almost no hysteresis, and a high on/off current ratio of 9.4 × 10⁷, which, so far, is better than that achieved with HZO-based MoS₂ NCFETs under the same fabrication and measurement conditions.

2. Experimental Method

Heavily-doped p⁺⁺-Si wafers with a resistivity of 0.005~0.01 Ω·cm were cleaned by a standard RCA method as substrate/back gate and then were placed in an atom-layer deposition (ALD) chamber. As the ferroelectricity of the HZAO thin film is highly dependent on its annealing temperature and atom ratio [19,22,23], HZAO thin films with different atom ratios were prepared through alternately ALD-depositing Al₂O₃, HfO₂ and ZrO₂ at ratios of Al₂O₃:HfO₂:ZrO₂ = 1:5:5 or 1:10:10 or 1:20:20 or 0:1:1 to yield a nano-laminate Hf_0.4Zr_0.4Al_0.2O_y or Hf_0.45Zr_0.45Al_0.1Oy or Hf_0.475Zr_0.475Al_0.05Oy or Hf_0.5Zr_0.5O_y (HZO) thin film on the p⁺⁺-Si substrate using trimethylaluminium (TMA) as the Al source, tetrakis (ethylmethylamino)-Hf (TDMAH) as the Hf source, tetrakis (ethylmethylamino)-Zr (TDMAZ) as the Zr source, and H₂O as the oxidant. During deposition, the temperatures of the substrate and the Hf/Zr sources were 200 °C and 75 °C, respectively. The resultant thicknesses of the thin films were 8.03 nm, 8.01 nm, 8.03 nm, and 8.00 nm, respectively, measured by ellipsometry. The thin films were then annealed by rapid thermal processing (RTP) at 600 °C, 650 °C, 700 °C and 750 °C, respectively, for a duration of 30 s.

MoS₂ flakes were transferred from bulk crystal onto the HZAO or HZO/p⁺⁺-Si substrates by a micromechanical exfoliating method using 3M tapes and PDMS films [24]. Electron-beam lithography (EBL) was used to pattern the source (S) and drain (D) electrodes of the transistors, followed by deposition of 15 nm Cr and 45-nm Au at room temperature by thermal evaporation and a lift-off process to form the S/D electrodes [25,26,27]. The drawn channel length (L) of these transistors was 3 μm and the channel width (W) was 3~5 μm, based on the shape of the flakes. Lastly, the transistors were annealed at 300 °C for 180 s in a N₂ environment to improve the electrical contact between the MoS₂ and metal electrode and to remove the gas and liquid molecules on the MoS₂ [28].

A schematic diagram of a back-gated NCFET is shown in Figure 1a and its optical micrograph is shown in Figure 1b.

3. Results and Discussion

3.1. Optimization of Al Content in HZAO Thin Film

The polarization vs. field (P-E) measurements were carried out on the (Au/Cr)/HZAO/p⁺⁺-Si capacitor to characterize the ferroelectricity of the HZAO thin films at a frequency of 50 Hz at room temperature in light-tight condition, with Au/Cr as the top electrode and p⁺⁺-Si as the bottom electrode. Figure 2a shows the P-E curves of the Hf_0.4Zr_0.4Al_0.2O_y, Hf_0.45Zr_0.45Al_0.1O_y, Hf_0.475Zr_0.475Al_0.05O_y and Hf_0.5Zr_0.5O samples; the inset shows the extracted ferroelectric parameters. The Hf_0.475Zr_0.475Al_0.05O_y thin film exhibited the strongest ferroelectricity, with a total remnant polarization (2|Pr|) of 15.22 μC/cm² and a Pr/Ec ratio of 9.06 pF/cm (Ec is the coercive field), indicating that the ferroelectricity of the HZO thin film could be enhanced by incorporation of Al with a suitable content (e.g., 5% Al in an HZO thin film).

The capacitance-voltage (C-V) curves of the (Au/Cr)/HZAO/p++-Si capacitors were measured by an Agilent 4284A precision LCR meter. Figure 2b shows the C-V curves of the HZAO thin films with different Al contents under 5 kHz frequency. A sharp capacitance peak can be observed around 0 V; the higher peak indicates stronger ferroelectricity and a negative-capacitance effect [29]. For the conventional (Cr/Au)/HfO₂/p-Si MOS capacitor in Figure 2c, we did not observe a capacitance peak, which would exclude the impact of stresses or high frequency signals. The Hf_0.475Zr_0.475Al_0.05O_y thin film exhibited the highest capacitance peak, which was consistent with the P-E measurement result, indicating that the strongest ferroelectricity was for the Hf_0.475Zr_0.475Al_0.05O_y thin film. The peaks indicate that the single layer HZAO film had both positive- and negative-capacitance characteristics and was able to achieve capacitance-matching by itself without another positive capacitance layer.

The drain current vs. gate-source voltage (I_d-V_gs) curves of the transistors were measured using a Keithley 4200 SCS semiconductor parameter analyzer in a light-tight and electrically-shielded probe station in an atmospheric pressure environment at room temperature, as shown in Figure 3a. The sweeping range of V_gs was from −1 V to 3 V, with a sweeping rate of 0.2 V/s and drain-source voltage (V_ds) fixed at 50 mV. The SS-I_d relations were extracted from the transfer curves and are shown in Figure 3b.

Table 1. Electrical parameters of HZAO NCFETs with different Al contents extracted from their transfer curves (annealing temperature of 600 °C).

Sample	Hf0.4Zr0.4Al0.2Oy	Hf0.45Zr0.45Al0.1Oy	Hf0.475Zr0.475Al0.05Oy	Hf0.5Zr0.5Oy
Ioff (pA/μm)	0.3~1	0.3~1	0.3~1	0.3~1
Ion (μA/μm)	1.1~1.2	1.9~2.2	2.5~2.8	1.5~1.7
Mobility (cm2/Vs)	35.8~38.4	35.6~38.5	36.2~38.7	35.5~37.8
SS (mV/dec)	35.0~45.1	24.4~26.9	22.3~25.6	28.8~40.6
Hysteresis (mV)	30~50	15~20	5~10	20~30
VTH (V)	0.55~0.60	0.15~0.20	0.10~0.15	0.40~0.45

lists the off-current (I_off), on-current (I_on), mobility, SS and hysteresis of the HZAO NCFETs with different Al contents, which were extracted from their relevant transfer curves.

From Figure 3 and Table 1, it can be seen that the HZAO NCFETs with different Al contents exhibited similar I_off and mobility, indicating that the insulation integrity of the HfZrO thin film was not influenced by the incorporation of Al atoms. It is especially worth noting that the Hf_0.475Zr_0.475Al_0.05O_y NCFET (Al content of 5%) exhibited the lowest SS (22.3 mV/dec) over almost four orders of I_d magnitude, the largest I_on (2.8 μA/μm) and the smallest hysteresis (~10 mV) among all the samples, i.e., a suitable Al-doped concentration was determined to be 5%, at which a high switching speed from the off-state to the on-state can be obtained. In addition, comparison of electrical properties between the single-layer HZAO and traditional multi-layer gate stack NCFETs was performed, as shown in Figure 3c and

Table 2. Electrical parameters of the HZAO NCFETs and HZO-Al₂O₃ NCFETs.

Gate Stack	8 nm HZAO	6 nm HZO +2 nm Al2O3
Ioff (pA/μm)	0.3~1	0.3~1
Ion (μA/μm)	2.5~2.8	1.4~1.6
Mobility (cm2/Vs)	36.2~38.7	35.8~37.5
SS (mV/dec)	22.3~25.6	33.5~41.4
Hysteresis (mV)	5~10	40~50
VTH (V)	0.10~0.15	0.25~0.30

. For the same thickness of the gate stack, the former exhibited better electrical parameters than the latter. According to the formulas of SS = $\left(ln10\right)\times \left(\frac{k_{B}T}{q}\right)\times \left(1+\frac{C_s+C_{it}}{C_{ox}}\right)$ and $C_{it}=q^2{D}_{it}$ [30], the interface-state density between MoS₂ and positive HZAO was determined to be in a range of (2.75~2.94) × 10¹² eV⁻¹cm⁻², which would not lead to relatively large hysteresis.

3.2. Optimization of Annealing Temperature

Based on the above results, the Hf_0.475Zr_0.475Al_0.05O_y thin film was selected to investigate its optimum annealing temperature. The P-E curves of the Hf_0.475Zr_0.475Al_0.05O_y thin films annealed at 600 °C, 650 °C, 700 °C and 750 °C, respectively, are shown in Figure 4a. The 700 °C annealed Hf_0.475Zr_0.475Al_0.05O_y thin film exhibited the strongest ferroelectricity, with |2P_r| of 15.76 μC/cm² and a P_r/E_c ratio of 9.27 pF/cm.

The C-V curves of the (Au/Cr)/Hf_0.475Zr_0.475Al_0.05O_y/p⁺⁺-Si capacitors for different annealing temperatures were measured at 5 kHz, as shown in Figure 4b. The Hf_0.475Zr_0.475Al_0.05O_y thin film annealed at 700 °C exhibited the highest capacitance peak, which was consistent with the P-E measurement result, supporting it exhibiting the strongest ferroelectricity, as shown in Figure 4a.

The I_d-V_gs curves and the SS-I_d curves of the Hf_0.475Zr_0.475Al_0.05O_y NCFETs for different annealing temperatures are shown in Figure 5a,b, respectively; the relevant electrical parameters extracted from their transfer curves are listed in Table 2.

From Figure 5 and

Table 3. Zr_0.475Al_0.05O_y NCFETs with different annealing temperatures (T) extracted from their transfer curves.

T (°C)	600	650	700	750
Ioff (pA/μm)	0.3~1	0.3~1	0.3~1	0.3~1
Ion (μA/μm)	2.5~2.8	2.4~2.6	2.5~2.8	1.5~1.7
Mobility (cm2/Vs)	36.2~38.7	36.6~38.3	36.4~38.7	35.2~37.4
SS (mV/dec)	22.3~25.6	22.3~25.6	20.4~23.1	30.3~40.7
Hysteresis (mV)	5~10	0	−5~−10	40~50
VTH (V)	0.10~0.15	0.05~0.10	0~0.05	0.20~0.25

, it can be observed that the Hf_0.475Zr_0.475Al_0.05O_y NCFET annealed at 700 °C exhibited the lowest SS (20.4 mV/dec) by almost four orders of I_d magnitude with a very small anticlockwise hysteresis of −5~−10 mV, attributed to its enhanced ferroelectricity (large P_r/E_c ratio and |2P_r|), as shown in Figure 4a, resulting in a large ferroelectric capacitance (|C_FE|) and, thus, a better capacitance match [31,32]. However, the 650 °C-annealed NCFET exhibited the second lowest SS (22.3 mV/dec) without hysteresis. This is because the hysteresis of the MoS₂ NCFETs is influenced by both the interface states and the NC effect. The hysteresis caused by interfacial defaults is clockwise [33] and an anticlockwise hysteresis is introduced by the NC effect of the ferroelectric thin film [1]. So, the total hysteresis for the MoS₂ NCFETs, with HZAO as the gate dielectric, is a sum of the two kinds of hysteresis [34]. Assuming a consistent interface property for the MoS₂ NCFETs annealed at 650 °C and 700 °C, i.e., that the two samples have the same clockwise hysteresis, the total hysteresis depends on their anticlockwise hysteresis. For the 650 °C annealed Hf_0.475Zr_0.475Al_0.05O_y NCFET, its clockwise hysteresis just counteracted its anticlockwise hysteresis, resulting in hysteresis-free behavior. For the 700 °C-annealed Hf_0.475Zr_0.475Al_0.05O_y NCFET, its anticlockwise hysteresis was slightly larger than its clockwise hysteresis, resulting in a total anticlockwise hysteresis of −5~−10 mV (almost hysteresis-free behavior). Therefore, it is suggested that a reasonable range for the annealing temperature is 650 °C~700 °C.

To support the electrical results, X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) measurements were undertaken on the HZAO thin films for different Al contents and annealing temperatures to investigate their crystal structure. Figure 6a,b show the XRD patterns of the HZAO thin films with different Al contents and annealing temperatures, respectively. The diffraction peaks occurring at around 30.5° and 36° are attributed to the orthorhombic phase [16,35,36]; a higher peak implies an enhanced orthorhombic phase and, thus, stronger ferroelectricity [19,37]. The 5%Al content and 700 °C annealed HZAO thin films exhibited the highest diffraction peaks, indicating the strongest ferroelectricity, which is consistent with the P-E measurement results shown in Figure 2a and Figure 4a.

Figure 6c,d show the Hf 4f, Zr 3d, Al 3p and Q 1s XPS spectra of the Hf_0.475Zr_0.475Al_0.05O_y and Hf_0.45Zr_0.45Al_0.1O_y thin films, respectively. The percentage of the Al element in the two thin films was 2.62% and 5.33%, respectively, based on calculation of the Al 3p/O1s peak-area ratio. Similarly, the Hf 4f/O 1s and Zr 3d/O 1s ratios were calculated to be 48.23% and 46.53%, for the Hf_0.475Zr_0.475Al_0.05O_y sample, and 45.36% and 43.98%, for the Hf_0.45Zr_0.45Al_0.1O_y sample. So, their chemical formulae were Hf_0.4823Zr_0.4653Al_0.0524O_y and Hf_0.4536Zr_0.4398Al_0.1066O_y, respectively, which is consistent with the atom ratios of the ALD-yielded HZAO thin films, confirming the validity of the electrical results.

4. Conclusions

In this investigation, back-gated MoS₂ NCFETs with a single HZAO layer as the gate dielectric were successfully fabricated. The effects of Al content and annealing temperature on the device performances were investigated. It was found that the 700°C-annealed Hf_0.475Zr_0.475Al_0.05O_y (5%Al content) NCFET exhibited the lowest SS (~20 mV/dec), the highest I_on/I_off (9.1~9.8 × 10⁶) and almost hysteresis-free behavior, attributed to its strong ferroelectricity and NC effects. The 650°C-annealed Hf_0.475Zr_0.475Al_0.05O_y NCFET exhibited better comprehensive performances, including low SS (~22 mV/dec), no hysteresis and a high I_on/I_off ratio [(8.8~9.5) × 10⁶], attributed to its second strongest ferroelectricity and the excellent balance between anticlockwise hysteresis from the NC effect and clockwise hysteresis from the HZAO/MoS₂ interface.

XRD, C-V and P-E measurements were used to confirm the ferroelectricity of the Hf_0.5−0.5xZr_0.5−0.5xAl_xO_y thin films with different Al contents and annealed at different temperatures, indicating strong ferroelectricity for the Hf_0.475Zr_0.475Al_0.05O_y samples annealed at 650~700 °C, with higher diffraction peaks of the orthorhombic phase and C-V peaks relevant to the NC effect, and large P_r. Compared to single HZO layer and gate-stacked NCFETs, the single HZAO layer gate-dielectric NCFET has significant potential for small-scale and low-power devices due to its excellent sub-threshold properties and simplified preparation process.