Search Results (1,271)

A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal with a high-conversion-gain (HCG) signal. However, the signal-to-noise ratio (SNR) drops at the switching point from HCG signal to LCG signal due to the significant pixel noise in the LCG signal. To address this issue, a triple-gain LOFIC CIS with a middle-conversion-gain (MCG) signal has been introduced. In this work, we propose an area-efficient readout circuit for the triple-gain LOFIC CIS, using amplifier and capacitor sharing techniques to process the HCG, MCG, and LCG signals. A test chip of the proposed readout circuit was fabricated using the $0.18\mathsf{\mu }$m CMOS process. The area overhead was only $7.6\%$, and the SNR drop was improved by $8.05$ dB compared to the readout circuit for a dual-gain LOFIC CIS. Full article

Molecular quantum-dot cellular automata (QCA) are attracting much attention as an alternative that can improve the problems of digital circuit design technology represented by existing CMOS technology. In particular, they are well suited to the upcoming nanoquantum environment era with their small size, fast switching speed, and low power consumption. In this study, we propose a 5 × 5 × 1 ultra-slim vertical panel type multi-layer 2-to-1 multiplexer (Mux) using molecular QCA, departing from conventional multi-layer formats, and show its expansion to 4-to-1 Mux and application to vertical panel type D-latch and RAM cells. In addition, the polarization phenomenon of cells is physically proven using the potential energy, distance among electrons, and the relative positions of cells, and the secure RAM design takes noise elimination and polarization of the output signal into consideration. The circuits are simulated in terms of operation and performance using QCADesigner 2.0.3 and QCADesignerE, and the proposed multi-layer 2-to-1 Mux shows a significant improvement of at least 1473% and 277% in two representative standard design costs compared to the state-of-the-art multi-layer Muxes. Full article

This work presents a low-power photoplethysmography (PPG) readout integrated circuit (IC) that achieves a wide dynamic range (DR) through the direct integration of a voltage-controlled oscillator (VCO)-based quantizer into the photodiode driver. Conventional PPG readout circuits rely on either transimpedance amplifier (TIA) or light-to-digital converter (LDC) topologies, both of which require auxiliary DC suppression loops. These additional loops not only raise power consumption but also limit the achievable DR. The proposed design eliminates the need for such circuits by embedding a linear regulator with a mirroring scale calibrator and a time-domain quantizer. The quantizer provides first-order noise shaping, enabling accurate extraction of the AC PPG signal while the regulator directly handles the large DC current component. Post-layout simulations show that the proposed readout achieves a signal-to-noise-and-distortion ratio (SNDR) of 40.0 dB at 10 µA DC current while consuming only 0.80 µW from a 2.5 V supply. The circuit demonstrates excellent stability across process–voltage–temperature (PVT) corners and maintains high accuracy over a wide DC current range. These features, combined with a compact silicon area of 0.725 mm² using TSMC 250 nm bipolar–CMOS–DMOS (BCD) process, make the proposed IC an attractive candidate for next-generation wearable and biomedical sensing platforms. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

Recently, with the rapid development of underwater resource exploration and underwater activities, underwater acoustic (UA) target recognition has become crucial in marine resource exploration. However, traditional underwater acoustic recognition systems face challenges such as low energy efficiency, poor accuracy, and slow response times. Systems for UA target recognition using deep learning networks have garnered widespread attention. Convolutional neural network (CNN) consumes significant computational resources and energy during convolution operations, which exacerbates the issues of energy consumption and complicates edge deployment. This paper explores a high-energy-efficiency UA target recognition system. Based on the DenseNet CNN, the system uses fine-grained pruning for sparsification and sparse convolution computations. The UA target recognition CNN was deployed on FPGAs and chips to achieve low-power recognition. Using the noise-disturbed ShipsEar dataset, the system reaches a recognition accuracy of 98.73% at 0 dB signal-to-noise ratio (SNR). After 50% fine-grained pruning, the accuracy is 96.11%. The circuit prototype on FPGA shows that the circuit achieves an accuracy of 95% at 0 dB SNR. This work implements the circuit design and layout of the UA target recognition chip based on a 65 nm CMOS process. DC synthesis results show that the power consumption is 90.82 mW, and the single-target recognition time is 7.81 ns. Full article

To enhance the RF power properties of CMOS-compatible gold-free GaN devices, this work introduces a kind of GaN-on-Si HEMT with a low parasitic regrown ohmic contact technology. Attributed to the highly doped n⁺ InGaN regrown layer and smooth morphology of gold-free ohmic stacks, the lowest ohmic contact resistance (R_c) was presented as 0.072 Ω·mm. More importantly, low RF loss and low total dislocation density (TDD) of the Si-based GaN epitaxy were achieved by a designed two-step-graded (TSG) transition structure for the use of scaling-down devices in high-frequency applications. Finally, the fabricated GaN HEMTs on the Si substrate presented a maximum drain current (I_drain) of 1206 mA/mm, a peak transconductance (G_m) of 391 mS/mm, and a breakdown voltage (V_BR) of 169 V. The outstanding material and DC performances strongly encourage a maximum output power density (P_out) of 10.2 W/mm at 8 GHz and drain voltage (V_drain) of 50 V in active pulse mode, which, to our best knowledge, updates the highest power level for gold-free GaN devices on Si substrates. The power results reflect the reliable potential of low parasitic regrown ohmic contact technology for future large-scale CMOS-integrated circuits in RF applications. Full article

This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits. Full article

The rapid growth of artificial intelligence (AI), data centers, and high-performance computing (HPC) has increased the demand for large bandwidth, high energy efficiency, and high-density optical interconnects. Co-packaged optics (CPO) technology offers a promising solution by integrating photonic integrated circuits (PICs) directly within or close to electronic integrated circuit (EIC) packages. This paper explores the evolution of CPO performance from various perspectives, including fan-out wafer level packaging (FOWLP), through-silicon via (TSV)-based packaging, through-glass via (TGV)-based packaging, femtosecond laser direct writing waveguides, ion-exchange glass waveguides, and optical coupling. Micro ring resonators (MRRs) are a high-density integration solution due to their compact size, excellent energy efficiency, and compatibility with CMOS processes. However, traditional thermal tuning methods face limitations such as high static power consumption and severe thermal crosstalk. To address these issues, non-volatile neuromorphic photonics has made breakthroughs using phase-change materials (PCMs). By combining the integrated storage and computing capabilities of photonic memory with the efficient optoelectronic interconnects of CPO, this deep integration is expected to work synergistically to overcome material, integration, and architectural challenges, driving the development of a new generation of computing hardware with high energy efficiency, low latency, and large bandwidth. Full article

This paper proposes a second-order low-pass Butterworth multiple-feedback (MFB) filter with a reconfigurable bandwidth and gain, implemented in a 28 nm CMOS. The filter supports independent tuning of the bandwidth from 10 MHz to 100 MHz and the gain from 0 dB to 19 dB, effectively addressing the challenge of a tightly coupled gain and quality factor in traditional MFB designs. Notably, compared to the widely adopted Tow–Thomas structure, the proposed filter achieves second-order filtering and the same degree of flexibility using only a single operational amplifier (OPA), significantly reducing both the power consumption and area. Additionally, an RC tuning circuit is employed to reduce fluctuations in the RC time constant under process, voltage, and temperature (PVT) variations. To meet the requirements for high linearity and low power consumption in broadband applications, a three-stage push–pull OPA with current re-use feedforward and an RC Miller compensation technique is proposed. With the current re-use feedforward, the OPA’s loop gain at 100 MHz is significantly enhanced from 22.34 dB to 28.75 dB, achieving a 2.14 GHz unity-gain bandwidth. Using this OPA, the filter achieves a 48.2 dBm in-band (IB) OIP3, a 53.4 dBm out-of-band (OOB) OIP3, and a figure of merit (FoM) of 185.5 dBJ⁻¹ at a100 MHz bandwidth while consuming only 3.6 mW from a 1.8 V supply. Full article

This paper presents a temperature-robust current-mode vertical-cavity surface-emitting laser (VCSEL) driver (or CMVD) fabricated in a standard 180 nm CMOS process. While prior art relies on conventional current-mirror circuits for bias generation, the proposed CMVD integrates a bandgap-based biasing architecture to achieve high thermal stability and process insensitivity. The bandgap core yields a temperature-compensated reference voltage and is then converted into both stable bias and modulation currents through a cascode current-mirror and switching logic. Post-layout simulations of the proposed CMVD show that the reference voltage variation remains within ±2%, and the bias current deviation is under 10% across full PVT conditions. Furthermore, the output current variation is limited to 7.4%, even under the worst-case corners (SS, 125 °C), demonstrating the reliability of the proposed architecture. The implemented chip occupies a compact core area of 0.0623 mm² and consumes an average power of 18 mW from a single 3.3 V supply, suggesting that the bandgap-stabilized CMVD is a promising candidate for compact, power-sensitive optical systems requiring reliable and temperature-stable performance. Full article

This paper presents the design and implementation of a 6-bit high-precision active vector-sum phase shifter (PS) operating in the E-band, fabricated using a 40 nm CMOS process. To generate high-quality in-phase and quadrature (I/Q) signals, a folded transformer-based quadrature generator circuit (QGC) employing inductive compensation is developed. Additionally, the series peaking enhancement technique is applied to improve overall gain and effectively extend the bandwidth. Measurement results demonstrate that the phase shifter achieves a 3 dB bandwidth from 72.3 GHz to 82.3 GHz. Within this range, the measured RMS phase error is merely 1.78–2.55 degrees without calibration, and the RMS gain error is 0.6–0.75 dB. The core area of the proposed phase shifter is 940 μm × 280 μm, and it consumes 57.2 mW of power with a 1.1 V supply. Full article

This paper proposes a balanced dynamic Time Division Multiple Access bus architecture with a novel selectable–sequence–counter arbitration circuit. Most existing dTDMA-related studies focus on wireless communications, which involve significantly different architectural assumptions, design constraints, and implementation platforms compared to digital bus systems. Our comparative analysis was carried out against the only available implementation in the literature, aligning to the target domain of digital buses. The proposed SSC-based arbiter, evaluated on a 65 nm CMOS process, demonstrates superior performance, achieving substantial reductions in area and power consumption with an approximated linear resource scaling as the number of connected devices to the bus increases, unlike the quadratic growth in the conventional architecture. Thus, this work offers a practical and yet efficient novel dTDMA architecture solution for on-chip communication. Full article

This paper introduces a compact analog configuration that concurrently realizes a mixed-mode biquadratic filter and a dual-mode quadrature oscillator (QO) by employing a single differential differencing gain amplifier (DDGA) and all-grounded passive components. The proposed design supports four fundamental operation modes—voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM), and trans-admittance-mode (TAM)—utilizing the same circuit topology without structural modifications. In filter operation, it offers low-pass, high-pass, band-pass, band-stop, and all-pass responses with orthogonal and electronic pole frequency and quality factor. In oscillator operation, it delivers simultaneous voltage and current quadrature outputs with independent tuning of oscillator frequency and condition. The grounded-component configuration simplifies layout and enhances its suitability for monolithic integration. Numerical simulations in a 0.18-μm CMOS process with ±0.9 V supply confirm theoretical predictions, demonstrating precise gain-phase characteristics, low total harmonic distortion (<7%), modest sensitivity to 5% component variations, and stable operation from −40 °C to 120 °C. These results, combined with the circuit’s low component count and integration suitability, suggest strong potential for future development in low-power IoT devices, adaptive communication front-ends, and integrated biomedical systems. Full article

Multipliers are crucial components in digital processing and the arithmetic logic unit (ALU) of central processing unit (CPU) design. As the data bit length increases, the number of partial products in the multiplication process increases, resulting in an increased summation time for the partial products. Consequently, the speed of the multiplier circuit is adversely affected by increased time delays. In this article, we present a combined radix-4 Booth encoding module that employs metal–oxide–semiconductor (MOS) transistors that share common control signals to reduce the transistor count. In HSPICE simulations, the functionality of the proposed circuit architecture was verified, and the number of transistors used was successfully reduced. Full article