A Low-Power, Wide-DR PPG Readout IC with VCO-Based Quantizer Embedded in Photodiode Driver Circuits

Abstract

This work presents a low-power photoplethysmography (PPG) readout integrated circuit (IC) that achieves a wide dynamic range (DR) through the direct integration of a voltage-controlled oscillator (VCO)-based quantizer into the photodiode driver. Conventional PPG readout circuits rely on either transimpedance amplifier (TIA) or light-to-digital converter (LDC) topologies, both of which require auxiliary DC suppression loops. These additional loops not only raise power consumption but also limit the achievable DR. The proposed design eliminates the need for such circuits by embedding a linear regulator with a mirroring scale calibrator and a time-domain quantizer. The quantizer provides first-order noise shaping, enabling accurate extraction of the AC PPG signal while the regulator directly handles the large DC current component. Post-layout simulations show that the proposed readout achieves a signal-to-noise-and-distortion ratio (SNDR) of 40.0 dB at 10 µA DC current while consuming only 0.80 µW from a 2.5 V supply. The circuit demonstrates excellent stability across process–voltage–temperature (PVT) corners and maintains high accuracy over a wide DC current range. These features, combined with a compact silicon area of 0.725 mm² using TSMC 250 nm bipolar–CMOS–DMOS (BCD) process, make the proposed IC an attractive candidate for next-generation wearable and biomedical sensing platforms.

1. Introduction

Photoplethysmography (PPG) is one of the most widely adopted non-invasive techniques for monitoring physiological conditions such as heart rate, oxygen saturation, and vascular health. The technique relies on illuminating tissue with a light source and measuring the intensity of the reflected or transmitted light using a photodiode. Variations in the optical signal correspond to blood volume changes and can be digitized for clinical or wearable health applications. Owing to its simplicity and low cost, PPG has become central to consumer health devices, ranging from smartwatches to ambulatory monitoring systems [1,2,3,4,5,6,7,8].

Despite its advantages, the design of efficient PPG readout electronics remains challenging. A conventional solution is the transimpedance amplifier (TIA), which converts photodiode current to voltage before digitization. Although TIAs achieve high linearity, they suffer from large DC offsets and require additional suppression loops, which consume power and degrade efficiency. Several works have attempted to mitigate these drawbacks through feedback techniques, gain-boosted architectures, or digitally assisted calibration [9,10,11,12,13]. Another approach is the light-to-digital converter (LDC), which integrates the photodiode current directly and employs incremental conversion schemes. LDCs extend the DR compared to TIAs, but they too depend on auxiliary DC rejection paths and often require complex calibration to maintain accuracy [14,15,16,17,18]. As summarized in prior studies, these conventional schemes result in unnecessary power overhead and architectural inefficiencies, especially in portable applications where battery life is critical.

To overcome these limitations, time-based signal processing has recently emerged as a compelling alternative. By embedding the quantization process directly into the current regulation path of the photodiode driver, the need for explicit DC suppression is removed. Frequency-to-digital conversion (FDC) techniques offer inherent first-order noise shaping, in which quantization noise is suppressed in the signal band and shifted toward higher frequencies, allowing precise recovery of small AC components in the presence of large DC currents. VCO-based quantizers in particular provide compact implementation and high energy efficiency, making them attractive for biomedical readout ICs [19,20,21,22,23].

In this work, we propose a low-power PPG readout IC that integrates a VCO-based quantizer into the sensor driver’s linear regulator. The design introduces a mirroring scale calibrator that stabilizes oscillation frequency under process and temperature variations. Extensive simulations, including PVT corners and DC current sweeps, confirm that the proposed readout achieves high SNDR, robust transient behavior, and excellent load regulation while consuming less than 1 µW. Compared with prior art, the circuit demonstrates a significantly improved figure-of-merit (FoM), validating its suitability for wearable and biomedical sensing systems.

2. Prior State-of-the-Art Designs

The design of PPG readout circuits has evolved over the past two decades, with two major families dominating the literature: transimpedance amplifier (TIA)-based readouts and light-to-digital converter (LDC)-based readouts. Both approaches provide workable solutions but share fundamental inefficiencies, particularly in handling the large DC component of photodiode current. In this section, we review representative circuits from each family and highlight their limitations.

2.1. TIA-Based Readout Circuits

The TIA remains the most classical solution for PPG sensing, as shown in Figure 1. By converting the photodiode current directly into voltage, followed by analog-to-digital conversion, TIAs offer excellent linearity and compatibility with conventional mixed-signal systems. However, in practice the photodiode generates a large DC offset current, sometimes exceeding the signal of interest by several orders of magnitude. To accommodate this, TIAs are typically augmented with DC suppression loops, such as digitally controlled feedback, automatic gain control, or baseline wander correction [9,10,11,12,13].

While these techniques improve dynamic range, they introduce significant overhead. First, the suppression loop consumes additional current, conflicting with the low-power requirements of wearable systems. Second, the ADC following the TIA must support a wide input range, which reduces its effective resolution for the small AC component of the PPG waveform. Finally, the inclusion of large passive components (feedback resistors or capacitors) leads to increased area and design complexity.

Figure 1 illustrates the generalized architecture of a TIA-based PPG readout. The feedback network regulates the transimpedance gain while the suppression loop cancels part of the DC current. Nevertheless, the residual offset and power inefficiency remain problematic for continuous monitoring in battery-operated platforms.

2.2. LDC-Based Readout Circuits

To address the inefficiency of current-to-voltage conversion, researchers proposed direct light-to-digital conversion (LDC), as depicted in Figure 2. In this architecture, the photodiode current is integrated onto a capacitor, and the accumulated charge is digitized by an incremental converter [14,15,16,17,18]. This method inherently supports wider dynamic range compared to TIA-based designs, since it processes current in the charge domain rather than voltage domain.

Despite these advantages, LDCs are not free from limitations. Similarly to TIAs, a separate DC suppression loop is still required, as the photodiode’s DC current must be rejected to avoid saturating the integrator. Moreover, LDCs often rely on higher-order calibration to correct nonlinearity, which complicates design and increases system cost. Another drawback is the relatively high latency of incremental conversion, making it less suitable for real-time wearable applications where rapid tracking of physiological signals is essential.

Figure 2 summarizes the principle of an LDC-based PPG readout. The sensor current is fed directly into an integrator and then quantized. Although it removes the explicit voltage conversion stage, the structure suffers from calibration complexity and limited energy efficiency when compared with more recent approaches. In summary, both TIA- and LDC-based readout architectures suffer from fundamental drawbacks such as large DC offsets, additional suppression circuitry, calibration complexity, and power inefficiency, which limit their suitability for compact and ultra-low-power wearable applications.

2.3. System-Level Inefficiencies

In both families, the photodiode driver must provide a stable bias voltage to ensure proper sensor operation. This requires a regulation loop that delivers a constant current or voltage reference. Unfortunately, much of this supplied current is wasted in suppressing the unnecessary DC component. As a result, overall power consumption increases, while noise from the suppression loop couples into the signal path. These systemic inefficiencies have motivated alternative architectures that bypass explicit DC suppression and directly digitize the AC signal component.

The next section introduces our proposed solution, which embeds a time-based quantizer into the sensor driver itself. This integration not only eliminates the need for a DC suppression circuit but also enables highly efficient and compact readout suitable for low-power biomedical devices.

3. Proposed Readout IC

To address the inefficiencies of conventional PPG readout architectures, this work proposes a fully integrated readout IC in which the quantizer is embedded directly into the photodiode driver. By combining regulation, current sensing, and time-domain quantization within a single loop, the design eliminates the need for a separate DC suppression circuit. This section describes the overall architecture, the linear regulator-based driver, the VCO-based quantizer, and the mirroring scale calibrator that stabilizes circuit operation.

3.1. Overall System Architecture

The block diagram of the proposed system is shown in Figure 3. Unlike prior designs where sensor biasing and signal quantization are performed by separate circuits, here the linear regulator that drives the photodiode also serves as the entry point for signal conversion. The embedded quantizer processes the AC component of the photodiode current directly in the time domain, while the regulator handles the DC bias current. This integration minimizes redundant current paths and achieves high power efficiency.

3.2. Linear Regulator-Based Sensor Driver

The detailed implementation of the sensor driver is illustrated in Figure 4. A PMOS pass device regulates the photodiode bias voltage, ensuring stable sensor operation across a wide current range. The photodiode current is split into two parts: the DC component flows through the main transistor to maintain bias, while the AC component is mirrored to a scaled-down branch for sensing. This dual role of the regulator—both biasing and current partitioning—removes the need for external suppression circuits. As a result, overall power consumption is reduced while maintaining wide dynamic range.

3.3. Embedded VCO-Based Quantizer

The signal path includes a current-controlled oscillator (CCO), as shown in Figure 5. The mirrored AC current modulates the oscillation frequency of the CCO, which consists of cascaded inverter stages. The frequency variation is then digitized by a frequency-to-digital converter (FDC). This time-domain approach offers several advantages:

• The quantizer exhibits inherent first-order noise shaping, improving accuracy for small signals.
• The direct current-to-frequency conversion avoids the inefficiencies of current-to-voltage conversion required in TIA-based circuits.
• The digital nature of the output simplifies subsequent processing and is robust against analog mismatches.

3.4. Mirroring Scale Calibrator

Process and temperature variations cause frequency drift in the oscillator, which can degrade readout accuracy. To compensate, the proposed design incorporates a mirroring scale calibrator, shown in Figure 6. The calibrator dynamically adjusts the effective transistor sizing in the current mirror branch. A digital counter monitors the oscillator frequency, and when deviation from the target frequency is detected, the counter incrementally enables or disables unit transistors in the mirrored branch. This counting-based resizing mechanism ensures stable oscillation frequency without analog trimming. As a result, the system maintains consistent performance across corners and environmental variations, while adding negligible power and area overhead.

4. Performance Evaluation

The proposed PPG readout IC was verified through extensive post-layout simulations in a standard 250 nm CMOS process. Simulations were performed across typical operating conditions as well as process–voltage–temperature (PVT) variations to evaluate robustness. The results demonstrate that the circuit achieves both ultra-low power consumption and wide dynamic range while maintaining stable operation under diverse conditions.

4.1. Output Spectrum Across Process Corners

Figure 7 presents the simulated output spectrum of the proposed readout across multiple process (Figure 7a) corners (SS, FF, SF, and FS) and (Figure 7b) temperature. In each case, the photodiode current was modeled as a sinusoidal input signal riding on a large DC bias. The results confirm that the embedded quantizer consistently achieves high signal-to-noise-and-distortion ratio (SNDR) and maintains spectral integrity regardless of corner conditions. This robustness highlights the effectiveness of the mirroring scale calibrator in compensating frequency drift.

4.2. Output Spectrum Under Different DC Currents

The impact of varying photodiode DC bias current on signal quality was also examined. Figure 8 shows the output spectrum for DC current levels of 1 µA, 10 µA, 50 µA and 100 µA. Across this wide operating range, the AC signal is accurately captured without distortion, and the noise floor remains low. These results verify that the circuit maintains a wide dynamic range without requiring external suppression loops, making it well-suited for wearable sensors that encounter large variations in ambient light conditions.

4.3. SNDR Versus DC Current

Figure 9 plots the SNDR as a function of DC current. The curve demonstrates that the readout achieves stable performance across a broad bias range, with SNDR values consistently above 35 dB even at the extremes. This confirms that the architecture effectively isolates the useful AC component from the large DC offset inherent in photodiode outputs.

4.4. Transient Response

Figure 10 evaluates the transient behavior of the sensor driver when subjected to sudden changes in photodiode current. Both load-transient and line-transient conditions were simulated. The regulator recovers rapidly from step changes in sensor current while maintaining output voltage stability. This fast response ensures reliable biasing of the photodiode under dynamic physiological conditions, such as abrupt motion or illumination changes.

4.5. Load Regulation

The load regulation characteristics are shown in Figure 11. As the load current increases from 100 nA to 35 mA, the regulated output voltage drops only marginally (from 2.0002 V to 1.9996 V), corresponding to 0.03% deviation. This excellent regulation demonstrates that the driver can reliably support wide load variations while minimizing voltage fluctuation, a key requirement for low-noise PPG sensing.

4.6. Area and Power Efficiency

The complete layout of the proposed readout IC is presented in Figure 12a. The design occupies a compact area of 0.725 mm², making it suitable for integration in multi-channel sensor systems. The small footprint, combined with ultra-low power operation, enables deployment in space- and energy-constrained wearable platforms. Figure 12b presents the power breakdown of the proposed readout. As shown, the time-based quantizer dominates the power usage, accounting for approximately 66% of the total. The 31-stage current-controlled oscillator contributes about 29%, while the calibration circuit consumes only 5%.

4.7. Performance Summary and Comparison

A summary of the circuit performance is provided in

Table 1. Performance comparison.

	[9]	[10]	[11]	[12]	[13]	[14]	[15]	[16]	[17]	[18]	This Work
Process (nm)	180	40	180	350	65	180	180	180	180	180	250
SNR (dB)	39.4	41	>30	58.6	>80	41.9	82.31	79.2	120	61.4	40.0
Power Consumption (µW)	216.6	3.75	87	50.75	64.4	15.7	89	61	28	9.84	0.80
FoMSNR a (dB/µW)	0.182	10.93	0.345	1.155	1.242	2.668	0.925	1.298	4.286	6.239	50.0
Area/CH (mm2)	1.56	0.91	4.6	3.91	4.96	2.30	3.36	4.2	4.65	2.40	0.725
Architecture	RC-TIA	RC-TIA	RC-TIA	RC-TIA	R-TIA	LDC	LDC	LDC	LDC	SAR-LDC	Time-based Quantizer
FS b (Hz)	165	100	50	200	20	250	512	2000	2048	1536	10,000
Max DC Bias Current (µA)	100	15	N/A	24	N/A	51.2	30	50	200	460	100
DC Suppression Circuit loop	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes	no
DC Dynamic Range (dB)	N/A	N/A	N/A	N/A	92	108	119	95	134	148.9	60

^a Figure-of-Merit_SNR = SNR/Power Consumption. ^b F_S = Sampling Frequency.

, which compares the proposed work against representative prior state-of-the-art designs. The results clearly show that the design achieves superior energy efficiency, with a figure-of-merit (FoM) of 50.0 dB/µW, significantly outperforming recent TIA- and LDC-based solutions. Unlike previous architectures that require dedicated suppression loops, the proposed readout eliminates redundant current paths while delivering competitive SNDR and area efficiency.

5. Discussion

A major noise source in PPG readout circuits is DC variation (drift) due to ambient light changes and motion artifacts. In the proposed design, the linear regulator absorbs the large DC component while the VCO-based quantizer with inherent noise shaping extracts the AC signal robustly. This approach mitigates DC drift without requiring an explicit cancelation loop.

The simulation results confirm that the proposed readout architecture achieves a unique combination of low power, wide dynamic range, and robustness across variations. Several design choices contribute to these outcomes. First, integrating the quantizer within the sensor driver avoids redundant current paths and eliminates the need for explicit DC suppression, leading to an ultra-low power consumption of only 0.80 µW. This is significantly lower than recent TIA- and LDC-based circuits, as highlighted in Table 1. Second, the use of a mirroring scale calibrator ensures that the oscillator frequency remains stable against process and temperature variations, a challenge that commonly limits time-based quantizers. The counting-based resizing mechanism requires only minimal digital overhead yet provides substantial improvement in stability.

Another critical advantage is the figure-of-merit (FoM) achieved. The design reports 50.0 dB/µW, a value that is orders of magnitude higher than many previously published circuits. This metric demonstrates that the proposed solution delivers superior energy efficiency without sacrificing accuracy. Moreover, the inclusion of PVT corner simulations and DC current sweeps underscores the robustness of the approach, giving confidence that the architecture will perform reliably in real-world wearable environments where conditions vary continuously.

While the present work focuses on single-channel operation, the compact area (0.725 mm²) leaves ample room for scaling to multi-channel implementations in future work. Furthermore, the digital-friendly output of the VCO-based quantizer aligns well with system-on-chip integration, enabling straightforward coupling with digital signal processors for feature extraction. Overall, the architecture bridges the gap between traditional analog-intensive designs and modern low-power, time-domain approaches.

6. Conclusions

This paper presented a low-power, a wide-dynamic-range PPG readout IC that integrates a VCO-based quantizer directly into the photodiode driver, extended from [24]. By eliminating the need for a dedicated DC suppression circuit, the proposed design achieves both reduced power consumption and simplified architecture. The linear regulator-based driver manages the DC component efficiently, while the embedded quantizer digitizes the AC signal with first-order noise shaping. A novel mirroring scale calibrator stabilizes oscillator frequency against process and temperature variations through a counting-based transistor sizing mechanism.

Post-layout simulations demonstrated that the readout achieves an SNDR of 40.0 dB at 10 µA bias current while consuming less than 1 µW from a 2.5 V supply. The circuit maintained high performance across PVT corners and over a wide range of DC currents, validating its robustness. With an occupied area of only 0.725 mm², the design is well-suited for wearable and biomedical sensing platforms that demand compactness and energy efficiency.

Compared to prior works, the proposed architecture delivers a substantially improved energy efficiency figure-of-merit, making it a strong candidate for integration in next-generation health monitoring devices. Future work will explore multi-channel implementations and chip-level measurements to further validate the design in practical applications. In particular, multi-channel integration requires addressing challenges such as channel-to-channel interference, increased power consumption, and synchronization of parallel readout paths. In addition, chip fabrication and measurement with real PPG sensors will be carried out to verify robustness under varying ambient conditions and user motion, ensuring practical applicability in wearable healthcare systems. Furthermore, multi-channel operation will necessitate enhanced digital back-end processing, including higher data throughput and adaptive algorithms for artifact reduction.