An E-Band High-Precision Active Phase Shifter Based on Inductive Compensation and Series Peaking Enhancement Techniques

Abstract

This paper presents the design and implementation of a 6-bit high-precision active vector-sum phase shifter (PS) operating in the E-band, fabricated using a 40 nm CMOS process. To generate high-quality in-phase and quadrature (I/Q) signals, a folded transformer-based quadrature generator circuit (QGC) employing inductive compensation is developed. Additionally, the series peaking enhancement technique is applied to improve overall gain and effectively extend the bandwidth. Measurement results demonstrate that the phase shifter achieves a 3 dB bandwidth from 72.3 GHz to 82.3 GHz. Within this range, the measured RMS phase error is merely 1.78–2.55 degrees without calibration, and the RMS gain error is 0.6–0.75 dB. The core area of the proposed phase shifter is 940 μm × 280 μm, and it consumes 57.2 mW of power with a 1.1 V supply.

1. Introduction

With the rapid advancement of industries such as automotive electronics, intelligent transportation, and industrial automation, coupled with the growing demand for high-speed, low-latency, and large-capacity wireless communication, millimeter-wave (mm-wave) wireless communication has emerged in recent years as a frontier in communication technology research. In particular, during the later stages of 5G evolution and in upcoming 6G systems, the mm-wave frequency band—with its abundant spectrum resources—has become widely recognized as a key enabler of ultra-high-data-rate transmission. Among these, high-speed wireless communication standards operating in the E-band (71–76 GHz and 81–86 GHz) have attracted significant attention, with related products and applications advancing rapidly. Within the family of mm-wave communication technologies, beamforming based on phased array systems has been extensively adopted across diverse scenarios due to its advantages in dynamic beam steering, enhanced signal quality, and interference suppression [1,2]. As the core component for implementing beamforming, the phase shifter (PS) plays a critical role, as its performance directly determines the beam accuracy and direction control capabilities of the system [3,4]. Currently, PSs are mainly divided into two categories: passive [5,6,7,8] and active types [9,10,11,12]. Passive structures include switch-type [13], reflective-type [14], and load–transmission-line types. Although these circuits feature relatively simple architectures, they generally suffer from drawbacks such as high insertion loss, large chip area, and limited control flexibility, which restrict their suitability for highly integrated systems. In contrast, active PSs offer clear advantages in terms of phase resolution, tuning speed, insertion loss, and integration density, making them particularly well-suited for mm-wave phased array systems that demand high frequency, high speed, and compact design. With the continued advancement of CMOS processes in the mm-wave frequency band, active PS implementations not only achieve better cost efficiency but also provide the technological foundation for large-scale system integration. Consequently, as a critical building block, the research and application of active PSs in modern mm-wave communication systems have become increasingly important, drawing growing attention from both academia and industry.

With the widespread use of phased array systems in high-frequency communication and radar applications, PS technology is encountering several new technical challenges: (1) PSs experience impedance fluctuations during phase state transitions, which can negatively impact the stability of the overall link gain. (2) Active PSs, due to their higher gain, can compensate for the losses in high-frequency millimeter waves, making them more commonly used in phased array systems than passive phase shifters. However, the quadrature generator circuit (QGC) of active PSs, when operating at high-frequency millimeter waves, is susceptible to parasitic effects that degrade both amplitude and phase performance at the output, ultimately affecting phase shifting accuracy. (3) Active PSs typically incorporate a digital-to-analog converter (DAC) array, which relies on numerous switching devices, potentially influencing both the overall link gain and bandwidth.

To address these challenges, several technical solutions have been proposed. For the issue of impedance fluctuations during PS phase switching, ref. [15] introduced a hybrid structure combining a 5-bit passive phase shifter with a 1-bit active PS. To enhance gain stability across different phase states, the passive PS employs a compensation technique with constant insertion loss, achieved by integrating an NMOS transistor into each module as an attenuator. This stabilizes insertion loss and ensures consistent link gain across phase states, though at the cost of increased area overhead due to the additional passive PS. To mitigate parasitic effects in the QGC, which degrade overall performance, ref. [16] proposed a self-calibration method that leverages on-chip calibration to improve PS accuracy. However, this approach increases both the phase-shifting response time and chip area. Finally, to address bandwidth limitations in the mm-wave frequency range, stagger-tuning technology is commonly employed in amplifiers, trading off some gain and area efficiency to achieve wider bandwidth.

Different from the mentioned designs, this paper proposes a complementary switch-type DAC array to address the impedance fluctuation issue during phase switching. Additionally, series peaking enhancement is employed to further improve the PS’s bandwidth and gain. To mitigate the impact of parasitic effects on the QGC, an inductance-compensated QGC based on a folded transformer structure is proposed, using inductance compensation to alleviate the deteriorating effects of parasitic elements. To verify the effectiveness of the overall concept and technology, this paper uses the TSMC 40 nm CMOS process for design and fabrication, and its validity is verified through testing. The structure of the paper is as follows: Section 2 presents the circuit design, including the compact impedance-compensated QGC and complementary switch-type I/Q path DAC. In addition, the series peaking enhancement technique and driver module are also analyzed in this section. Section 3 provides a comprehensive overview of the test results and performance analysis, including S-parameters, RMS gain error, and RMS phase error, as well as other key performance metrics that are critical to the evaluation of PS’s overall functionality and efficiency. Section 4 provides the conclusion, and also shows performance summary and comparisons to previous mm-wave PSs.

2. Circuit Design of the Proposed PS

The schematic of the proposed PS is shown in Figure 1. The design integrates a compact impedance-compensated, capacitor-free QGC; a common-source (CS) amplifier; an I/Q DAC array with a 6-bit decoder for phase control; and a three-stage driver module. For measurement purposes, baluns are incorporated at both the input and output ports. The impedance-compensated, capacitor-free QGC is engineered to generate high-quality differential I/Q signals, while a transformer-based interstage matching network is employed between the QGC and the CS amplifier to maximize power transfer. The 6-bit I/Q DACs and decoder are co-designed to enable efficient vector summation, and series-peaking inductors are introduced between the CS amplifier and DACs to extend the overall bandwidth.

Figure 1. Schematic of the proposed PS.

2.1. Compact Impedance-Compensated and Capacitor-Free QGC

The QGC is employed to generate two equal-amplitude orthogonal signals. Building on the QGC described in [17], this section introduces an inductance-compensated QGC, which features four differential ports: input, coupling, through, and isolation ports. In the actual layout, three of the QGC ports (input, coupling, and through) are connected to external modules via metal traces, which effectively introduce inductance. To ensure optimal amplitude and phase performance, a compensating inductance is added at the isolation port, as depicted in Figure 2.

Figure 2. Schematic diagram of inductively compensated QGC.

The following analysis discusses the impact of the introduced equivalent inductance on the QGC. For an ideal QGC, its S-parameters can be expressed as (1)

$$S_{\mathrm{original}}=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{-j}{\sqrt{2}}}& {\displaystyle \frac{1}{\sqrt{2}}}\\ 0& 0& {\displaystyle \frac{1}{\sqrt{2}}}& {\displaystyle \frac{-j}{\sqrt{2}}}\\ {\displaystyle \frac{-j}{\sqrt{2}}}& {\displaystyle \frac{1}{\sqrt{2}}}& 0& 0\\ {\displaystyle \frac{1}{\sqrt{2}}}& {\displaystyle \frac{-j}{\sqrt{2}}}& 0& 0\end{array}\right]$$

(1)

where port 1 represents the input port, port 2 is the isolation port, port 3 is the through port, and port 4 is the coupling port.

From S_original, S41 = jS31 and S33 = S44, indicating that the matching conditions for the two output ports (through port and coupling port) are consistent, and the amplitude-phase performance is excellent.

The Z-matrix can be derived using (2) as

$${Z_{\mathrm{original}}=Z}_0 \times (I+{ S}_{\mathrm{original}}) \times {(I-S_{\mathrm{original}})}^{-1}$$

(2)

where Z₀ = 50 Ω, and I is the 4th-order identity matrix.

When an equivalent inductance L is added to ports 1, 3, and 4, resulting in an equivalent series impedance of jωL, the new Z-matrix is

$$Z_1=Z_{\mathrm{original}}+j\omega L·\mathrm{diag}(1,0,1,1)$$

(3)

Next, the Z-matrix is converted into S-parameters, and the new four-port S-parameters are obtained as

$$S_1=(Z_1-Z_{0}I) \times { (Z_1+{ Z}_{0}I)}^{-1}.$$

(4)

Assuming the added inductance is small, i.e., ωL ≪ Z₀, then

$$S_1=\left[\begin{array}{cccc}-{\displaystyle \frac{L\omega }{-L\omega +2Z_{0}j}}& -{\displaystyle \frac{2L{Z}_0\omega {\mathsf{\sigma }}_2}{{\mathsf{\sigma }}_6^2}}& {\mathsf{\sigma }}_5& {\displaystyle \frac{2\sqrt{2}{Z_0}^2}{{\mathsf{\sigma }}_7^2}}\\ {\displaystyle \frac{2L{Z}_0\omega }{{\mathsf{\sigma }}_7^2}}& {\displaystyle \frac{L^3{\omega }^3{\mathsf{\sigma }}_{1}j}{{\mathsf{\sigma }}_6^3}}& {\mathsf{\sigma }}_4& -{\displaystyle \frac{2\sqrt{2}{Z}_0(-{\mathsf{\sigma }}_8+2L{Z}_0\omega j+2{Z_0}^2)j}{{\mathsf{\sigma }}_7^3}}\\ {\mathsf{\sigma }}_5& {\mathsf{\sigma }}_4& {\displaystyle \frac{L\omega (-{\mathsf{\sigma }}_8+{\mathsf{\sigma }}_3+2{Z_0}^2)j}{{\mathsf{\sigma }}_7^3}}& {\displaystyle \frac{2L{Z_0}^2\omega }{{\mathsf{\sigma }}_7^3}}\\ -{\displaystyle \frac{2\sqrt{2}{Z_0}^2{\mathsf{\sigma }}_2}{{\mathsf{\sigma }}_6^2}}& {\displaystyle \frac{2\sqrt{2}{Z}_0{\mathsf{\sigma }}_1(L^2{\omega }^{2}j+2L{Z}_0\omega -2{Z_0}^{2}j)}{{\mathsf{\sigma }}_6^3}}& {\displaystyle \frac{2L{Z_0}^2\omega {\mathsf{\sigma }}_1}{{\mathsf{\sigma }}_6^3}}& {\displaystyle \frac{L\omega {\mathsf{\sigma }}_1({-\mathsf{\sigma }}_8+{\mathsf{\sigma }}_3+6{Z_0}^2)j}{{\mathsf{\sigma }}_6^3}}\end{array}\right]$$

(5)

where ${\mathsf{\sigma }}_1={(2Z_0-L\omega j)}^3$, ${\mathsf{\sigma }}_2={(L\omega +2Z_{0}j)}^2$, ${\mathsf{\sigma }}_3=4{LZ}_0\omega j$, ${\mathsf{\sigma }}_4={\displaystyle \frac{-4\sqrt{2}{Z_0}^2(-L\omega +Z_{0}j)j}{{\mathsf{\sigma }}_7^3}}$, ${\mathsf{\sigma }}_5={\displaystyle \frac{-2\sqrt{2}{Z_0}^{2}j}{{\mathsf{\sigma }}_7^2}}$, ${\mathsf{\sigma }}_6={\mathsf{\sigma }}_8+4{Z_0}^2$, ${\mathsf{\sigma }}_7=2Z_0+L\omega j$, ${\mathsf{\sigma }}_8=L^2{\omega }^2$.

In S₁, S41 = jS31 and S33 ≠ S44, indicating that the two output ports cannot simultaneously achieve matching while maintaining reliable amplitude-phase performance. After adding a compensation inductance L to port 2, the new four-port S-parameters, derived through the same process, are shown as

$$S_2=\left[\begin{array}{cccc}{\mathsf{\sigma }}_1& {\mathsf{\sigma }}_2& {\mathsf{\sigma }}_4& {\mathsf{\sigma }}_3\\ {\mathsf{\sigma }}_2& {\mathsf{\sigma }}_1& {\mathsf{\sigma }}_3& {\mathsf{\sigma }}_4\\ {\mathsf{\sigma }}_4& {\mathsf{\sigma }}_3& {\mathsf{\sigma }}_1& {\mathsf{\sigma }}_2\\ {\mathsf{\sigma }}_3& {\mathsf{\sigma }}_4& {\mathsf{\sigma }}_2& {\mathsf{\sigma }}_1\end{array}\right]$$

(6)

where

• ${\mathsf{\sigma }}_1={\displaystyle \frac{L\omega (L^7{\omega }^7+2L^6{Z_0\omega }^{6}j-10L^5{{Z_0}^2\omega }^5-12L^4{{Z_0}^3\omega }^{4}j+32L^3{{Z_0}^4\omega }^3+32L^2{{Z_0}^5\omega }^{2}j+16L{Z_0}^6\omega +32{Z_0}^{7}j)}{{\mathsf{\sigma }}_6}}$,
• ${\mathsf{\sigma }}_2=-{\displaystyle \frac{2L{Z_0}^2\omega (-{\mathsf{\sigma }}_5+2L^4{Z_0\omega }^4+4L^3{{Z_0}^2\omega }^{3}j+8{L^2{Z_0}^3\omega }^2+24L{Z_0}^4\omega j-16{Z_0}^5)}{{\mathsf{\sigma }}_6}}$,
• ${\mathsf{\sigma }}_3={\displaystyle \frac{4\sqrt{2}{Z_0}^3({\mathsf{\sigma }}_5-3L^4{Z_0\omega }^4-8L^3{{Z_0}^2\omega }^{3}j+4{L^2{Z_0}^3\omega }^2-8L{Z_0}^4\omega j+8{Z_0}^5)}{{\mathsf{\sigma }}_6}}$,
• ${\mathsf{\sigma }}_4=-{\displaystyle \frac{2\sqrt{2}{Z_0}^2(-L^6{\omega }^{6}j+2L^5{Z_0\omega }^5+6L^4{{Z_0}^2\omega }^{4}j+16L{Z_0}^5\omega +16{Z_0}^{6}j)}{{\mathsf{\sigma }}_6}}$,
• ${\mathsf{\sigma }}_5=L^5{\omega }^{5}j$, ${\mathsf{\sigma }}_6=L^8{\omega }^8-8{L^6{Z_0}^2\omega }^6+32L^4{{Z_0}^4\omega }^4+64L^2{{Z_0}^6\omega }^2+64L{Z_0}^8$.

In S₂, S41 = jS31 and S33 = S44, indicating that the two output ports can achieve matching while maintaining excellent amplitude-phase performance.

The above analysis uses an ideal model to illustrate the improvement effect of adding compensation inductance to the QGC. In practical circuit layouts, the equivalent inductance introduced by metal traces at the three ports is not identical, and there is usually the influence of parasitic capacitance. Therefore, the S-parameters will become more complex. To verify the effectiveness of the proposed QGC with compensation inductance, a circuit simulation is performed. The QGCs with and without inductive compensation structures are placed in the phase shifting module for simulation, and their respective RMS phase errors are calculated. The results are shown in Figure 3. The simulation results indicate that after adding inductance at the isolation port of the QGC, the RMS phase error of the PS is improved. At a frequency of 77 GHz, the RMS phase error without inductance is 2 degrees, while with the added inductance, it improves to 1.6 degrees, which is a 20% performance enhancement. The compensation inductor is 41.5 pH at 77 GHz in this design.

Figure 3. RMS phase error of phase shifting module with and without compensation inductance.

2.2. Complementary Switch-Type I/Q Path DAC Design

The circuit schematic of the I/Q dual DAC array is shown in Figure 4. I+/I− and Q+/Q− are the differential input ports, and OUT+/OUT− are the differential output ports. The transistors in the DAC are controlled by a 6-bit decoder for their on and off states. To achieve high-precision phase synthesis, the width ratio of the transistors in the same group is set to 1:2:4:8:16:32. The minimum transistor size is 850 nm.

Figure 4. Schematic of complementary switch-type I/Q Path DAC.

One of the core challenges in PS design is ensuring the stability of the impedance across different phase states; otherwise, it can complicate the design of the matching network. At the same time, impedance instability can alter the signal transmission characteristics, leading to phase errors. To address this issue, the transistors in the DAC array adopt a complementary switch structure [18]. As shown in Figure 5, the I/Q dual DAC array and the driving amplifier below form a cascade structure. A and B are the output control bits of the 6-bit decoder, with values ranging from 000000 to 111111. M1 to M4 are the drive amplifier transistors of the same size. Above the M1 transistor, two sets of transistors are connected. The left set is controlled by A, and the right set is controlled by $\overline{\mathrm{A}}$ (the inverse of A), forming a complementary switch structure. Regardless of the value of A, there are always six transistors conducting and six transistors off above the M1 transistor, ensuring that the current through M1 remains stable. The principles of M2 to M4 transistors are the same, and the impedance remains unchanged under different phase states.

Figure 5. Cascade structure formed by the DAC array and the driver amplifier.

To verify the stable impedance characteristics of the complementary switch structure, a test circuit for the corresponding differential structure was set up. The I+/I− ports serve as the differential input ports, while OUT+/OUT− are the differential output ports. The logical combinations of control signals are used to achieve different phase states. Figure 6a shows the simulation results of S11 and S22 in the range of 73–83 GHz under different phase states. The results indicate that the DAC array using complementary switches maintains stable input and output impedance, which is beneficial for the design of the matching network.

Figure 6. Simulation results of (a) S11 and S22 and (b) S21 with different techniques.

2.3. Series Peaking Enhancement Technique

The schematic of the CS amplifier is shown in Figure 7. To improve stability, two neutralization capacitors are employed. While the complementary DAC structure ensures stable input and output impedance, the increased number of transistors results in a significant rise in equivalent parasitic capacitance. This, in turn, limits the phase shifter’s bandwidth and gain. To mitigate this issue, series peaking inductors are inserted between the CS amplifier and DAC array, creating a resonant circuit with the parasitic capacitance. To optimize the bandwidth, the LC resonant frequency is selected as the center frequency.

Figure 7. Circuit schematic of the CS amplifier, series inductance, and DAC array.

To verify the improvement effect of series/parallel resonance on overall bandwidth and gain, circuit validation is performed using the 77 GHz frequency band as an example. The results are shown in Figure 6b. For the 77 GHz frequency band, the 3 dB bandwidth was 7.6 GHz without inductance. When series or parallel inductance is added, the 3 dB bandwidth increases to 10 GHz and 11.4 GHz, respectively, yielding improvements of 31.5% and 50%. In this design, the series inductance option is chosen, as it not only enhances the bandwidth but also significantly optimizes the PS’s gain. The specific analysis can be concluded as follows.

(1)

Bandwidth Optimization: By adding series inductance, the 3 dB bandwidth of the PS increases from 7.6 GHz to 10 GHz, a 31.5% increase. This improvement alleviates the frequency deviation effects during testing, reducing the risk of the measured frequency deviating from the target frequency band, thereby enhancing the stability of the results.

(2)

Gain Enhancement: The introduction of series inductance significantly improves the peak gain of the PS (an increase of 1.3 dB), thus optimizing the transmitter link gain. This improvement reduces the design complexity of the subsequent power amplifier and enhances the overall link efficiency.

2.4. Driver Module Design

The schematic of the driver module is shown in Figure 8. The driver module consists of three cascaded CS amplifiers, each incorporating neutralization capacitors to ensure stability [19]. Compact transformers are employed to achieve input, interstage, and output matching. The driver module amplifies the output signal of the phase shift module by 16 dB, thereby providing sufficient signal power for the subsequent stage following the phase shifter.

Figure 8. Schematic of the driver module.

2.5. Large-Signal Simulation Results

The simulation results of the RMS phase error, large-signal gain and OP1dB for the proposed PS are shown in Figure 9. Herein, Figure 9a,b present the simulation results at 77 GHz under the condition of maximum S21, while Figure 9c shows the simulated OP1dB across different frequency bands for this state. The large-signal gain reaches 6.25 dB, and the RMS phase error remains below 2° within the normal operating input power range.

Figure 9. Simulation results of (a) RMS phase error, (b) power gain versus input power and (c) OP_1dB.

2.6. Process/Temperature Variation and Monte Carlo Analysis

Figure 10a,b present the simulated results of the RMS phase error and RMS gain error of the proposed design under different temperatures and process corners. In every case, the RMS phase error is limited to under 2.5°, with the RMS gain error stayed below 1.9 dB.

Figure 10. The process/temperature variation in (a) RMS phase error and (b) RMS gain error.

Figure 11a,b illustrate the bandwidth (BW) and gain (Gain) results obtained from 500 sample Monte Carlo simulations. It can be observed that the bandwidth exhibits a relatively concentrated performance range, remaining stable with a mean value close to 10.8 GHz. Regarding gain distribution, a large proportion of samples fall within the range of 6–8 dB, indicating a favorable degree of concentration.

Figure 11. The Monte Carlo simulation results for (a) bandwidth and (b) gain.

3. Measurement Results

The chip micrograph of the proposed 6-bit PS is shown in Figure 12a. The design is implemented in 40 nm CMOS technology, occupying a core area of 940 µm × 280 µm. At a supply voltage of 1.1 V, the circuit draws a DC current of 52 mA, corresponding to a power consumption of 57.2 mW. Figure 12b presents the test setup for the proposed PS, utilizing a Keysight N5290A PNA Series 110 GHz millimeter-wave network analyzer, sourced from USA. First, solder the chip onto the PCB board and use gold wire bonding to connect the relevant pads to the PCB test board. Signals are transmitted via GSG probe needle contact. Before testing, verify the DC operating condition of the chip using a voltmeter and ammeter. Once confirmed normal, perform relevant calibrations, and finally test its S-parameters and large-signal performance.

Figure 12. (a) Chip photograph of the proposed 6-bit PS. (b) Test setup for the proposed PS.

The measured and simulated results are presented in Figure 13. The PS achieves a 3 dB bandwidth of 72.3 GHz to 82.3 GHz. Within this bandwidth, the measured S21 ranges from 0.5 dB to 3 dB, which is approximately 2 dB lower than the simulated values, while the measured S22 remains below −7.3 dB.

Figure 13. S parameter of the proposed PS.

The proposed PS provides a full 360° phase-shifting range with a minimum phase resolution of 5.625°. The measured relative phase-shifting responses for all 64 states are shown in Figure 14. As illustrated in Figure 14a, the variation in S21 at 77 GHz across different phase states is 3.4 dB. Figure 14b presents the phase response of S21 for the 64 states, where minimal overlap between the phase curves is observed, indicating satisfactory phase performance.

Figure 14. The measurement results of S21 for different phase shifting states: (a) amplitude and (b) phase.

The RMS phase error and RMS gain error are summarized in Figure 15. The RMS phase error remains below 2.55° over the 72.3–82.3 GHz band, while the RMS gain error is less than 0.75 dB. Across the entire frequency range, the RMS phase error does not exceed 2.8°, meeting the 5.625° phase resolution requirement.

Figure 15. The measurement results of RMS phase error and RMS gain error.

4. Conclusions

In this paper, an E-band 6-bit high-precision active PS is proposed. The PS employs a compact capacitor-free QGC with inductive compensation to generate a high-quality quadrature signal for low RMS errors. In addition, the series peaking enhancement technique is applied to improve the operational bandwidth. The core area of the proposed PS is 940 um × 280 um. The proposed PS exhibits a measured peak gain of 5.1 dB at 77 GHz, and 3 dB bandwidth from 72.3 to 82.3 GHz. Within the 3 dB bandwidth, the RMS phase error is as low as 1.78–2.55 deg without calibration, and the RMS gain error is 0.6–0.75 dB. The performance of the PS is summarized and compared with previous mm-wave PSs in Table 1. The proposed PS offers advantages in terms of compact size and high precision, making it well-suited for large-scale phased array systems operating in the E-band.

Table 1. Performance summary and comparison to previous mm-wave PSs.

Refs	CMOS Process	Frequency (GHz)	Resolution (bits)	RMS Phase Error (deg)	RMS Gain Error (dB)	Peak Gain (dB)	DC Power (mW)	Core Area (mm2)	FoM (dB)
This work	40 nm	72.3–82.3	6	1.78–2.55	0.6–0.75	5.1	57.2	0.26	86.4
[20]	28 nm	78.8–92.8	4	9.4–11.9	1.68–2	2.3	21.6	0.12	66.8
JSSC’17
[21]	65 nm	79 *	5	6.74	1.89	−11.4	24.7	0.14	35.5 *
MWCL’18
[22]	65 nm	51–66.3	5	7	0.72	−1.8	5	0.3	67.6
TMTT’20
[23]	28 nm	55–64	5	3.3	0.47	−3.02	15.4	0.41	64.4
MWCL’21
[24]	40 nm	52–57	6	2.8–3.76	2.07–2.23	−9	14.3	0.15	56.5
MWCL’18
[13]	65 nm	57–66	5	4–8	0.18–0.25	−16	0	0.44	62.8
TCAS II’17

* Does not provide the whole bandwidth. $FoM=20log{\displaystyle \frac{f_o\left(GHz\right)·Gain\left(lin\right)·{BW}_{3dB}\left(GHz\right)·n\left(bits\right)}{RMS\_PE\left(deg\right)·RMS\_GE\left(dB\right)·CoreArea\left({mm}^2\right)}}$.