Networks-on-chip Again on the Rise: from Emerging Applications to Emerging Technologies

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: closed (31 March 2021) | Viewed by 26661

Special Issue Editors


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Guest Editor
Engineering Department, University of Ferrara, 44122 Ferrara, Italy
Interests: interconnection networks; embedded computing; emerging technologies; design automation

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Guest Editor
Computer Engineering and Technology Department, University of Murcia, 30100 Murcia, Spain
Interests: computer architecture; interconnection networks; memory hierarchy; domain-specific architecture; machine learning
Special Issues, Collections and Topics in MDPI journals

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Guest Editor
Electrical and Computer Engineering Department, Colorado State University, Fort Collins, CO 80523, USA
Interests: silicon photonics; high-performance computing systems; interconnection networks

Special Issue Information

Dear Colleagues,

Twenty years after the advent of interconnection networks to tackle the on-chip communication bottleneck, integrated computing platforms are again interconnect-dominated. On the one hand, the future of computing beyond Moore’s law and Dennard scaling is moving towards Systems-in-Package (SiP) based computing platforms that leverage advanced integration technologies such as 2.5D or 3D stacking. On the other hand, the advent and consolidation of data-intensive applications from artificial intelligence and big data analytics is putting unprecedented pressure on interconnection fabrics at each layer of the compute hierarchy, such as networks-on-chip (NoCs) and networks-in-package (NiPs).

This Special Issue seeks contributions on the latest advancements on chip- and package-scale interconnection systems, architectures, and/or circuits, capable of addressing the communication bottleneck raised by emerging data-intensive applications. The interest is in interconnect solutions for big data architectures across the computing continuum (from Edge computing to HPC) pursuing synergistic goals such as effective system integration (e.g., architectures for 2.5D or 3D-stacking) or architecture specialization (e.g., deep learning accelerators), and in any case striving to push performance boundaries under constant power budgets (e.g., approximate communication). At the same time, we welcome contributions on emerging technologies for on-chip and on-package networking (e.g., silicon nanophotonic networks, wireless NoCs, RF interconnects) with a focus ranging from disruptive devices to novel system concepts through architecture design methods. At the intersection of the above research directions, topics of interest include interconnect solutions for unconventional computing paradigms, such as  in-memory computing, neuromorphic computing or reconfigurable computing.

Prof. Dr. Davide Bertozzi
Prof. Dr. José L. Abellán
Prof. Dr. Mahdi Nikdast
Guest Editors

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Keywords

  • Communication bottleneck
  • Big data architectures
  • Deep learning hardware
  • Networks-on-chip
  • Networks-in-package
  • Communication fabric customization
  • Approximate communication
  • 2.5D and 3D integration
  • Emerging interconnect technologies
  • Communication in unconventional computing

Published Papers (9 papers)

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Editorial

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3 pages, 195 KiB  
Editorial
Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies
by Davide Bertozzi, José L. Abellán and Mahdi Nikdast
Micromachines 2021, 12(12), 1570; https://doi.org/10.3390/mi12121570 - 17 Dec 2021
Viewed by 1789
Abstract
Twenty years after the advent of interconnection networks to tackle the on-chip communication bottleneck [...] Full article

Research

Jump to: Editorial

10 pages, 2097 KiB  
Article
A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip
by Fen Ge, Chenchen Cui, Fang Zhou and Ning Wu
Micromachines 2021, 12(6), 613; https://doi.org/10.3390/mi12060613 - 26 May 2021
Cited by 4 | Viewed by 2367
Abstract
More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a [...] Read more.
More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications. Full article
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26 pages, 2798 KiB  
Article
A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities
by Jose Ricardo Gomez-Rodriguez, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila and Ramon Parra-Michel
Micromachines 2021, 12(2), 183; https://doi.org/10.3390/mi12020183 - 12 Feb 2021
Cited by 11 | Viewed by 4528
Abstract
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload [...] Read more.
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs. Full article
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14 pages, 547 KiB  
Article
Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip
by Yan-Li Zheng, Ting-Ting Song, Jun-Xiong Chai, Xiao-Ping Yang, Meng-Meng Yu, Yun-Chao Zhu, Yong Liu and Yi-Yuan Xie
Micromachines 2021, 12(1), 54; https://doi.org/10.3390/mi12010054 - 5 Jan 2021
Cited by 6 | Viewed by 2419
Abstract
The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network [...] Read more.
The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance. Full article
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12 pages, 1739 KiB  
Article
A Hardware Pseudo-Random Number Generator Using Stochastic Computing and Logistic Map
by Junxiu Liu, Zhewei Liang, Yuling Luo, Lvchen Cao, Shunsheng Zhang, Yanhu Wang and Su Yang
Micromachines 2021, 12(1), 31; https://doi.org/10.3390/mi12010031 - 30 Dec 2020
Cited by 11 | Viewed by 3369
Abstract
Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic [...] Read more.
Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic map is optimised by using the perturbation operation which effectively reduces the degradation of digital chaos. By employing stochastic computing, a hardware PRNG is designed with relatively low hardware utilisation. The proposed hardware PRNG is implemented by using a Field Programmable Gate Array device. Results show that the chaotic map achieves good security performance by using the perturbation operations and the generated pseudo-random numbers pass the TestU01 test and the NIST SP 800-22 test. Most importantly, it also saves 89% of hardware resources compared to conventional approaches. Full article
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27 pages, 31605 KiB  
Article
A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies
by Salvador Ibarra-Delgado, Remberto Sandoval-Arechiga, José Ricardo Gómez-Rodríguez, Manuel Ortíz-López and María Brox
Micromachines 2020, 11(12), 1063; https://doi.org/10.3390/mi11121063 - 30 Nov 2020
Cited by 3 | Viewed by 2398
Abstract
Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. [...] Read more.
Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed. Full article
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17 pages, 719 KiB  
Article
ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs
by Juan Fang, Di Zhang and Xiaqing Li
Micromachines 2020, 11(12), 1034; https://doi.org/10.3390/mi11121034 - 25 Nov 2020
Cited by 6 | Viewed by 2270
Abstract
Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness [...] Read more.
Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness routing algorithms to make routing decisions, thus degrading the performance of NoC. In this paper, we propose an efficient area partition-based congestion-aware routing algorithm, ParRouting, which aims at increasing the throughput and reducing the latency for NoC systems. First, ParRouting partitions the network into two areas (i.e., edge area and central area.) based on node priorities. Then, for the edge area, ParRouting selects the output node based on different priorities for higher throughput; for the central area, ParRouting selects the node in the low congestion direction as the output node for lower queuing latency. Our experimental results indicate that ParRouting achieves a 53.4% reduction in packet average latency over SPLASH -2 ocean application and improves the saturated throughput by up to 38.81% over a synthetic traffic pattern for an NoC system, compared to existing routing algorithms. Full article
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14 pages, 1257 KiB  
Article
A Novel Algorithm for Routing Paths Selection in Mesh-Based Optical Networks-on-Chips
by Xiao-Ping Yang, Ting-Ting Song, Yi-Chen Ye, Bo-Cheng Liu, Hua Yan, Yun-Chao Zhu, Yan-Li Zheng, Yong Liu and Yi-Yuan Xie
Micromachines 2020, 11(11), 996; https://doi.org/10.3390/mi11110996 - 9 Nov 2020
Cited by 5 | Viewed by 2867
Abstract
Optical networks-on-chips (ONoCs) is an effective and extensible on-chip communication technology, which has the characteristics of high bandwidth, low consumption, and low delay. In the design process of ONoCs, power loss is an important factor for limiting the scalability of ONoCs. Additionally, the [...] Read more.
Optical networks-on-chips (ONoCs) is an effective and extensible on-chip communication technology, which has the characteristics of high bandwidth, low consumption, and low delay. In the design process of ONoCs, power loss is an important factor for limiting the scalability of ONoCs. Additionally, the optical signal-to-noise ratio (OSNR) is an index to measure the quality of ONoCs. Nowadays, the routing algorithm commonly used in ONoCs is the dimension-order routing algorithm, but the routing paths selected by the algorithm have high power loss and crosstalk noise. In this paper, we propose a 5×5 all-pass optical router model for two-dimensional (2-D) mesh-based ONoCs. Based on the general optical router model and the calculation models of power loss and crosstalk noise, a novel algorithm is proposed in ordder to select the routing paths with the minimum power loss. At the same time, it can ensure that the routing paths have the approximately optimal OSNR. Finally, we employ the Cygnus optical router to verify the proposed routing algorithm. The results show that the algorithm can effectively reduce the power loss and improve the OSNR in the case of network sizes of 5×5 and 6×6. With the increase of the optical network scale, the algorithm can perform better in reducing the power loss and raising the OSNR. Full article
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21 pages, 5115 KiB  
Article
Crosstalk Analysis and Performance Evaluation for Torus-Based Optical Networks-on-Chip Using WDM
by Tingting Song, Yiyuan Xie, Yichen Ye, Shujian Wang and Yingxue Du
Micromachines 2020, 11(11), 985; https://doi.org/10.3390/mi11110985 - 31 Oct 2020
Cited by 1 | Viewed by 2643
Abstract
Insertion loss and crosstalk noise will influence network performance severely, especially in optical networks-on-chip (ONoCs) when wavelength division multiplexing (WDM) technology is employed. In this paper, an insertion loss and crosstalk analysis model for WDM-based torus ONoCs is proposed to evaluate the network [...] Read more.
Insertion loss and crosstalk noise will influence network performance severely, especially in optical networks-on-chip (ONoCs) when wavelength division multiplexing (WDM) technology is employed. In this paper, an insertion loss and crosstalk analysis model for WDM-based torus ONoCs is proposed to evaluate the network performance. To demonstrate the feasibility of the proposed methods, numerical simulations of the WDM-based torus ONoCs with optimized crossbar and crux optical routers are presented, and the worst-case link and network scalability are also revealed. The numerical simulation results demonstrate that the scale of the WDM-based torus ONoCs with the crux optical router can reach 6 × 5 or 5 × 6 before the noise power exceeds the signal power, and the network scale is 5 × 4 in the worst case when the optimized crossbar router is employed. Additionally, the simulated results of OptiSystem reveal that WDM-based torus ONoCs have better signal transmission quality when using the crux optical router, which is consistent with previous numerical simulations. Furthermore, compared with the single-wavelength network, WDM-based ONoCs have a great performance improvement in end-to-end (ETE) delay and throughput according to the simulated results of OPNET. The proposed network analysis method provides a reliable theoretical basis and technical support for the design and performance optimization of ONoCs. Full article
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