InGaAs-OI Substrate Fabrication on a 300 mm Wafer †
Abstract
:1. Introduction
2. InGaAs-OI Fabrication
3. Results and Discussion
3.1. Bonding Condition Optimization
3.2. Fracture in the InP Buffer Layer
4. Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
Abbreviations
MOSFET | metal oxide semiconductor field effect transistor |
InGaAs-OI | indium–gallium–arsenic on an insulator |
DWB | direct wafer bonding |
SEM | scanning electron microscopy |
SIMS | secondary ion mass spectrometry |
TEM | transition electron microscopy |
HR-XRD | high resolution X-ray diffraction |
SAM | scanning acoustic microscopy |
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Sollier, S.; Widiez, J.; Gaudin, G.; Mazen, F.; Baron, T.; Martin, M.; Roure, M.-C.; Besson, P.; Morales, C.; Beche, E.; et al. InGaAs-OI Substrate Fabrication on a 300 mm Wafer. J. Low Power Electron. Appl. 2016, 6, 19. https://doi.org/10.3390/jlpea6040019
Sollier S, Widiez J, Gaudin G, Mazen F, Baron T, Martin M, Roure M-C, Besson P, Morales C, Beche E, et al. InGaAs-OI Substrate Fabrication on a 300 mm Wafer. Journal of Low Power Electronics and Applications. 2016; 6(4):19. https://doi.org/10.3390/jlpea6040019
Chicago/Turabian StyleSollier, Sebastien, Julie Widiez, Gweltaz Gaudin, Frederic Mazen, Thierry Baron, Mickail Martin, Marie-Christine Roure, Pascal Besson, Christophe Morales, Elodie Beche, and et al. 2016. "InGaAs-OI Substrate Fabrication on a 300 mm Wafer" Journal of Low Power Electronics and Applications 6, no. 4: 19. https://doi.org/10.3390/jlpea6040019