InGaAs-OI Substrate Fabrication on a 300 mm Wafer †

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 ◦C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.


Introduction
In 0.53 Ga 0.47 As is one of the most promising III-V materials for a sub-10-nm technological node n-channel, with a theoretical mobility of 9500 cm 2 •V −1 •s −1 for an n-type Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) [1], around four times better than strained Si (2500 cm 2 •V −1 •s −1 ) [2].InGaAs epitaxial layers grown on a 300 mm Si substrate using a metamorphic layer has been reported in the literature [3].To take the most advantage of its good electrical properties, an ultrathin body III-V semi-conductor-on-insulator (III-V-OI) is needed to reduce the short channel effects [4].In our approach, the III-V layer buffer is used to grow the thin indium-gallium-arsenic (InGaAs) layer and to localize the H + implantation for the layer transfer.A thin InGaAs layer is then transferred after the direct wafer bonding onto an oxidized handle wafer.The bonding interface quality was optimized in this work to maintain a defect-free bonding interface up to 600 • C, which is the temperature target driven by the n-MOSFET devices fabrication.

InGaAs-OI Fabrication
Figure 1 shows the process flow to fabricate InGaAs-OI substrates using Smart Cut TM technology.A thin film (30 nm) is grown via metal organic chemical vapor deposition (MOCVD) on a 300-mm on-axis (100) Si substrate using an optimized InP/GaAs (250 nm/500 nm) metamorphic buffer to minimize the final surface roughness.An amorphous Al 2 O 3 layer is deposited by atomic layer deposition (ALD) at 300 • C using tri-methyl-aluminum (TMA) and H 2 O as precursors.A SiO 2 layer is then deposited on top of the Al 2 O 3 to optimize the direct bonding parameters.The films are annealed between 300 • C to 600 • C in nitrogen gas for 1 h to stabilize the layers.The future buried oxide (BOX) thickness and surface roughness are controlled by a chemical-mechanical polishing step (CMP).The H + implantation can be located in the metamorphic buffer (inside the InP layer in our case) or on the Si substrate.Then, the direct wafer bonding occurs on a thermally oxidized Si substrate.The splitting is performed via thermal annealing.The finishing step is done by chemical selective etching in the case of a splitting in the InP layer and CMP followed by chemical selective etching in the case of a splitting in the Si substrate.The final InGaAs thin film was characterized by AFM, HRXRD, and TEM.
(InGaAs) layer and to localize the H + implantation for the layer transfer.A thin InGaAs layer is then transferred after the direct wafer bonding onto an oxidized handle wafer.The bonding interface quality was optimized in this work to maintain a defect-free bonding interface up to 600 °C, which is the temperature target driven by the n-MOSFET devices fabrication.

InGaAs-OI Fabrication
Figure 1 shows the process flow to fabricate InGaAs-OI substrates using Smart Cut TM technology.A thin film (30 nm) is grown via metal organic chemical vapor deposition (MOCVD) on a 300-mm on-axis (100) Si substrate using an optimized InP/GaAs (250 nm/500 nm) metamorphic buffer to minimize the final surface roughness.An amorphous Al2O3 layer is deposited by atomic layer deposition (ALD) at 300 °C using tri-methyl-aluminum (TMA) and H2O as precursors.A SiO2 layer is then deposited on top of the Al2O3 to optimize the direct bonding parameters.The films are annealed between 300 °C to 600 °C in nitrogen gas for 1 h to stabilize the layers.The future buried oxide (BOX) thickness and surface roughness are controlled by a chemical-mechanical polishing step (CMP).The H + implantation can be located in the metamorphic buffer (inside the InP layer in our case) or on the Si substrate.Then, the direct wafer bonding occurs on a thermally oxidized Si substrate.The splitting is performed via thermal annealing.The finishing step is done by chemical selective etching in the case of a splitting in the InP layer and CMP followed by chemical selective etching in the case of a splitting in the Si substrate.The final InGaAs thin film was characterized by AFM, HRXRD, and TEM.

Results and Discussion
The III-V epitaxy growth process has been optimized to reduce the surface roughness values by a factor of two.This was possible thanks to an increase in the GaAs layer thickness.The obtained

Results and Discussion
The III-V epitaxy growth process has been optimized to reduce the surface roughness values by a factor of two.This was possible thanks to an increase in the GaAs layer thickness.The obtained values (RMS = 1.91 nm, PV = 16 nm) were low considering the large lattice mismatch between Si and InGaAs (about 8%) and our thin total buffer thickness (665 nm) [5][6][7].To achieve splitting in the InP layer, we increased the InP layer by up to 430 nm.The crystalline defects were localized in the GaAs layer, while low crystalline defects were observed in the thin InGaAs layer, as shown on TEM image in Figure 2. values (RMS = 1.91 nm, PV = 16 nm) were low considering the large lattice mismatch between Si and InGaAs (about 8%) and our thin total buffer thickness (665 nm) [5][6][7].To achieve splitting in the InP layer, we increased the InP layer by up to 430 nm.The crystalline defects were localized in the GaAs layer, while low crystalline defects were observed in the thin InGaAs layer, as shown on TEM image in Figure 2.This optimization allows us to substantially reduce the thickness of the dielectric capping layer, which is used to reduce the surface roughness by using a well-known CMP process on this material.The study of the direct bonding interface quality was done in terms of annealing temperatures [8].

Bonding Condition Optimization
The bonding interface quality of different bonding configurations (Al2O3//Al2O3, Al2O3//Si, Al2O3//SiO2, and Al2O3 under SiO2//SiO2) were studied as a function of post bonding annealing.Silicon substrates were used for this study, and SAM images of the results have been presented in previous articles [5][6][7].Al2O3 layers were pre-annealed at 600 °C in N2 ambient conditions and then cleaned in megasonic de-ionized water before bonding.SiO2 were prepared by polishing and hydrophilic cleaning.At room temperature (RT), no defects were observed after bonding for all stacks thanks to these efficient cleaning processes.All the bonding conditions present no defects up to 400 °C, except the Al2O3/Si bonding, which is already defective.At over 400 °C, only the last stack (with the SiO2//SiO2 bonding configuration) presented good performance in temperature without bonding defects up to 600 °C.This configuration avoids the diffusion of bonding interface water at the Al2O3//Si interfaces, which are known to be weak and easily defectives [8,9].This deposited SiO2 layer is essential in the bonding process for two reasons: it can be easily polished to allow the DWB, and it allows the best bonding condition, but a pre-annealing before bonding (at 600 °C) is necessary to avoid defect at 600 °C after bonding [5].
This oxide layer thickness is driven by the initial III-V stack roughness and the implantation process conditions.This optimal bonding condition was applied to the InGaAs-OI process.We obtained direct bonding with no defects at room temperature, and the Smart Cut TM technology was achieved either in the InP layer or on the Si substrate.

Fracture in the InP Buffer Layer
We investigated splitting conditions for the fracture to be located inside the epitaxial InP layer.For bulk InP, implantation temperature was identified as playing an important role [10]: some groups have reported that the temperature of an InP wafer during implantation should be kept below 0 °C [11,12], and others have claimed that heating the wafers during implantation is mandatory [12,13].This optimization allows us to substantially reduce the thickness of the dielectric capping layer, which is used to reduce the surface roughness by using a well-known CMP process on this material.The study of the direct bonding interface quality was done in terms of annealing temperatures [8].

Bonding Condition Optimization
The bonding interface quality of different bonding configurations (Al 2 O 3 //Al 2 O 3 , Al 2 O 3 //Si, Al 2 O 3 //SiO 2 , and Al 2 O 3 under SiO 2 //SiO 2 ) were studied as a function of post bonding annealing.Silicon substrates were used for this study, and SAM images of the results have been presented in previous articles [5][6][7].Al 2 O 3 layers were pre-annealed at 600 • C in N 2 ambient conditions and then cleaned in megasonic de-ionized water before bonding.SiO 2 were prepared by polishing and hydrophilic cleaning.At room temperature (RT), no defects were observed after bonding for all stacks thanks to these efficient cleaning processes.All the bonding conditions present no defects up to 400 • C, except the Al 2 O 3 /Si bonding, which is already defective.At over 400 • C, only the last stack (with the SiO 2 //SiO 2 bonding configuration) presented good performance in temperature without bonding defects up to 600 • C.This configuration avoids the diffusion of bonding interface water at the Al 2 O 3 //Si interfaces, which are known to be weak and easily defectives [8,9].This deposited SiO 2 layer is essential in the bonding process for two reasons: it can be easily polished to allow the DWB, and it allows the best bonding condition, but a pre-annealing before bonding (at 600 • C) is necessary to avoid defect at 600 • C after bonding [5].
This oxide layer thickness is driven by the initial III-V stack roughness and the implantation process conditions.This optimal bonding condition was applied to the InGaAs-OI process.We obtained direct bonding with no defects at room temperature, and the Smart Cut TM technology was achieved either in the InP layer or on the Si substrate.

Fracture in the InP Buffer Layer
We investigated splitting conditions for the fracture to be located inside the epitaxial InP layer.For bulk InP, implantation temperature was identified as playing an important role [10]: some groups have reported that the temperature of an InP wafer during implantation should be kept below 0 • C [11,12], and others have claimed that heating the wafers during implantation is mandatory [12,13].
We performed H + implantations in the InP epitaxial buffer layer at different temperatures using 300-mm Al 2 O 3 /InP/GaAs/Si wafers.In our case, we were able to obtain a fracture using "standard" temperature control during the implantation step, i.e., the wafers were maintained close to room temperature thanks to a backside gas cooling combined with water circulation in the chuck.The maximum of H + implantation concentration were localized in the middle of the InP layer.Micro-cracks were observed in the InP layer after annealing at 300 • C, as seen on the SEM cross-section image [6].These results indicate the layer transfer capability, which was confirmed during the InGaAs-OI fabrication.
A picture of the 300-mm InGaAs-OI substrate with thin film transfer is shown on Figure 3.No crystal defects were observed.HRXRD measurements were performed both after splitting and the InP chemical selective etch.The full width at half maximum, the rocking curve of the InGaAs transferred was approximately 0.38 • .Thus, the InGaAs layer remained crystalline during the overall process (2θ = 63.24• ).We performed H + implantations in the InP epitaxial buffer layer at different temperatures using 300-mm Al2O3/InP/GaAs/Si wafers.In our case, we were able to obtain a fracture using "standard" temperature control during the implantation step, i.e., the wafers were maintained close to room temperature thanks to a backside gas cooling combined with water circulation in the chuck.The maximum of H + implantation concentration were localized in the middle of the InP layer.Micro-cracks were observed in the InP layer after annealing at 300 °C, as seen on the SEM cross-section image [6].These results indicate the layer transfer capability, which was confirmed during the InGaAs-OI fabrication.
A picture of the 300-mm InGaAs-OI substrate with thin film transfer is shown on Figure 3.No crystal defects were observed.HRXRD measurements were performed both after splitting and the InP chemical selective etch.The full width at half maximum, the rocking curve of the InGaAs transferred was approximately 0.38°.Thus, the InGaAs layer remained crystalline during the overall process (2θ = 63.24°).

Conclusions
We here demonstrated 300 mm InGaAs-OI substrates with Smart Cut TM technology.The transfer of a 30 nm-thick In0.53Ga0.47Aslayer grown on a 300 mm Si substrate by MOCVD shows good quality with a low defect density.Bonding interface quality was optimized in this work to maintain a defect-free bonding interface up to 600°C.Moreover, the process conditions were found to induce splitting in the InP epitaxial layer.

Figure 1 .
Figure 1.The fabrication process flow of the InGaAs-OI substrates using Smart Cut TM technology inside the InP buffer layer.

Figure 1 .
Figure 1.The fabrication process flow of the InGaAs-OI substrates using Smart Cut TM technology inside the InP buffer layer.

Figure 3 .
Figure 3. Picture of a 300 mm InGaAs-OI substrate after transfer using Smart Cut TM technology.