Feasibility-Aware Design-Space Exploration of Transparent Coarse-Grained Reconfigurable Architectures

Coarse-Grained Reconfigurable Architectures (CGRAs) execute compute-intensive kernels on a reconfigurable processing mesh. Transparent CGRAs extend this model by generating configurations at runtime and storing them in a dedicated cache, removing compiler dependence and enabling adaptive behavior. Although prior work has explored mapping strategies and mesh scaling, the feasibility of the configuration cache remains unaddressed, as it is commonly treated as a generic storage block. This paper presents a feasibility study of configuration cache organizations and a design-space exploration of Transparent CGRAs, introducing a parameterized cache geometry model that relates cache parameters to the processing mesh and configuration structure. The model enables realistic estimates of area, latency, and energy at the digital system level and is applied to three Transparent CGRAs from the literature and five additional designs covering a wide range of spatial and temporal organizations. The results show that mesh scaling must be balanced with cache feasibility: wide I/O paths and large configurations lead to impractical caches, whereas well-proportioned meshes achieve competitive performance with modest overheads. Under the proposed exploration, selected expanded meshes outperform a two-issue out-of-order processor by up to 1.4× while increasing area by only 14.8% and energy by 2%. These findings demonstrate that Transparent CGRAs are viable, but their scalability depends on a realistic configuration cache design. The proposed parameterized cache model provides a structured and reproducible basis for analyzing transparency overheads and guiding future CGRA designs.