High-Performance Computer Architecture

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 May 2026 | Viewed by 120

Special Issue Editors


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Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: compiler technologies for performance, energy efficiency, and security
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Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: embedded systems; compiler technology; software–hardware co-design

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Guest Editor
Department of Computer Science, Norwegian University of Science and Technology, 7034 Trondheim, Norway
Interests: compilers; approximate computing

Special Issue Information

Dear Colleagues,

Computing architectures are experiencing a surge in interest, driven by the need to achieve high performance at a reduced energy cost, as highlighted by the "power wall" experienced in supercomputer design and by the need to maximize performance at the edge.

AI and other emerging technologies have led to a range of tailored architectural solutions, exploiting specific characteristics of an application class to increase performance and reduce energy consumption.

At the edge, the need for high performance meets other more stringent requirements such as real-time constraints. To address these issues, a range of tools are needed at the architectural, electronic design automation, and system software levels to enable the customization, co-design, and co-optimization of applications and architectures.

This Special Issue aims to collect manuscripts presenting solutions and tools for improving performance in a range of different application classes, in the context of both supercomputers and high-performance embedded systems.

Dr. Giovanni Agosta
Dr. Daniele Cattaneo
Dr. Stefano Cherubin
Guest Editors

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Keywords

  • high-performance computing architectures
  • co-design
  • co-optimization
  • RISC-V
  • high performance embedded systems
  • optimizing compilers
  • energy efficiency

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Published Papers (1 paper)

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Research

20 pages, 421 KiB  
Article
RISC-V Address-Encoded Byte Order Extension
by David Guerrero, Jorge Juan-Chico, German Cano-Quiveu, Paulino Ruiz-de-Clavijo, Julian Viejo and Enrique Ostua
Electronics 2025, 14(16), 3257; https://doi.org/10.3390/electronics14163257 (registering DOI) - 16 Aug 2025
Abstract
In some cases, computer systems need to handle both little-endian and big-endian data, even if it differs from their native endianness. This paper proposes an RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data. It can [...] Read more.
In some cases, computer systems need to handle both little-endian and big-endian data, even if it differs from their native endianness. This paper proposes an RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data. It can be implemented with little engineering effort and a negligible impact on performance and hardware resources. Our results demonstrate that the extension can reduce the overhead of foreign-endian data processing by 62% or 37% compared to software-based solutions that use the base Instruction Set Architecture (ISA) or current bit manipulation extensions, respectively. This performance boost has the potential to benefit both new and legacy software once compiler and library support have been put in place. Full article
(This article belongs to the Special Issue High-Performance Computer Architecture)
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