Special Issue "Advanced Technologies in Intelligent Computer System Architecture"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 30 June 2022.

Special Issue Editors

Prof. Dr. Giovanni Agosta
E-Mail Website
Guest Editor
Politecnico di Milano, Milan, Italy
Interests: compiler technologies for performance, energy efficiency, and security
Prof. Dr. Carlo Brandolese
E-Mail Website
Guest Editor
DEIB, Politecnico di Milano, Milan, Italy
Interests: embedded systems design; low-power computing systems
Dr. Stefano Cherubin
E-Mail Website
Guest Editor
School of Computing, Edinburgh Napier University, Edinburgh, UK
Interests: approximate computing; compiler technology for mixed precision

Special Issue Information

Dear Colleagues,

Intelligent computer systems are increasingly gaining traction thanks to the improvements in the underlying machine intelligence theory and applications. This is also driving intelligence into embedded devices, which are expected to implement complex decision logics, with or without the support of remote networked servers, and possibly coordinate information from multiple sources to achieve a correct understanding of the environment they are operating in.

These scenarios pose numerous challenges in terms of performance, battery life, reliability, and security, which must be addressed through appropriate architectural solutions, including hardware accelerators for specific tasks, as well as through software-level optimizations, including compiler transformations and software design methodologies. The combination and co-design of software and hardware become particularly important when resources are constrained, and holistic techniques need to be adopted.

This Special Issue aims at collecting advances in the field, including a mix of application-specific and methodological contributions. The topics of interest include, but are not limited to, the following:

  • Hardware architectures and accelerators for intelligent embedded and cyberphysical systems;
  • Compiler-based techniques for enforcing extrafunctional properties;
  • Approximate computing and mixed-precision techniques;
  • Low-power embedded systems architectures for AI and machine learning applications;
  • Embedded systems compiler/runtime frameworks to support AI and machine learning applications;
  • Programmability of self-driving cars and other safety-critical intelligent computer systems;
  • Models and learning discretization for low-end microcontrollers;
  • Performance/memory tradeoffs and optimizations in intelligent computer systems;
  • Hardware/software co-design and platform-based design of intelligent computer systems.

Prof. Dr. Giovanni Agosta
Prof. Dr. Carlo Brandolese
Dr. Stefano Cherubin
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Intelligent systems architecture
  • Embedded systems design
  • Cyberphysical systems
  • Approximate computing
  • Energy efficiency
  • Compiler optimization
  • Ubiquitous computing systems

Published Papers (2 papers)

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Research

Article
Runtime Adaptive IoMT Node on Multi-Core Processor Platform
by , , and
Electronics 2021, 10(21), 2572; https://doi.org/10.3390/electronics10212572 (registering DOI) - 21 Oct 2021
Abstract
The Internet of Medical Things (IoMT) paradigm is becoming mainstream in multiple clinical trials and healthcare procedures. Thanks to innovative technologies, latest-generation communication networks, and state-of-the-art portable devices, IoTM opens up new scenarios for data collection and continuous patient monitoring. Two very important [...] Read more.
The Internet of Medical Things (IoMT) paradigm is becoming mainstream in multiple clinical trials and healthcare procedures. Thanks to innovative technologies, latest-generation communication networks, and state-of-the-art portable devices, IoTM opens up new scenarios for data collection and continuous patient monitoring. Two very important aspects should be considered to make the most of this paradigm. For the first aspect, moving the processing task from the cloud to the edge leads to several advantages, such as responsiveness, portability, scalability, and reliability of the sensor node. For the second aspect, in order to increase the accuracy of the system, state-of-the-art cognitive algorithms based on artificial intelligence and deep learning must be integrated. Sensory nodes often need to be battery powered and need to remain active for a long time without a different power source. Therefore, one of the challenges to be addressed during the design and development of IoMT devices concerns energy optimization. Our work proposes an implementation of cognitive data analysis based on deep learning techniques on resource-constrained computing platform. To handle power efficiency, we introduced a component called Adaptive runtime Manager (ADAM). This component takes care of reconfiguring the hardware and software of the device dynamically during the execution, in order to better adapt it to the workload and the required operating mode. To test the high computational load on a multi-core system, the Orlando prototype board by STMicroelectronics, cognitive analysis of Electrocardiogram (ECG) traces have been adopted, considering single-channel and six-channel simultaneous cases. Experimental results show that by managing the sensory node configuration at runtime, energy savings of at least 15% can be achieved. Full article
(This article belongs to the Special Issue Advanced Technologies in Intelligent Computer System Architecture)
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Article
An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance
Electronics 2021, 10(11), 1328; https://doi.org/10.3390/electronics10111328 - 01 Jun 2021
Viewed by 589
Abstract
Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache [...] Read more.
Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs. Full article
(This article belongs to the Special Issue Advanced Technologies in Intelligent Computer System Architecture)
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