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Electronics
Volume 14
Issue 16
10.3390/electronics14163257
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This is an early access version, the complete PDF, HTML, and XML versions will be available soon.
Article

RISC-V Address-Encoded Byte Order Extension

by
David Guerrero
*,
Jorge Juan-Chico
,
German Cano-Quiveu
,
Paulino Ruiz-de-Clavijo
,
Julian Viejo
and
Enrique Ostua
Departamento de Tecnología Electrónica, Universidad de Sevilla, 41012 Sevilla, Spain
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(16), 3257; https://doi.org/10.3390/electronics14163257 (registering DOI)
Submission received: 16 July 2025 / Revised: 11 August 2025 / Accepted: 14 August 2025 / Published: 16 August 2025
(This article belongs to the Special Issue High-Performance Computer Architecture)
Versions Notes

Abstract

In some cases, computer systems need to handle both little-endian and big-endian data, even if it differs from their native endianness. This paper proposes an RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data. It can be implemented with little engineering effort and a negligible impact on performance and hardware resources. Our results demonstrate that the extension can reduce the overhead of foreign-endian data processing by 62% or 37% compared to software-based solutions that use the base Instruction Set Architecture (ISA) or current bit manipulation extensions, respectively. This performance boost has the potential to benefit both new and legacy software once compiler and library support have been put in place.
Keywords: RISC-V; ISA; alignment; byte order; endianness; MPSoC RISC-V; ISA; alignment; byte order; endianness; MPSoC

Share and Cite

MDPI and ACS Style

Guerrero, D.; Juan-Chico, J.; Cano-Quiveu, G.; Ruiz-de-Clavijo, P.; Viejo, J.; Ostua, E. RISC-V Address-Encoded Byte Order Extension. Electronics 2025, 14, 3257. https://doi.org/10.3390/electronics14163257

AMA Style

Guerrero D, Juan-Chico J, Cano-Quiveu G, Ruiz-de-Clavijo P, Viejo J, Ostua E. RISC-V Address-Encoded Byte Order Extension. Electronics. 2025; 14(16):3257. https://doi.org/10.3390/electronics14163257

Chicago/Turabian Style

Guerrero, David, Jorge Juan-Chico, German Cano-Quiveu, Paulino Ruiz-de-Clavijo, Julian Viejo, and Enrique Ostua. 2025. "RISC-V Address-Encoded Byte Order Extension" Electronics 14, no. 16: 3257. https://doi.org/10.3390/electronics14163257

APA Style

Guerrero, D., Juan-Chico, J., Cano-Quiveu, G., Ruiz-de-Clavijo, P., Viejo, J., & Ostua, E. (2025). RISC-V Address-Encoded Byte Order Extension. Electronics, 14(16), 3257. https://doi.org/10.3390/electronics14163257

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