Special Issue "Design and Implementation of Efficient Future Memory Systems"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 31 July 2021.

Special Issue Editor

Prof. Dr. Tae-Sun Chung
Website
Guest Editor
Department of Computer Engineering, Ajou University, Suwon 16499, Korea
Interests: flash memory storages; embedded systems; database systems; data mining

Special Issue Information

Dear Colleagues,

Recently, as new memory technologies, including flash memory, phase change memory (PCM), magnetoresistive random-access memory (MRAM), spin-torque transfer memory (STTRAM), resistive RAM (ReRAM), and so on have appeared, the system software for supporting the new memory technologies has become more important. Particularly, the new memory technologies create many challenging issues in designing new algorithms or architectures for supporting high-performance systems. Particularly, new design methodologies and architectures may be targeted to specific applications, including machine learning, AR (Augmented Reality), and so on.

In this Special Issue, original research articles as well as review articles that deal with system software and design architectures for new memory technologies are invited. The system software includes each module in operating systems, files systems, or database systems, and design architectures include new hardware design for future memory techniques.

Potential topics include but are not limited to: 

  • Advanced operating systems for future memory technologies;
  • Advanced file systems for future memory technologies;
  • Advanced database systems for future memory technologies;
  • New hardware design for target applications including machine learning, AR, and so on;
  • Fault-tolerance for future memory technologies;
  • Performance analysis for future memory technologies.

Prof. Dr. Tae-Sun Chung
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Flash memory
  • Embedded system
  • Future memory
  • File system
  • Machine learning/AR

Published Papers (4 papers)

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Research

Open AccessArticle
Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System
Electronics 2020, 9(12), 2158; https://doi.org/10.3390/electronics9122158 - 16 Dec 2020
Abstract
This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory [...] Read more.
This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement. Full article
(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)
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Open AccessArticle
FTRM: A Cache-Based Fault Tolerant Recovery Mechanism for Multi-Channel Flash Devices
Electronics 2020, 9(10), 1581; https://doi.org/10.3390/electronics9101581 - 27 Sep 2020
Abstract
Flash memory prevalence has reached greater extents with its performance and compactness capabilities. This enables it to be easily adopted as storage media in various portable devices which includes smart watches, cell-phones, drones, and in-vehicle infotainment systems to mention but a few. To [...] Read more.
Flash memory prevalence has reached greater extents with its performance and compactness capabilities. This enables it to be easily adopted as storage media in various portable devices which includes smart watches, cell-phones, drones, and in-vehicle infotainment systems to mention but a few. To support large flash storage in such portable devices, existing flash translation layers (FTLs) employ a cache mapping table (CMT), which contains a small portion of logical page number to physical page number (LPN-PPN) mappings. For robustness, it is of importance to consider the CMT reconstruction mechanisms during system recovery. Currently, existing approaches cannot overcome the performance penalty after experiencing unexpected power failure. This is due to the disregard of the delay caused by inconsistencies between the cached page-mapping entries in RAM and their corresponding mapping pages in flash storage. Furthermore, how to select proper pages for reconstructing the CMT when rebooting a device needs to be revisited. In this study we address these problems and propose a fault tolerant power-failure recovery mechanism (FTRM) for flash memory storage systems. Our empirical study shows that FTRM is an efficient recovery and robust protocol. Full article
(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)
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Open AccessArticle
File Type and Access Pattern Aware Buffer Cache Management for Rendering Systems
Electronics 2020, 9(1), 164; https://doi.org/10.3390/electronics9010164 - 15 Jan 2020
Cited by 1
Abstract
Rendering is the process of generating high-resolution images by software, which is widely used in animation, video games and visual effects in movies. Although rendering is a computation-intensive job, we observe that storage accesses may become another performance bottleneck in desktop-rendering systems. In [...] Read more.
Rendering is the process of generating high-resolution images by software, which is widely used in animation, video games and visual effects in movies. Although rendering is a computation-intensive job, we observe that storage accesses may become another performance bottleneck in desktop-rendering systems. In this article, we present a new buffer cache management scheme specialized for rendering systems. Unlike general-purpose computing systems, rendering systems exhibit specific file access patterns, and we show that this results in significant performance degradation in the buffer cache system. To cope with this situation, we collect various file input/output (I/O) traces of rendering workloads and analyze their access patterns. The results of this analysis show that file I/Os in rendering processes consist of long loops for configuration, short loops for texture input, random reads for input, and single-writes for output. Based on this observation, we propose a new buffer cache management scheme for improving the storage performance of rendering systems. Experimental results show that the proposed scheme improves the storage I/O performance by an average of 19% and a maximum of 55% compared to the conventional buffer cache system. Full article
(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)
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Open AccessFeature PaperArticle
DSFTL: An Efficient FTL for Flash Memory Based Storage Systems
Electronics 2020, 9(1), 145; https://doi.org/10.3390/electronics9010145 - 12 Jan 2020
Cited by 1
Abstract
Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), [...] Read more.
Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead. Full article
(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)
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