Submit to Electronics Review for Electronics Propose a Special Issue

Journal Browser

Design and Implementation of Efficient Future Memory Systems

Print Special Issue Flyer
Special Issue Editors
Special Issue Information
Keywords
Published Papers

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 July 2021) | Viewed by 31698

Share This Special Issue

Special Issue Editor

Prof. Dr. Tae-Sun Chung

E-Mail Website
Guest Editor

Department of Software, Ajou University, Suwon 16499, Republic of Korea
Interests: database systems; data mining; machine learning; VR/AR system; flash memory storage; embedded systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Recently, as new memory technologies, including flash memory, phase change memory (PCM), magnetoresistive random-access memory (MRAM), spin-torque transfer memory (STTRAM), resistive RAM (ReRAM), and so on have appeared, the system software for supporting the new memory technologies has become more important. Particularly, the new memory technologies create many challenging issues in designing new algorithms or architectures for supporting high-performance systems. Particularly, new design methodologies and architectures may be targeted to specific applications, including machine learning, AR (Augmented Reality), and so on.

In this Special Issue, original research articles as well as review articles that deal with system software and design architectures for new memory technologies are invited. The system software includes each module in operating systems, files systems, or database systems, and design architectures include new hardware design for future memory techniques.

Potential topics include but are not limited to:

Advanced operating systems for future memory technologies;
Advanced file systems for future memory technologies;
Advanced database systems for future memory technologies;
New hardware design for target applications including machine learning, AR, and so on;
Fault-tolerance for future memory technologies;
Performance analysis for future memory technologies.

Prof. Dr. Tae-Sun Chung
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

Flash memory
Embedded system
Future memory
File system
Machine learning/AR

Published Papers (11 papers)

Download All Papers

Research

12 pages, 3465 KiB

Open AccessArticle

Direct-Virtio: A New Direct Virtualized I/O Framework for NVMe SSDs

by Sewoog Kim, Heekwon Park and Jongmoo Choi

Electronics 2021, 10(17), 2058; https://doi.org/10.3390/electronics10172058 - 26 Aug 2021

Cited by 2 | Viewed by 3885

Abstract

Virtualization is a core technology for cloud computing, server consolidation and multi-platform support. However, there is a concern regarding performance degradation due to the duplicated I/O stacks virtualization environments. In this paper, we propose a new I/O framework, we refer to it as Direct-Virtio, that manipulates storage directly, which makes it feasible to avoid the duplicated overhead. In addition, we devise two novel mechanisms, called vectored I/O and adaptive polling, to process multiple I/O requests collectively and to check I/O completion efficiently. Real implementation-based evaluation shows that our proposal can enhance performance for both micro and macro benchmarks. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

17 pages, 6023 KiB

Open AccessArticle

A Novel Low Power Method of Combining Saliency and Segmentation for Mobile Displays

by Simon Suh, Seok Min Hong, Young-Jin Kim and Jong Sung Park

Electronics 2021, 10(10), 1200; https://doi.org/10.3390/electronics10101200 - 18 May 2021

Cited by 1 | Viewed by 1502

Abstract

Saliency, which means the area human vision is concentrated, can be used in many applications, such as enemy detection in solider goggles and person detection in an auto-driving car. In recent years, saliency is obtained instead of human eyes using a model in an automated way in HMD (Head Mounted Display), smartphones, and VR (Virtual Reality) devices based on mobile displays; however, such a mobile device needs too much power to maintain saliency on a mobile display. Therefore, low power saliency methods have been important. CURA tried to power down, according to the saliency level, while keeping human visual satisfaction. But it still has some artifacts due to the difference in brightness at the boundary of the region divided by saliency. In this paper, we propose a new segmentation-based saliency-aware low power approach to minimize the artifacts. Unlike CURA, our work considers visual perceptuality and power management at the saliency level and at the segmented region level for each saliency. Through experiments, our work achieves low power in each region divided by saliency and in the segmented regions in each saliency region, while maintaining human visual satisfaction for saliency. In addition, it maintains good image distortion quality while removing artifacts efficiently. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

19 pages, 2303 KiB

Open AccessArticle

Phase-Based Accurate Power Modeling for Mobile Application Processors

by Kitak Lee, Seung-Ryeol Ohk, Seong-Geun Lim and Young-Jin Kim

Electronics 2021, 10(10), 1197; https://doi.org/10.3390/electronics10101197 - 17 May 2021

Cited by 2 | Viewed by 1909

Abstract

Modern mobile application processors are required to execute heavier workloads while the battery capacity is rarely increased. This trend leads to the need for a power model that can analyze the power consumed by CPU and GPU at run-time, which are the key components of the application processor in terms of power savings. We propose novel CPU and GPU power models based on the phases using performance monitoring counters for smartphones. Our phase-based power models employ combined per-phase power modeling methods to achieve more accurate power consumption estimations, unlike existing power models. The proposed CPU power model shows estimation errors of 2.51% for ARM Cortex A-53 and 1.97% for Samsung M1 on average, and the proposed GPU power model shows an average error of 8.92% for the Mali-T880. In addition, we integrate proposed CPU and GPU models with the latest display power model into a holistic power model. Our holistic power model can estimate the smartphone′s total power consumption with an error of 6.36% on average while running nine 3D game benchmarks, improving the error rate by about 56% compared with the latest prior model. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

18 pages, 6072 KiB

Open AccessArticle

Presence Effects in Virtual Reality Based on User Characteristics: Attention, Enjoyment, and Memory

by Si Jung Kim, Teemu H. Laine and Hae Jung Suk

Electronics 2021, 10(9), 1051; https://doi.org/10.3390/electronics10091051 - 29 Apr 2021

Cited by 12 | Viewed by 3311

Abstract

Presence refers to the emotional state of users where their motivation for thinking and acting arises based on the perception of the entities in a virtual world. The immersion level of users can vary when they interact with different media content, which may result in different levels of presence especially in a virtual reality (VR) environment. This study investigates how user characteristics, such as gender, immersion level, and emotional valence on VR, are related to the three elements of presence effects (attention, enjoyment, and memory). A VR story was created and used as an immersive stimulus in an experiment, which was presented through a head-mounted display (HMD) equipped with an eye tracker that collected the participants’ eye gaze data during the experiment. A total of 53 university students (26 females, 27 males), with an age range from 20 to 29 years old (mean 23.8), participated in the experiment. A set of pre- and post-questionnaires were used as a subjective measure to support the evidence of relationships among the presence effects and user characteristics. The results showed that user characteristics, such as gender, immersion level, and emotional valence, affected their level of presence, however, there is no evidence that attention is associated with enjoyment or memory. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

14 pages, 41640 KiB

Open AccessArticle

An Efficient Stereo Matching Network Using Sequential Feature Fusion

by Jaecheol Jeong, Suyeon Jeon and Yong Seok Heo

Electronics 2021, 10(9), 1045; https://doi.org/10.3390/electronics10091045 - 28 Apr 2021

Cited by 2 | Viewed by 1936

Abstract

Recent stereo matching networks adopt 4D cost volumes and 3D convolutions for processing those volumes. Although these methods show good performance in terms of accuracy, they have an inherent disadvantage in that they require great deal of computing resources and memory. These requirements limit their applications for mobile environments, which are subject to inherent computing hardware constraints. Both accuracy and consumption of computing resources are important, and improving both at the same time is a non-trivial task. To deal with this problem, we propose a simple yet efficient network, called Sequential Feature Fusion Network (SFFNet) which sequentially generates and processes the cost volume using only 2D convolutions. The main building block of our network is a Sequential Feature Fusion (SFF) module which generates 3D cost volumes to cover a part of the disparity range by shifting and concatenating the target features, and processes the cost volume using 2D convolutions. A series of the SFF modules in our SFFNet are designed to gradually cover the full disparity range. Our method prevents heavy computations and allows for efficient generation of an accurate final disparity map. Various experiments show that our method has an advantage in terms of accuracy versus efficiency compared to other networks. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

13 pages, 3021 KiB

Open AccessArticle

Human Perceptuality-Aware Tone-Mapping-Based Dynamic Voltage Scaling for an AMOLED Display Smartphone

by Simon Suh, Seok Min Hong, Young-Jin Kim and Jong Sung Park

Electronics 2021, 10(9), 1015; https://doi.org/10.3390/electronics10091015 - 24 Apr 2021

Cited by 1 | Viewed by 1689

Abstract

In recent years, people have wanted to watch high dynamic range imagery which can give high human visual satisfaction on smartphones and demand longer smartphone battery time. However, compression of dynamic range using tone-mapping operators is required in smartphones because most smartphone displays currently have a low dynamic range, and this causes loss of local contrast and details to compress dynamic range. Thus, in this paper we propose a novel dynamic voltage scaling scheme tightly coupled with a modified tone-mapping operator to achieve high power saving as well as good human perceptuality on an AMOLED display smartphone. In order to perform a human perceptuality-aware voltage control, we control display panel voltage to save power consumption and use a well-adjusted global tone-mapping operator to convert image brightness and unsharp masking to enhance local contrast and details and control. We implement the proposed scheme on the AMOLED display Android smartphone and experiment with various high dynamic range image databases. Experimental results show that not only tone-mapped images but also general images are improved in terms of human visual satisfaction and power saving, compared to conventional techniques. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

20 pages, 3533 KiB

Open AccessFeature PaperArticle

A Crash Recovery Scheme for a Hybrid Mapping FTL in NAND Flash Storage Devices

by Jong-Hyeok Park, Dong-Joo Park, Tae-Sun Chung and Sang-Won Lee

Electronics 2021, 10(3), 327; https://doi.org/10.3390/electronics10030327 - 01 Feb 2021

Cited by 5 | Viewed by 2907

Abstract

An FTL (flash translation layer), which most flash storage devices are equipped with, needs to guarantee the consistency of modified metadata from a sudden power failure. This crash recovery scheme significantly affects the writing performance of a flash storage device during its normal operation, as well as its reliability and recovery performance; therefore, it is desirable to make the crash recovery scheme efficient. Despite the practical importance of a crash recovery scheme in an FTL, few works exist that deal with the crash recovery issue in FTL in a comprehensive manner. This study proposed a novel crash recovery scheme called FastCheck for a hybrid mapping FTL called Fully Associative Sector Translation (FAST). FastCheck can efficiently secure the newly generated address-mapping information using periodic checkpoints, and at the same time, leverages the characteristics of an FAST FTL, where the log blocks in a log area are used in a round-robin way. Thus, it provides two major advantages over the existing FTL recovery schemes: one is having a low logging overhead during normal operations in the FTL and the other to have a fast recovery time in an environment where the log provisioning rate is relatively high, e.g., over 20%, and the flash memory capacity is very large, e.g., 32 GB or 64 GB. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

15 pages, 3956 KiB

Open AccessArticle

Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

by Jeong-Geun Kim, Shin-Dug Kim and Su-Kyung Yoon

Electronics 2020, 9(12), 2158; https://doi.org/10.3390/electronics9122158 - 16 Dec 2020

Cited by 2 | Viewed by 2946

Abstract

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

15 pages, 877 KiB

Open AccessArticle

FTRM: A Cache-Based Fault Tolerant Recovery Mechanism for Multi-Channel Flash Devices

by Ronnie Mativenga, Prince Hamandawana, Tae-Sun Chung and Jongik Kim

Electronics 2020, 9(10), 1581; https://doi.org/10.3390/electronics9101581 - 27 Sep 2020

Cited by 6 | Viewed by 2770

Abstract

Flash memory prevalence has reached greater extents with its performance and compactness capabilities. This enables it to be easily adopted as storage media in various portable devices which includes smart watches, cell-phones, drones, and in-vehicle infotainment systems to mention but a few. To support large flash storage in such portable devices, existing flash translation layers (FTLs) employ a cache mapping table (CMT), which contains a small portion of logical page number to physical page number (LPN-PPN) mappings. For robustness, it is of importance to consider the CMT reconstruction mechanisms during system recovery. Currently, existing approaches cannot overcome the performance penalty after experiencing unexpected power failure. This is due to the disregard of the delay caused by inconsistencies between the cached page-mapping entries in RAM and their corresponding mapping pages in flash storage. Furthermore, how to select proper pages for reconstructing the CMT when rebooting a device needs to be revisited. In this study we address these problems and propose a fault tolerant power-failure recovery mechanism (FTRM) for flash memory storage systems. Our empirical study shows that FTRM is an efficient recovery and robust protocol. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

13 pages, 2428 KiB

Open AccessArticle

File Type and Access Pattern Aware Buffer Cache Management for Rendering Systems

by Donghee Shin, Kyungwoon Cho and Hyokyung Bahn

Electronics 2020, 9(1), 164; https://doi.org/10.3390/electronics9010164 - 15 Jan 2020

Cited by 6 | Viewed by 2787

Abstract

Rendering is the process of generating high-resolution images by software, which is widely used in animation, video games and visual effects in movies. Although rendering is a computation-intensive job, we observe that storage accesses may become another performance bottleneck in desktop-rendering systems. In this article, we present a new buffer cache management scheme specialized for rendering systems. Unlike general-purpose computing systems, rendering systems exhibit specific file access patterns, and we show that this results in significant performance degradation in the buffer cache system. To cope with this situation, we collect various file input/output (I/O) traces of rendering workloads and analyze their access patterns. The results of this analysis show that file I/Os in rendering processes consist of long loops for configuration, short loops for texture input, random reads for input, and single-writes for output. Based on this observation, we propose a new buffer cache management scheme for improving the storage performance of rendering systems. Experimental results show that the proposed scheme improves the storage I/O performance by an average of 19% and a maximum of 55% compared to the conventional buffer cache system. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

19 pages, 3372 KiB

Open AccessFeature PaperArticle

DSFTL: An Efficient FTL for Flash Memory Based Storage Systems

by Suk-Joo Chae, Ronnie Mativenga, Joon-Young Paik, Muhammad Attique and Tae-Sun Chung

Electronics 2020, 9(1), 145; https://doi.org/10.3390/electronics9010145 - 12 Jan 2020

Cited by 9 | Viewed by 5080

Abstract

Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead. Full article

(This article belongs to the Special Issue Design and Implementation of Efficient Future Memory Systems)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Design and Implementation of Efficient Future Memory Systems

Share This Special Issue

Special Issue Editor

Special Issue Information

Keywords

Published Papers (11 papers)

Research

Further Information

Guidelines

MDPI Initiatives

Follow MDPI