Recent Advances in Microelectronics Devices and Integrated Circuit

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 January 2023) | Viewed by 12068

Special Issue Editors

Engineering Product Development (EPD), Singapore University of Technology and Design, Singapore 487372, Singapore
Interests: low-power and low-voltage design for sensor interface; mixed-signal wireless; AI integrated circuit
Special Issues, Collections and Topics in MDPI journals
Digital Architecture Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tokyo, Japan
Interests: low-power embedded systems; on-chip interconnect; reliable SoC
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Computationally intelligent devices are becoming the mainstream due to the emerging technology around Artificial Intelligence, which is particularly deep-learning-driven. AI is everywhere now and accelerating all the technologies in microelectronics and related integrated circuits, such as direct memory, processing units, display/motor drivers, sensor interfaces, parallel computing, etc. Cryptography is also triggering the fast growth of quantum computing devices and circuits. Advanced microelectronics and integrated circuits have enabled the long-awaited practical implementation of Artificial Intelligence in a reasonable computation speed.

Accordingly, this Special Issue seeks to showcase research papers and review articles that focus on novel methodological developments in the field of advanced microelectronics and the design of related integrated circuits. Work that explores how technologies can be incorporated with AI methods to identify novel design directions and improve devices, circuits, system performance, as well as processes is sought after. Additionally, research which identifies and evaluates the limitations of applying AI to certain problems and specific domains, in advanced microelectronics and integrated circuits, is also welcome.

This Special Issue is primarily meant to serve as a collection of extended versions of selected papers presented at the IEEE 15th International Symposium on Embedded Multicore/Manycore Systems-on-Chip (MCSoC-2022) https://www.mcsoc-forum.org/. Selected papers from MCSoC 2022 and all external contributions in this field are welcome in this Special Issue.

Dr. Teo Tee Hui
Dr. Akram Ben Ahmed
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • artificial intelligence
  • deep learning
  • integrated circuits
  • microelectronics
  • quantum computing

Published Papers (5 papers)

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Research

16 pages, 859 KiB  
Article
A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction
Electronics 2023, 12(6), 1439; https://doi.org/10.3390/electronics12061439 - 17 Mar 2023
Viewed by 1046
Abstract
This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock [...] Read more.
This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication. Full article
(This article belongs to the Special Issue Recent Advances in Microelectronics Devices and Integrated Circuit)
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17 pages, 5022 KiB  
Article
Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s
Electronics 2023, 12(4), 908; https://doi.org/10.3390/electronics12040908 - 10 Feb 2023
Cited by 1 | Viewed by 1198
Abstract
This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, [...] Read more.
This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently. Full article
(This article belongs to the Special Issue Recent Advances in Microelectronics Devices and Integrated Circuit)
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14 pages, 3215 KiB  
Article
Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter
by , and
Electronics 2023, 12(4), 810; https://doi.org/10.3390/electronics12040810 - 06 Feb 2023
Cited by 3 | Viewed by 1203
Abstract
The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use [...] Read more.
The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%. Full article
(This article belongs to the Special Issue Recent Advances in Microelectronics Devices and Integrated Circuit)
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10 pages, 6288 KiB  
Article
Design and Implementation of Sigma-Delta ADC Filter
Electronics 2022, 11(24), 4229; https://doi.org/10.3390/electronics11244229 - 19 Dec 2022
Cited by 3 | Viewed by 4070
Abstract
This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) [...] Read more.
This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively reduces about 13% multiplier cells and memory cells. The coefficient symmetry technique and CSD (Canonic Signed Digit) coding technique are used to optimize the parameters of the filter, which further reduces the computational complexity. After optimization, the circuit area is reduced by about 15%, and the logic resources are decreased by about 23%. The Verilog hardware description language is used to describe the behavior of the digital decimation filter, and the simulation is carried out based on the VCS (Verilog Compile Simulator) platform. At the same time, the prototype verification is implemented on the Xilinx Artix-7 series FPGA, and the ADC achieves 113 dB SNR and 18.5 bits ENOB. Finally, the Sigma-Delta ADC is fabricated on SMIC 0.18 μm CMOS process with the layout area of 714.8 μm × 628.4 μm and the power consumption of 11.2 mW. The more tests for the fabricated prototypes will be performed in the future to verify that the Sigma-Delta ADC complies with the design specifications. Full article
(This article belongs to the Special Issue Recent Advances in Microelectronics Devices and Integrated Circuit)
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14 pages, 2327 KiB  
Article
Implementation of Binarized Neural Networks in All-Programmable System-on-Chip Platforms
Electronics 2022, 11(4), 663; https://doi.org/10.3390/electronics11040663 - 21 Feb 2022
Cited by 4 | Viewed by 2800
Abstract
The Binarized Neural Network (BNN) is a Convolutional Neural Network (CNN) consisting of binary weights and activation rather than real-value weights. Smaller models are used, allowing for inference effectively on mobile or embedded devices with limited power and computing capabilities. Nevertheless, binarization results [...] Read more.
The Binarized Neural Network (BNN) is a Convolutional Neural Network (CNN) consisting of binary weights and activation rather than real-value weights. Smaller models are used, allowing for inference effectively on mobile or embedded devices with limited power and computing capabilities. Nevertheless, binarization results in lower-entropy feature maps and gradient vanishing, which leads to a loss in accuracy compared to real-value networks. Previous research has addressed these issues with various approaches. However, those approaches significantly increase the algorithm’s time and space complexity, which puts a heavy burden on those embedded devices. Therefore, a novel approach for BNN implementation on embedded systems with multi-scale BNN topology is proposed in this paper, from two optimization perspectives: hardware structure and BNN topology, that retains more low-level features throughout the feed-forward process with few operations. Experiments on the CIFAR-10 dataset indicate that the proposed method outperforms a number of current BNN designs in terms of efficiency and accuracy. Additionally, the proposed BNN was implemented on the All Programmable System on Chip (APSoC) with 4.4 W power consumption using the hardware accelerator. Full article
(This article belongs to the Special Issue Recent Advances in Microelectronics Devices and Integrated Circuit)
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