A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

: The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a ﬂipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 µ m CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 µ A with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV,


Introduction
Power management integrated circuits (PMICs) are playing an increasingly important role in system-on-a-chip (SOC). The function of electronic products is related to PMICs. High-performance PMICs with high stability, fast dynamic response and high efficiency have become more important. With the advantages of simple structure, low quiescent current, wide bandwidth and noise suppression ability [1][2][3][4][5], LDOs are widely used in wearable intelligence devices, memory, etc. [6][7][8][9][10].
Due to the existence of a large off-chip capacitor in traditional LDOs [11][12][13][14][15][16][17][18], the stability of the traditional LDO is not guaranteed. The dominant pole of the traditional LDO is at the output node, so the dominant pole of the traditional LDO will change under different load conditions. With an increase in load, the dominant pole moves to a low frequency, which causes instability of the LDO system. The traditional LDO regulator with a large output capacitor has the disadvantages of high design complexity, large chip area and high cost [1,19], and this will limit the fully integrated ability of modern SOCs. However, in fully integrated LDOs, the transient and stability will degrade significantly due to the absence of the off-chip capacitor, thus becoming major design challenges.
Many methods have emerged to tackle these issues. For example, in [12,18], a slewrate enhancement circuit and dynamic transient control circuit were used to improve the transient response, but the impedance of the output still changed with the load, so a large Miller capacitor was used to ensure stability at low load. The FVF structure [20][21][22][23] gives another way of compensation, and it can make the output pole independent of the loading. Figure 1a shows the FVF circuit. M P is the power transistor, and V SET is the input voltage.
Because of the small impedance of the FVF structure [24], the output pole is independent of the load and moves to a high frequency. The output impedance can be expressed as In Equation (1), g m1 is the transconductance of M 1 . Equation (1) indicates that R OUT is related to g m1 and much smaller than the load resistance; therefore, the output pole does not vary with the load, and the stability problem is solved.
In Figure 1a, the FVF structure decreases the output resistance [25,26] and moves the non-dominant pole, which is constituted by output resistance and output capacitance, into a high frequency, but the stability issues still need to be considered if the two poles are close enough. However, the low loop gain of the FVF structure affects the response time, line regulation and load regulation in the stable output state [8,27,28]. The FVF structure can be replaced by a folded FVF structure [25,[29][30][31][32], as illustrated in Figure 1b. With the addition of cascade transistor M 2 in the feedback loop, the loop gain of the folded FVF is improved.
In Equation (1), gm1 is the transconductance of M1. Equation (1) indicates that ROUT is related to gm1 and much smaller than the load resistance; therefore, the output pole does not vary with the load, and the stability problem is solved.
In Figure 1a, the FVF structure decreases the output resistance [25,26] and moves the non-dominant pole, which is constituted by output resistance and output capacitance, into a high frequency, but the stability issues still need to be considered if the two poles are close enough. However, the low loop gain of the FVF structure affects the response time, line regulation and load regulation in the stable output state [8,27,28]. The FVF structure can be replaced by a folded FVF structure [25,[29][30][31][32], as illustrated in Figure 1b. With the addition of cascade transistor M2 in the feedback loop, the loop gain of the folded FVF is improved. However, fast transient response is an important requirement in the OCL-LDO because there is no external output capacitor to decrease the output variations when the transient occurs. In Figure 1b, Ibias1 and Ibias2 determine the transient response, and a large bias current will consume more power. The authors of [29] presented a voltage spike detection circuit based on capacitive coupling. This circuit realized bias current change in load changes, but the capacitor consumed a greater area. The authors of [33] proposed a novel positive transient detection circuit to improve the transient response, but the better effect was achieved only with heavy to light load changes. This paper proposes a dynamic bias generation circuit for fast charging/discharging of the large gate-source parasitic capacitance of the power transistor MP by using an MOS to detect changes in the output. Fast transient response is achieved by dynamically adjusting the bias currents Ibias1 and Ibias2 when the load changes.
This article is organized as follows. Section 2 elaborates on the structure and principle of the proposed dynamic bias circuit. In Section 3, the implementation of the LDO circuit is described. Simulation results are presented in Section 4. Finally, Section 5 concludes the paper.

Proposed Dynamic Bias Circuit
The concept of the proposed dynamic bias circuit is illustrated in Figure 2. The circuit consists of five MOS transistors, MD1-5, and two constant bias currents, Ibias and I2. VREF is a constant voltage. The function of MD2 is to detect the change in voltage VOUT directly. I1 is influenced by the change in VOUT and then affects I3 because I3 = I2 + I1. In the steady state, However, fast transient response is an important requirement in the OCL-LDO because there is no external output capacitor to decrease the output variations when the transient occurs. In Figure 1b, I bias1 and I bias2 determine the transient response, and a large bias current will consume more power. The authors of [29] presented a voltage spike detection circuit based on capacitive coupling. This circuit realized bias current change in load changes, but the capacitor consumed a greater area. The authors of [33] proposed a novel positive transient detection circuit to improve the transient response, but the better effect was achieved only with heavy to light load changes. This paper proposes a dynamic bias generation circuit for fast charging/discharging of the large gate-source parasitic capacitance of the power transistor M P by using an MOS to detect changes in the output. Fast transient response is achieved by dynamically adjusting the bias currents I bias1 and I bias2 when the load changes.
This article is organized as follows. Section 2 elaborates on the structure and principle of the proposed dynamic bias circuit. In Section 3, the implementation of the LDO circuit is described. Simulation results are presented in Section 4. Finally, Section 5 concludes the paper.

Proposed Dynamic Bias Circuit
The concept of the proposed dynamic bias circuit is illustrated in Figure 2. The circuit consists of five MOS transistors, M D1-5 , and two constant bias currents, I bias and I 2 . V REF is a constant voltage. The function of M D2 is to detect the change in voltage V OUT directly. I 1 is influenced by the change in V OUT and then affects I 3 because I 3 = I 2 + I 1 . In the steady Electronics 2022, 11, 3009 3 of 13 state, V OUT remains constant, and V GS1 is constant to give a fixed current I 1 . The current I 1 can be expressed as In Equation (2), V GS2 is the gate-source voltage of M D2 in the steady state. The gate and source voltages of M D2 remain unchanged; consequently, I 3 is a stationary current in steady state. ctronics 2022, 11, x FOR PEER REVIEW VOUT remains constant, and VGS1 is constant to give a fixed current I1. The curr expressed as In Equation (2), VGS2 is the gate-source voltage of MD2 in the steady state. T source voltages of MD2 remain unchanged; consequently, I3 is a stationary curr state. In the steady state, VOUT equals VREF. However, when VOUT increases insta the variation is ΔV. The source of MD2 detects the change, then |VGS2| increa tarily to increase I1. I1 can be found from The extract current ΔI1 is given by (4) shows that large W/L and ΔV are conducive to increasing injects more transient current into I3. When VOUT returns to a constant voltage in a steady state once again, then I1 returns to the stable value.
Similarly, when VOUT decreases, |VGS2| decreases, then I1 is reduced, and fected. Figure 3 illustrates the variation in I1 and I2 when VOUT changes. I1 chan In the steady state, V OUT equals V REF . However, when V OUT increases instantaneously, the variation is ∆V. The source of M D2 detects the change, then |V GS2 | increases momentarily to increase I 1 . I 1 can be found from The extract current ∆I 1 is given by Equation (4) shows that large W/L and ∆V are conducive to increasing I 1 ; thus, M D2 injects more transient current into I3. When V OUT returns to a constant voltage level, V GS2 is in a steady state once again, then I 1 returns to the stable value.
Similarly, when V OUT decreases, |V GS2 | decreases, then I 1 is reduced, and I 3 is also affected. Figure 3 illustrates the variation in I 1 and I 2 when V OUT changes. I 1 changes with the variation in V OUT , and I 3 changes as well.

Circuit Design
The proposed LDO circuit structure implementation presented in this paper is shown in Figure 4. The proposed LDO is formed by a folded FVF circuit, the proposed dynamic bias circuit, an amplifier, and a power transistor, MP. To ensure the performance of the circuit, the folded FVF was adopted to improve the circuit gain. MC1-MC2 and two bias currents I1-I2 make up the folded FVF circuit. VSET as the input of the folded FVF is generated by the amplifier. VB is a constant voltage. Figure 5 shows the dynamic bias circuit. MOS transistors MD1-MD14 comprise the dynamic bias circuit. VB1 and VB2 are constant voltages. The sources of MD1 and MD4 are connected to VOUT to achieve direct detection of the voltage spike created at the transient instant. MD3 and MD6 were developed to generate new dynamic bias voltages VBN and VBP; they are dynamic bias currents I1 and I2 in the folded FVF circuit.

Circuit Design
The proposed LDO circuit structure implementation presented in this paper is shown in Figure 4.

Circuit Design
The proposed LDO circuit structure implementation presented in this paper is show in Figure 4. The proposed LDO is formed by a folded FVF circuit, the proposed dynamic b circuit, an amplifier, and a power transistor, MP. To ensure the performance of the circu the folded FVF was adopted to improve the circuit gain. MC1-MC2 and two bias curren I1-I2 make up the folded FVF circuit. VSET as the input of the folded FVF is generated the amplifier. VB is a constant voltage. Figure 5 shows the dynamic bias circuit. MOS transistors MD1-MD14 comprise the d namic bias circuit. VB1 and VB2 are constant voltages. The sources of MD1 and MD4 are co nected to VOUT to achieve direct detection of the voltage spike created at the transient stant. MD3 and MD6 were developed to generate new dynamic bias voltages VBN and V they are dynamic bias currents I1 and I2 in the folded FVF circuit. The proposed LDO is formed by a folded FVF circuit, the proposed dynamic bias circuit, an amplifier, and a power transistor, M P . To ensure the performance of the circuit, the folded FVF was adopted to improve the circuit gain. M C1 -M C2 and two bias currents I 1 -I 2 make up the folded FVF circuit. V SET as the input of the folded FVF is generated by the amplifier. V B is a constant voltage. In the dynamic bias circuit, the drop (or increase) in VOUT is detected by the so MD1 and subsequently decreases (or increases) the gate voltage of MP through th path formed by MD3 and I1. Similarly, MD4 also senses the drop (or increase) in increase (or decrease) the gate voltage of MD6 and finally decrease (or increase) voltage of MP via the signal path formed by I2 and MC2.
The constant current sources generated by MD2 and MD5 are added to the circu avoids excessively high or low VOUT resulting in extremely low currents generated and MD4.
When ILOAD suddenly increases, VOUT drops rapidly. The signal response is sh Figure 6. In Figure 6, the capacitor C is the parasitic capacitor of the gate and so MP. The direction of the arrow in the capacitor represents discharge or charge cu  In the dynamic bias circuit, the drop (or increase) in V OUT is detected by the source of MD1 and subsequently decreases (or increases) the gate voltage of M P through the signal path formed by M D3 and I 1 . Similarly, M D4 also senses the drop (or increase) in V OUT to increase (or decrease) the gate voltage of M D6 and finally decrease (or increase) the gate voltage of M P via the signal path formed by I 2 and M C2 .
The constant current sources generated by M D2 and M D5 are added to the circuit. This avoids excessively high or low V OUT resulting in extremely low currents generated by M D1 and M D4 .
When I LOAD suddenly increases, V OUT drops rapidly. The signal response is shown in Figure 6. In Figure 6, the capacitor C is the parasitic capacitor of the gate and source of MP. The direction of the arrow in the capacitor represents discharge or charge current. In the dynamic bias circuit, the drop (or increase) in VOUT is detected by the source of MD1 and subsequently decreases (or increases) the gate voltage of MP through the signal path formed by MD3 and I1. Similarly, MD4 also senses the drop (or increase) in VOUT to increase (or decrease) the gate voltage of MD6 and finally decrease (or increase) the gate voltage of MP via the signal path formed by I2 and MC2.
The constant current sources generated by MD2 and MD5 are added to the circuit. This avoids excessively high or low VOUT resulting in extremely low currents generated by MD1 and MD4.
When ILOAD suddenly increases, VOUT drops rapidly. The signal response is shown in Figure 6. In Figure 6, the capacitor C is the parasitic capacitor of the gate and source of MP. The direction of the arrow in the capacitor represents discharge or charge current.  I  I  I  I  I  = +Δ In Equation (5), IMC1 and IMD1 are the steady-state currents of MC1 and MD1. ΔIMC1 and ΔIMD1 are the variations. We know from Equation (5) that IMC2 increases. The capacitor C then discharges. The discharge current of C is  In Equation (5), I MC1 and I MD1 are the steady-state currents of M C1 and M D1 . ∆I MC1 and ∆I MD1 are the variations. We know from Equation (5) that I MC2 increases. The capacitor C then discharges. The discharge current of C is I MD4 is the current of M D4 in the steady state, and ∆I MD4 is the variation. Accelerated discharge of C, decreased gate voltage of M P , and increased output current are achieved due to M C1 , M B1− and M B2 . When V OUT is regulated back to the nominal value, the bias condition of the circuit returns to normal.
Similarly, when I LOAD decreases suddenly, V OUT increases. The signal response is shown in Figure 7.
IMD4 is the current of MD4 in the steady state, and ΔIMD4 is the variation. Accelerated discharge of C, decreased gate voltage of MP, and increased output current are achieved due to MC1, MB1 and MB2. When VOUT is regulated back to the nominal value, the bias condition of the circuit returns to normal.
Similarly, when ILOAD decreases suddenly, VOUT increases. The signal response is shown in Figure 7.
We know from Equation (7) that IMC2 decreases. The capacitor C is then charged. The charging current of C is  I  I  I  I  I  I  I C is charged up to reduce the current provided by MP to the load. The operation is automatically shut down again when VOUT returns to the steady state.
The small-signal model of the proposed folded FVF LDO is shown in Figure 8.
We know from Equation (7) that I M C2 decreases. The capacitor C is then charged. The charging current of C is C is charged up to reduce the current provided by M P to the load. The operation is automatically shut down again when V OUT returns to the steady state.
The small-signal model of the proposed folded FVF LDO is shown in Figure 8.
IMD4 is the current of MD4 in the steady state, and ΔIMD4 is the variation. Accelerated discharge of C, decreased gate voltage of MP, and increased output current are achieved due to MC1, MB1 and MB2. When VOUT is regulated back to the nominal value, the bias condition of the circuit returns to normal.
Similarly, when ILOAD decreases suddenly, VOUT increases. The signal response is shown in Figure 7. We know from Equation (7) that IMC2 decreases. The capacitor C is then charged. The charging current of C is  I  I  I  I  I  I  I C is charged up to reduce the current provided by MP to the load. The operation is automatically shut down again when VOUT returns to the steady state.
The small-signal model of the proposed folded FVF LDO is shown in Figure 8. R B and C B are the equivalent resistance and capacitance at node B. The resistance and capacitance are R B = r oMB2 || g mc2 · r oMC2 · r oMB1 (9) In Equations (9) and (10), gM C2 and gmp are the transconductances of M C2 and M P ; r oMB1 , r oMB2 and r oMC2 are the drain output resistances of M B1 , M B2 and M C2 ; and C GSP is the gate source capacitance of M P .
The resistance and capacitance of the output node are ||r op ||R load (11) In Equations (11) and (12), gM C1 , g mD1 and g mD4 are the transconductances of M C1 , M D1 and M D4 ; r op is the drain output resistor of M P ; CGSM C1 , C GSMD1 and C GSMD4 are the gate source capacitance of M C1 , M D1 and M D4 ; and C para is the parasitic capacitance in output node. The large R B and C B determine the position of the dominant pole.
Generally, R load is larger than 1/g m ; then, the output resistance is related to 1/g m , and this means that the R OUT has little correlation with R load . The dominant pole is at node B, and the non-dominant pole at the output node is almost unchanged when the load changes, so the circuit is stable.

Simulation Results
The proposed LDO circuit was designed using 0.18 µm standard CMOS technology. The supply voltage was 1.8 V. The simulation results are presented here. Figure 9 shows the frequency response of the proposed LDO at different I LOAD values (I LOAD = 0.1 mA and I LOAD = 20 mA). It can be seen that the phase margins are more than 85 in all conditions. This circuit is stable.
In Equations (9) and (10), gmc2 and gmp are the transconductances of MC2 and MP; roMB1, roMB2 and roMC2 are the drain output resistances of MB1, MB2 and MC2; and CGSP is the gate source capacitance of MP.
The resistance and capacitance of the output node are In Equations (11) and (12), gmc1, gmD1 and gmD4 are the transconductances of MC1, MD1 and MD4; rop is the drain output resistor of MP; CGSMC1, CGSMD1 and CGSMD4 are the gate source capacitance of MC1, MD1 and MD4; and Cpara is the parasitic capacitance in output node. The large RB and CB determine the position of the dominant pole.
Generally, Rload is larger than 1/gm; then, the output resistance is related to 1/gm, and this means that the ROUT has little correlation with Rload. The dominant pole is at node B, and the non-dominant pole at the output node is almost unchanged when the load changes, so the circuit is stable.

Simulation Results
The proposed LDO circuit was designed using 0.18 μm standard CMOS technology. The supply voltage was 1.8 V. The simulation results are presented here. Figure 9 shows the frequency response of the proposed LDO at different ILOAD values (ILOAD = 0.1 mA and ILOAD = 20 mA). It can be seen that the phase margins are more than 85 in all conditions. This circuit is stable.    In Figure 11, the transient response simulation results of the LDO without and with the proposed dynamic bias circuit are shown. The load current changes from 0.1 mA to 20 mA with a rise/fall time of 1 ps.    During load transition, the change in dynamic bias current caus quiescent current to change; however, in the steady state, the quiescent current is con Therefore, the quiescent of LDO is stable at zero load and full load.  Tsettle is the recovery time when VOUT settles back to 1% accuracy [33]. As shown in Figure 11, the undershoot, overshoot and recovery time of the LDO without the proposed dynamic bias circuit were about 248 mV, 260 mV and 177 ns, respectively, while those of the LDO with the proposed circuit were about 242 mV, 250 mV and 52 ns only, respectively. The transient benefitted from the dynamic bias current and large bias current. Figure 12 shows the simulated recovery time versus process corners and temperature variations. As can be seen, across all process corners at −40 °C, 27 °C and 85 °C, the max recovery time was 59 ns at 85 °C in the SS corner, while the min recovery time was 45 ns at −40 °C in the FF corner. Figure 13 and Figure 14 present the simulated overshoot and undershoot against process corners and temperature variations (−40 °C, 27 °C and 85 °C). The max overshoot was 283 mV at 85 °C in the SS corner, while the min overshoot was 217 mV at −40 °C in the FS corner. The max undershoot was 280 mV at 85 °C in the SS corner, and the min undershoot T settle is the recovery time when V OUT settles back to 1% accuracy [33]. As shown in Figure 11, the undershoot, overshoot and recovery time of the LDO without the proposed dynamic bias circuit were about 248 mV, 260 mV and 177 ns, respectively, while those of the LDO with the proposed circuit were about 242 mV, 250 mV and 52 ns only, respectively. The transient benefitted from the dynamic bias current and large bias current. Figure 12 shows the simulated recovery time versus process corners and temperature variations. As can be seen, across all process corners at −40 • C, 27 • C and 85 • C, the max recovery time was 59 ns at 85 • C in the SS corner, while the min recovery time was 45 ns at −40 • C in the FF corner.   For the layout of the design, we used a 0.18 μm standard CMOS process. Figu    For the layout of the design, we used a 0.18 μm standard CMOS process. Figure 15 shows the layout of this design, with an active area of approximately 0.0235 mm 2 (156.8 μm × 149.8 μm).    For the layout of the design, we used a 0.18 μm standard CMOS process. Figure 15 shows the layout of this design, with an active area of approximately 0.0235 mm 2 (156.8 μm × 149.8 μm). For the layout of the design, we used a 0.18 µm standard CMOS process. Figure 15 shows the layout of this design, with an active area of approximately 0.0235 mm 2 (156.8 µm × 149.8 µm).
Electronics 2022, 11, x FOR PEER REVIEW Figure 15. Layout of the proposed LDO. Table 1 summarizes the performance of the proposed LDO circuit and com with the prior state of the art in terms of quiescent current, on-chip capacitor, r time spike voltage, load regulation (LDR), line regulation (LNR) and power-supp tion ratio (PSRR). Compared with the prior designs in Table 1, this paper achie shortest response time. In Table 1, FOM1 is defined as in [26,34]; it can be expressed as In Equation (13), K is the edge-time ratio, which is defined by used in the measurement t K Δ = Figure 15. Layout of the proposed LDO. Table 1 summarizes the performance of the proposed LDO circuit and compares it with the prior state of the art in terms of quiescent current, on-chip capacitor, recovery time spike voltage, load regulation (LDR), line regulation (LNR) and power-supply rejection ratio (PSRR). Compared with the prior designs in Table 1, this paper achieves the shortest response time. In Table 1, FOM1 is defined as in [26,34]; it can be expressed as In Equation (13), K is the edge-time ratio, which is defined by K = ∆t used in the measurement the smallest ∆t among the designs for comparison (14) In Equation (14), ∆t is the edge time taken for the change in the output current.  [35] can be expressed as

Conclusions
This paper proposed a new dynamic bias technique applied in FVF OCL-LDO circuits. The output current of the power MOS is changed quickly due to the discharge/charge current of the gate of the power MOS increasing during the load current transition; thus, the output voltage returns to the steady state quickly. It achieves a fast transient response by only changing the bias currents during load transition, without increasing the quiescent current.
The proposed LDO was realized by a 0.18 µm CMOS process. The result shows that V OUT recovered to 1% in 52 ns when the load current changed from 0.1 mA to 20 mA, or back, with an edge time of 1 ps. The quiescent current was 92 µA under light and heavy load. The total on-chip capacitance was 2.8 pF, and the undershoot and overshoot were 242 mV and 250 mV, respectively. The proposed LDO is satisfactory for digital circuits and fully integrated body sensor chips.