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Chips, Volume 1, Issue 1 (June 2022) – 6 articles

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Article
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Chips 2022, 1(1), 54-71; https://doi.org/10.3390/chips1010006 - 13 Jun 2022
Viewed by 365
Abstract
Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in [...] Read more.
Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits. Full article
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Editorial
Chips: A New Open Access Journal in the Domain of ICs
Chips 2022, 1(1), 51-53; https://doi.org/10.3390/chips1010005 - 30 May 2022
Viewed by 424
Abstract
As Editor-in-Chief, it is my honor and pleasure to introduce Chips [...] Full article
Article
Multiphase Interpolating Digital Power Amplifiers for TX Beamforming
Chips 2022, 1(1), 30-50; https://doi.org/10.3390/chips1010004 - 26 May 2022
Viewed by 442
Abstract
This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for [...] Read more.
This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for low-frequency beamforming and MIMO, as it does not require passive or LO-based phase shifters. The SCPA is ideal for use as the core element since it can perform frequency translation and data conversion, and drive an output at high power and efficiency in a compact die area. A prototype four-element beamforming TX, occupying 2mm×2.5mm, can achieve a peak output power of 24.4 dBm with a peak system efficiency (SE) of 24%, while achieving <1 phase resolution and <1 dB gain error. When transmitting a 15 MHz, 64-QAM long-term evolution (LTE) signal it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) of <30 dBc and an error vector magnitude (EVM) of 3.27% RMS at 1.75 GHz. A synthesized beam pattern based on measured results from a single die achieves <0.32 RMS beam angle error and <0.1 dB RMS beam amplitude error. Full article
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Article
System on Chip Noise Integrity Simulation
Chips 2022, 1(1), 14-29; https://doi.org/10.3390/chips1010003 - 28 Apr 2022
Viewed by 478
Abstract
In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis [...] Read more.
In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured. Full article
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Article
Memory Optimisation on AVR Microcontrollers for IoT Devices’ Minimalistic Displays
Chips 2022, 1(1), 2-13; https://doi.org/10.3390/chips1010002 - 21 Apr 2022
Viewed by 362
Abstract
The minimalistic hardware of most Internet of things (IoT) devices and sensors, especially those based on microcontrollers (MCU), imposes severe limitations on the memory capacity and interfacing capabilities of the device. Nevertheless, many applications prescribe not only textual but also graphical display features [...] Read more.
The minimalistic hardware of most Internet of things (IoT) devices and sensors, especially those based on microcontrollers (MCU), imposes severe limitations on the memory capacity and interfacing capabilities of the device. Nevertheless, many applications prescribe not only textual but also graphical display features as output interface. Due to the aforementioned limitations, the storage of graphical data is however highly problematic and existing solutions have even resorted to requiring external storage (e.g., a microSD card) for that purpose. In this paper, we present, evaluate and discuss two solutions that enable loading fullscreen, optimal 18-bit colour image data directly from the MCU, that is, without having to rely on additional hardware. Importantly, these solutions retain a very low footprint to suit the microcontroller architecture; the AVR architecture has been selected given its popularity. The obtained results show the feasibility and practicability of the proposal: in the worst case, 21 Kbytes of memory are required, in other words approximately 33% of the flash memory of a 32-Kbyte MCU remain available. Full article
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Editorial
Publisher’s Note: Chips—A New Open Access Journal on Integrated Circuit
Chips 2022, 1(1), 1; https://doi.org/10.3390/chips1010001 - 24 Aug 2021
Viewed by 1659
Abstract
A chip is a set of electronic circuits on one small flat piece (or “chip”) of semiconductor material [...] Full article
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