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Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits^{ †}

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## Abstract

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## 1. Introduction

**Contribution:**In this article, we significantly extend the methods and applicability of our novel equivalence checking methodology from [19], which is, to the best of our knowledge, the first of its kind. Essentially, our approach operates directly on the system-level and SPICE-level models by combining the linear graph modeling technique with several graph operations to transform these complex models into a canonical representation. It is therefore a static method and not simulation-based. The canonical representation is used to overcome the main challenge, which is to show that the SPICE-level model is equivalent to the behavioral system-level model implemented in SystemC AMS. We leverage Signal-Flow Graphs (SFG) as an intermediate representation between the SPICE-level and the system-level model, which the canonical representation also relies on. In particular, the developed method extends the applicability of the method in [19] to the class of complex single-input single-output (SISO) linear analog circuits with passive and active components. Many analog circuits fall into the linear category, such as various classic electronic circuits and many analog filters. Some examples of supported circuits are analog High-Pass Filters (HPF), averager circuits, amplifiers operated in their linear region, linear computation circuits, etc., and their combinations. Additionally, the method is extended to handle more complex behavioral models with respect to the simple LTF models used in [19]. We demonstrate the applicability of the developed methodology by successfully applying it to complex linear analog circuits.

- A novel equivalence checking methodology for SPICE-level models and behavioral system-level models that go beyond single LTFs.
- Leverage SFGs, canonical representations, and linear graph modeling techniques.
- Extension of applicability to the complete class of complex SISO linear analog circuits.
- Demonstration of equivalence checking on complex filter models, Small-Signal Models (SSM), series connections, and linear analog computers.

## 2. Related Work

## 3. Preliminaries

#### 3.1. Signal-Flow Graphs

#### 3.2. Simplification Operations for Signal-Flow Graphs

- Removal of a non-input node

- Parallel edge unification

- Reflexive edge elimination

#### 3.3. SystemC and SystemC AMS

#### 3.4. Motivating Example: Series-Connected HPF and SSM of Common-Source (CS) Amplifier

`hpcs`given in Figure 9. The declarations of the modules are at lines 5 and 6, and they are connected with the signal V_R_M at lines 10 and 11.

## 4. Signal-Flow Driven Equivalence Checking Methodology

#### 4.1. Methodology Overview

#### 4.2. Creating the Signal-Flow Graph from System-Level Descriptions

#### 4.3. Creating the Signal-Flow Graph from SPICE-Level Descriptions

- Voltages of components on the normal tree, from elemental equations.
- Currents of components on the normal tree, from continuity equations.
- Voltages of components on the tree links, from compatibility equations.
- Currents of components on the tree links, from elemental equations.

#### 4.4. Reducing the Signal-Flow Graph

#### 4.5. Illustration

## 5. Experimental Evaluation

#### 5.1. Experimental Setup

#### 5.2. Equivalence Checking

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

SoC | System-on-chip |

SFG | Signal-flow graph |

LPF | Low-pass filter |

HPF | High-pass filter |

DUV | Design under verification |

VP | Virtual prototyping |

ESL | Electronic system level |

TDF | Timed data flow |

LSF | Linear signal flow |

ELN | Electrical linear networks |

MoC | Model of computation |

LTF | Laplace transfer function |

RF | Radio frequency |

SSM | Small-signal model |

CS | Common source |

AMS | Analog/mixed-signal |

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**Figure 1.**The Signal-Flow Graph (SFG) corresponding to Equation (3).

**Figure 2.**The SFG corresponding to Equation (3) (

**a**) after removal of node ${x}_{1}$, (

**b**) after parallel edge unification, and (

**c**) after removal of the reflexive edge at node ${x}_{2}$.

**Figure 4.**System-level behavioral model of the example in Figure 3 implemented in SystemC AMS with (

**a**) example.h and (

**b**) example.cpp.

**Figure 5.**Motivating example: Series-connected High-Pass Filter (HPF) and small-signal model (SSM) of common-source (CS) amplifier with components Resistor (R), Capacitor (C), Inductor (L), and Voltage-Dependent Current Source (G1).

**Figure 6.**System-level block diagram of the series connection of an HPF and the SSM model of a CS amplifier.

**Figure 7.**System-level behavioral model of the HPF implemented in SystemC AMS with (

**a**) hpf.h and (

**b**) hpf.cpp.

**Figure 8.**System-level behavioral model of the CS amplifier’s SSM implemented in SystemC AMS with (

**a**) cs.h and (

**b**) cs.cpp.

**Figure 9.**System-level series connection of the HPF and the CS amplifier’s SSM implemented in SystemC AMS.

**Figure 12.**Graph of the series-connected HPF and CS amplifier circuit. The normal tree is emphasized with bold edges.

**Figure 14.**Some results from the simplification process: (

**a**) The SFG after eight simplification steps. (

**b**) The SFG after parallel edges in the previous SFG are merged. (

**c**) The SFG after removal of ${V}_{{L}_{1}}$. (

**d**) The SFG after removal of ${I}_{{C}_{L}}$. (

**e**) The SFG after the reflexive edge in the previous SFG is removed.

**Figure 16.**(

**a**) Initial SFG and (

**b**) reduced SFG of the system-level model of the HPF and CS amplifier circuit.

**Figure 17.**(

**a**) System-level block diagram of the analog simulator for a particle in a magnetic field. (

**b**) System-level block diagram, adjusted for SPICE-level implementation. The parameters of the simulator are: charge (q) and mass (m) of the particle, magnitude of the field (${B}_{z}$), and coefficient of the viscous friction ($\mu $).

**Figure 18.**System-level behavioral model of the analog simulator for a particle in a magnetic field implemented in SystemC AMS.

**Figure 19.**Template circuits for (

**a**) inverting gain, (

**b**) inverting integrator, and (

**c**) inverting summer.

**Figure 20.**An intermediate result from the simplification process of the analog simulator for a particle in a magnetic field.

**Figure 22.**(

**a**) Initial symbolic SFG and (

**b**) reduced SFG with numerical substitutions of the system-level model of the analog simulator for a particle in a magnetic field.

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**MDPI and ACS Style**

Coşkun, K.Ç.; Hassan, M.; Drechsler, R.
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits. *Chips* **2022**, *1*, 54-71.
https://doi.org/10.3390/chips1010006

**AMA Style**

Coşkun KÇ, Hassan M, Drechsler R.
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits. *Chips*. 2022; 1(1):54-71.
https://doi.org/10.3390/chips1010006

**Chicago/Turabian Style**

Coşkun, Kemal Çağlar, Muhammad Hassan, and Rolf Drechsler.
2022. "Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits" *Chips* 1, no. 1: 54-71.
https://doi.org/10.3390/chips1010006