Multicore Modular Multiplication of Progressive Multiplier Reduction Algorithm

Abstract

The global expansion of interconnected edge network components requires immediate strategies for securing low-power computing nodes. Cryptographic algorithms executing over binary extension fields yield considerable computational benefits because their carry-free arithmetic significantly optimizes dynamic power consumption. However, general-purpose silicon architectures lack the dedicated hardware structures to run these finite-field operations efficiently, resulting in severe processing throughput bottlenecks. This study addresses this limitation by introducing a parallelized modular multiplier framework designed to integrate smoothly with the multicore execution environments of modern embedded platforms. Our approach deploys a progressive multiplier reduction (PMR) protocol that segments dense mathematical workloads into distributed structural thread groups. This architectural alignment allows multiplication matrices and spatial field reductions to take place concurrently, balancing localized workloads while decreasing intermediate data buffering demands. We present two distinct topological styles based on column division and row division techniques, deriving comprehensive analytical formulations to capture precise silicon area footprints, critical path delays, and total operational cycle counts. The resulting hardware metrics demonstrate that the parallel PMR design achieves a highly competitive area–delay product alongside optimized dynamic consumption characteristics. This structural paradigm delivers a scalable and robust security alternative for general edge hardware, ensuring system runtime stability while meeting tight environmental power constraints, protecting vital industrial assets, and sustaining emerging macroeconomic infrastructure.

1. Introduction

The contemporary trajectory of industrial modernization relies extensively on the deployment of autonomous embedded computing units across various global operations. Modern computing frameworks have transitioned past isolated microcontrollers into heavily integrated cyber–physical networks that regulate automated factory-floor production lines, manage smart electrical utility grids, and monitor complex logistics tracking nodes. This widespread technological transition aligns directly with international development goals, mapping explicitly to UN Sustainable Development Goal 9, which focuses on building resilient, ecologically efficient industrial infrastructure. The systemic integration of these automated nodes also supports UN Sustainable Development Goal 8, which promotes sustained economic growth by ensuring the safety and operational continuity of digital workflows powering modern commerce. However, because these versatile edge processors depend on distributed wireless channels to broadcast runtime telemetry or accept operational commands, they introduce an exposed and vulnerable surface to sophisticated cyber-adversaries. Unauthorized access or data manipulation within these critical industrial systems can trigger severe financial data theft, corporate exploitation, or catastrophic infrastructure failures that directly destabilize national economic frameworks.

Establishing dependable data protection within these exposed frameworks requires the implementation of robust, high-grade cryptographic protocols. Public-key elliptic-curve cryptography (ECC) configurations supply vital encryption and key-exchange layers, while symmetric ciphers like the Advanced Encryption Standard (AES) provide efficient data validation and blocks for firmware authentication. These mathematical tools collectively guarantee data confidentiality, information integrity, and system node verification across decentralized operating networks. Even so, embedding these computationally demanding protocols directly into edge nodes presents serious engineering challenges due to the stark physical limitations of embedded hardware. These modules are forced to operate under extremely strict thermal and power envelopes, possess limited silicon area budgets, and demand completely deterministic, low-latency execution boundaries to prevent delaying real-time automation feedback loops. Standard software routines handling these complex algebraic formulae are fundamentally insufficient for long-term standalone use, as they lack the raw arithmetic throughput and energy management required for autonomous field applications.

To circumvent these operational bottlenecks, deploying specialized hardware accelerators focused entirely on modular multiplication—the most resource-demanding arithmetic foundation of public-key engines—has become critical [1]. Within elliptic curve mathematics, modular multiplication serves as the core computational layer driving point additions and point doublings, which together dictate the overall performance of digital signature generation and verification. Designing efficient cryptographic hardware requires an optimized mathematical approach, which is why modern implementations rely heavily on the unique characteristics of the binary extension field $GF\left(2^m\right)$. In contrast to traditional prime-field ($GF\left(p\right)$) environments—where integer operations trigger long, power-hungry carry propagation paths that degrade clock speed—arithmetic execution inside $GF\left(2^m\right)$ is inherently carry-free [2,3]. Additions are resolved via simple parallel XOR gates, completely preventing carry delays, reducing the underlying silicon footprint, and making binary fields highly advantageous for edge hardware relying on battery cells or environmental energy harvesting.

The physical efficiency of a $GF\left(2^m\right)$ mathematical engine depends entirely on the chosen Polynomial Basis and the structural parameters of the irreducible field equation. While implementations utilizing Normal Basis (NB) or Redundant Basis (RB) formats can offer select operational advantages, Polynomial Basis (PB) formulations remain highly popular for general silicon execution due to their structural simplicity, predictable routing paths, and the complete elimination of complex basis-conversion processing blocks [4,5,6,7]. Furthermore, field characteristics are heavily driven by the shape of the primitive polynomial; though trinomial and pentanomial configurations are widely selected to reduce gate counts, All-One Polynomial (AOP) architectures provide highly effective alternatives for specialized arithmetic structures [8,9]. Despite these clear field-level advantages, traditional general-purpose multicore microprocessors are structurally unsuited to run $GF\left(2^m\right)$ operations because their Arithmetic Logic Units (ALUs) are explicitly wired for standard integer and fixed-point data formats. A standard processor’s internal adder uses chained full-adder arrays to handle carries, and its multiplication units are designed for integer products using carry-save arrays. Standard commercial microcontrollers are confined to basic bitwise operations that fail to scale efficiently when managing high-security field lengths such as $m=233$ or $m=409$ [10,11]. Conversely, specialized cryptographic coprocessors or Hardware Security Modules (HSMs) are custom-engineered to execute multi-field operations over $GF\left(p\right)$, $GF\left(2^m\right)$, and various post-quantum polynomial rings for post-quantum security [12]. These specialized architectures deploy highly parallelized XOR logic matrices and leverage dedicated systolic array accelerators to maximize processing concurrency while maintaining a highly restrictive power profile.

Historically, many dedicated cryptographic processors were engineered through empirical, intuitive techniques that fell short of the strict optimization demands imposed by modern parallel embedded systems. In contrast to these informal paradigms, rigorous analytical design methods empower engineers to systematically regulate execution concurrency, intercore data exchange, and processing element workloads [13]. Prior frameworks heavily relied on algorithmic dependence graphs to capture localized interactions between data variables. Although instrumental for baseline synthesis, such representations constrained the comprehensive exploration of underlying hardware design spaces. To address these limitations, a variety of architectural enhancements have emerged, including fault-detecting array configurations [14], consolidated multiplication-and-squaring blocks [15], and localized-communication Montgomery engines optimized for resource-constrained IoT applications [16,17]. Moreover, sophisticated multi-dimensional scheduling and task-mapping strategies have been developed to manage operand word lengths and interconnection overheads in structures operating over trinomial-generated fields.

While modern multicore architectures leverage spatial parallelism to bypass traditional power limitations, they introduce significant problems concerning workload balancing and inter-processor communication (IPC). In highly sensitive real-time edge nodes, dividing massive cryptographic data words across disconnected processor cores can cause routing congestion and high signal-switching activity, which rapidly exhausts limited energy reserves. Many existing parallel systolic systems are hindered by high communication-to-computation ratios, as their field-reduction stages demand continuous data shuffling across processor boundaries to resolve feedback terms. This communication bottleneck can introduce unpredictable operational latencies that disrupt sensitive real-time industrial control loops.

To solve these intercore communication issues, this paper introduces a parallelized modular multiplication framework engineered to optimize the structural match between finite-field arithmetic and the multicore layouts of modern embedded systems. Moving past traditional single-core layouts, our approach utilizes a multicore execution grid to run a progressive multiplier reduction (PMR) algorithm, drawing structural design paradigms from previous product reduction formulations. This scheme structures the overall workload by dividing computations across localized blocks of rows or columns. This targeted distribution localizes intermediate data feedback within individual processing cores, drastically lowering cross-core communication traffic and establishing uniform processor utilization compared to classic “multiply-then-reduce” hardware pipelines. This research presents a rigorous architectural evaluation platform by investigating two distinct multicore mapping strategies: progressive multiplier reduction with column division (PMR-CD) and progressive multiplier reduction with row division (PMR-RD). Utilizing formal analytical derivations, we establish explicit hardware complexity models that quantify overall silicon area, critical path propagation delays, and total clock cycle periods as functions of parallel processor scaling. A primary finding from this structural exploration indicates that the PMR-RD topology exhibits enhanced energy efficiency, characterized by a monotonically decreasing area–delay product (ADP) as a larger number of computing cores are deployed within the processing array. By validating these specialized hardware configurations, this work delivers a highly scalable, low-complexity cryptographic engine well suited for general-purpose embedded systems, thereby securing edge network nodes while sustaining strict power budgets and deterministic runtime execution profiles.

The remainder of this manuscript is structured as follows: Section 2 reviews the foundational concepts of finite-field arithmetic required for developing the PMR method. Section 3 establishes the core mathematical formulations for the progressive multiplier reduction algorithm developed in this work. Section 4 introduces the task partitioning strategies and the baseline architectures for multicore mapping. Section 5 develops the parallel progressive multiplier reduction algorithm using the column division technique (PMR-CD). Section 6 details the design and coordination layout of the proposed row division paradigm (PMR-RD). Section 7 explores the hardware mapping configurations and parallel execution modes evaluated across the multicore processing architecture. Section 8 derives analytical formulations to estimate the physical area and critical path delays of the multicore system; this section also evaluates the exact number of clock cycles required to complete the baseline and proposed parallel implementations. Section 9 analyzes the performance metrics by comparing consumed area, execution delays, and area–delay product optimization trends. Finally, Section 10 summarizes the major research findings, concludes the study, and identifies target areas for future exploration.

2. Mathematical Background for Modular Multiplication Algorithm

In this section, we delineate the essential mathematical principles governing the binary extension field $GF\left(2^m\right)$ that serve as the groundwork for establishing our progressive multiplier reduction scheme, alongside evaluating the performance metrics of the proposed algorithm implementations. Throughout this analysis, the field $GF\left(2^m\right)$ is constructed via an irreducible primitive polynomial $Q\left(x\right)$ of degree m, expressed as follows:

$$Q\left(x\right)=x^m+D\left(x\right),$$

(1)

where $\mathrm{deg}\left(D\left(x\right)\right)=k<m$.

To confirm the universal applicability of this construction across any degree m, we recall that a primitive polynomial of degree m is characterized by the existence of a primitive root $\alpha$ whose multiplicative order satisfies [18,19,20,21]

$$\mathrm{order}\left(\alpha \right)=2^m-1.$$

(2)

The total number t of such valid primitive polynomials of degree m is formally determined by

$$t={\displaystyle \frac{\varphi (2^m-1)}{m}},$$

(3)

where $\varphi$ denotes Euler’s totient function. Because $\varphi (2^m-1)\ge 1$ for all $m>1$, t is guaranteed to be a positive integer, thereby proving that valid primitive polynomials exist for any choice of m. Crucially, these defining field polynomials are not restricted to sparse structures such as trinomials or pentanomials but encompass any valid term distribution.

Based on this general formulation, applying the fundamental reduction identity

$$Q\left(x\right)\left(\mathrm{mod}Q\right(x\left)\right)\equiv 0$$

(4)

directly yields the generalized substitution relation:

$$x^m\equiv D\left(x\right)\left(\mathrm{mod}Q\left(x\right)\right).$$

(5)

To demonstrate how this reduction rule operates directly on field elements, consider an unreduced polynomial $A\left(x\right)$ whose leading term has reached degree m:

$$A\left(x\right)=x^m+{\displaystyle \sum _{i=0}^{m-1}}{a}_i{x}^i.$$

(6)

Under modulo-2 addition, $A\left(x\right)$ can be reduced to its congruent field representation in $GF\left(2^m\right)$ by adding the zero-equivalent field polynomial $Q\left(x\right)$:

$$\begin{array}{ccc}\hfill A\left(x\right)\left(\mathrm{mod}Q\right(x\left)\right)& =& \left(x^m+D\left(x\right)\right)+x^m+{\displaystyle \sum _{i=0}^{m-1}}{a}_i{x}^i\hfill \\ & =& D\left(x\right)+{\displaystyle \sum _{i=0}^{m-1}}{a}_i{x}^i.\hfill \end{array}$$

(7)

This explicit cancellation validates the primary reduction substitution rule implemented throughout our hardware framework:

$$x^m\equiv D\left(x\right)\left(\mathrm{mod}Q\left(x\right)\right).$$

(8)

Building upon this basic substitution, the following lemma defines the exact structural conditions under which a higher-degree polynomial ($d\ge m$) can be fully reduced in a single parallel iteration, versus when the reduction cascade requires additional computational cycles:

Lemma 1.

Given the polynomial

$$P\left(x\right)=x^d+V\left(x\right),$$

where

$$V\left(x\right)={\displaystyle \sum _{i=0}^{m-1}}{v}_i{x}^i$$

and $m\le d<2m-k$, it is possible to reduce $P\left(x\right)$ in one step.

Proof. 

We can write $P\left(x\right)$ as

$$\begin{array}{ccc}\hfill P\left(x\right)& =& x^m{x}^{d-m}+V\left(x\right).\hfill \end{array}$$

Using Equation (8), we can write

$$\begin{array}{ccc}\hfill P\left(x\right)\mathrm{mod}Q& =& x^{d-m}D\left(x\right)+V\left(x\right).\hfill \end{array}$$

(9)

To perform the single-step reduction of $P\left(x\right)$, the upper bound on the degree of the resulting polynomial must comply with the following inequality:

$$\begin{array}{ccc}\hfill k+d-m& <& m\hfill \\ \hfill d& <& 2m-k,\hfill \end{array}$$

(10)

which is the desired result.    □

The reduction operations in Lemma 1 apply to one-term $x^d$. The following lemma shows how a short polynomial with degree $\ge m$ can be reduced in one step:

Lemma 2.

Considering a polynomial $P\left(x\right)$ of degree d, which is expressed as

$$\begin{array}{ccc}\hfill P\left(x\right)& =& x^{m}Y\left(x\right)+V\left(x\right)\hfill \\ \hfill Y\left(x\right)& =& {\displaystyle \sum _{i=0}^{Z-1}}{y}_i{x}^i\hfill \\ \hfill V\left(x\right)& =& {\displaystyle \sum _{i=0}^{m-1}}{v}_i{x}^i,\hfill \end{array}$$

(11)

where Z denotes the total number of terms in $Y\left(x\right)$, a single-step reduction of $P\left(x\right)$ is achievable under the condition that

$$Z\le m-k.$$

Proof. 

Substituting the result of Lemma 1 into Equation (11) allows the term $x^m$ to be replaced by $D\left(x\right)$:

$$\begin{array}{ccc}\hfill x^{m}Y\left(x\right)\mathrm{mod}Q\left(x\right)& =& D\left(x\right)\times Y\left(x\right).\hfill \end{array}$$

Because the degree of $Y\left(x\right)$ is $Z-1$, this polynomial multiplication can be completed in a single step provided that the degree of $x^{m}Y\left(x\right)$ complies with the inequality

$$Z+k-1<m$$

or

$$Z\le m-k.$$

   □

3. Progressive Multiplier Reduction (PMR) Derivation

Consider two polynomials $A,B\in GF\left(2^m\right)$:

$$\begin{array}{ccc}\hfill A& =& {\displaystyle \sum _{j=0}^{m-1}}{a}_j{x}^j,\hfill \end{array}$$

(12)

$$\begin{array}{ccc}\hfill B& =& {\displaystyle \sum _{i=0}^{m-1}}{b}_i{x}^i.\hfill \end{array}$$

(13)

The product of the two in terms of PMR is expressed as

$$\begin{array}{ccc}\hfill P& =& A\times B\mathrm{mod}Q\hfill \\ & =& {\displaystyle \sum _{i=0}^{m-1}}{b}_{i}A{x}^i\mathrm{mod}Q\hfill \\ & =& {\displaystyle \sum _{i=0}^{m-1}}{b}_i\left(A{x}^i\mathrm{mod}Q\right).\hfill \end{array}$$

(14)

We can express Equation (14) as an iteration:

$$\begin{array}{ccc}\hfill A^{\left(0\right)}& =& A,P^{\left(0\right)}=b_{0}A\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill A^{\left(i\right)}& =& x{A}^{(i-1)}\mathrm{mod}Q,0<i<m\hfill \end{array}$$

(16)

$$\begin{array}{ccc}\hfill P^{\left(i\right)}& =& P^{(i-1)}+b_i{A}^{\left(i\right)}\hfill \end{array}$$

(17)

$$\begin{array}{ccc}\hfill P& =& P^{(m-1)}.\hfill \end{array}$$

(18)

Equation (16) is an unconditional shift-and-reduce operation. On the other hand, Equation (17) is a conditional add–multiply. This is a feature commonly encountered in many cryptographic algorithms such as Rivest–Shamir–Adleman (RSA) and elliptic-curve cryptography (ECC).

We can express the iteration in Equation (16) explicitly as

$$A^{\left(i\right)}=a_{m-1}^{(i-1)}D\left(x\right)+{\displaystyle \sum _{j=1}^{m-1}}{a}_{j-1}^{(i-1)}{x}^j,$$

(19)

such that the degree of the simplified multiplier polynomial is strictly bounded below m.

The progressive multiplier reduction (PMR) modular multiplication process is detailed in Table 1, where each horizontal row corresponds to the generation of an individual partial product component. This specific illustration is provided for a field dimension of $m=256$.

Table 1. Operational breakdown of the PMR modular multiplication method for $m=256$, where every sequential row denotes a computed partial product.

Iteration (i)	${\mathit{A}}^{\left(\mathit{i}\right)}$	${\mathit{P}}^{\left(\mathit{i}\right)}$
0 “Initialize”	$A^{\left(0\right)}=A$	$P^{\left(0\right)}=b_0{A}^{\left(0\right)}$
1	$A^{\left(1\right)}=x{A}^{\left(0\right)}\mathrm{mod}Q\left(x\right)$	$P^{\left(1\right)}=P^{\left(0\right)}+b_1{A}^{\left(1\right)}$
2	$A^{\left(2\right)}=x{A}^{\left(1\right)}\mathrm{mod}Q\left(x\right)$	$P^{\left(2\right)}=P^{\left(1\right)}+b_2{A}^{\left(2\right)}$
3	$A^{\left(3\right)}=x{A}^{\left(2\right)}\mathrm{mod}Q\left(x\right)$	$P^{\left(3\right)}=P^{\left(2\right)}+b_3{A}^{\left(3\right)}$
⋮
254	$A^{\left(254\right)}=x{A}^{\left(253\right)}\mathrm{mod}Q\left(x\right)$	$P^{\left(254\right)}=P^{\left(253\right)}+b_{254}{A}^{\left(254\right)}$
255	$A^{\left(255\right)}=x{A}^{\left(254\right)}\mathrm{mod}Q\left(x\right)$	$P^{\left(255\right)}=P^{\left(254\right)}+b_{255}{A}^{\left(255\right)}$

We can express the iterations in Equations (16) and (17) in a bitwise fashion as follows:

$$\begin{array}{ccc}\hfill a_j^0& =& a_j\hfill \end{array}$$

(20)

$$\begin{array}{ccc}\hfill a_j^i& =& a_{j-1}^{i-1}+a_{m-1}^{i-1}{d}_j\hfill \end{array}$$

(21)

$$\begin{array}{ccc}\hfill p_j^i& =& p_j^{i-1}+b_i{a}_j^i\hfill \end{array}$$

(22)

$$\begin{array}{ccc}\hfill p_j& =& p_j^{m-1},\hfill \end{array}$$

(23)

where the indices have the ranges $0\le i<m$ and $0\le j<m$.

The iterations in Equations (21) and (22) correspond to a regular iterative expression that can be implemented as a hardware systolic array or as a software multithreaded system using formal techniques explained in [22].

3.1. Study of Algorithm Variables

An iterative procedure governed by two distinct indices, i and j, is formulated in Equations (20)–(23). Because these indices are restricted to positive integer values, the corresponding iterations span a two-dimensional (2D) convex domain denoted as $\mathcal{D}\in {\mathbb{Z}}^2$ [22]. This algorithm operates on the input multiplier polynomials A and B, alongside the updated intermediate polynomial $A^{\left(i\right)}$ and the evolving partial product polynomial $P^{\left(i\right)}$. The final output yielded by this process is the modular product polynomial P.

The iteration dependence graph (DG) for a field size of $m=256$ is illustrated in Figure 1. For this graphical representation, a degree-256 primitive trinomial is assumed with the structural form

$$Q\left(x\right)=x^{256}+D\left(x\right),$$

(24)

where the degree of $D\left(x\right)$ is less than m and the nonzero coefficients depend on which $Q\left(x\right)$ is chosen.

Figure 1. Algorithmic DG representing the execution iterations of Equations (21) and (22) for $m=256$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

The intermediate polynomial $A^{\left(i\right)}$ bits are updated according to Equations (21) and (22). This is shown by the diagonal lines in Figure 1 as well as the red lines due to the reduction operation. The input multiplicand B bits depend only on the index i. Therefore, these bits are represented by the horizontal lines in Figure 1. The intermediate product polynomial $P^{\left(i\right)}$ is updated according to Equation (22). This is shown by the vertical lines in Figure 1.

3.2. Word-Level Standard PMR Formulation

The dependency structure governing the conventional word-level PMR technique is illustrated in Figure 2. To facilitate execution on processors that operate natively on multi-bit data blocks rather than individual bits, the multiplier operand (A) is partitioned into distinct words of size W bits. For demonstration purposes, the figure depicts an architectural instance where $m=256$, $W=8$, and $L=32$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen. The total count of multiplier words, denoted by L, is computed as follows:

$$L=⌈{\displaystyle \frac{m}{W}}⌉.$$

(25)

Figure 2. Classic word-based PMR algorithm DG. Case when $m=256$, $W=8$, and $L=32$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

To guarantee that the field dimension m is a strict integer multiple of the word length W, the most significant bit positions of m can be padded with zero-valued words.

The multiplier polynomials are expressed in words in the following form:

$$\begin{array}{ccc}\hfill A& =& {\displaystyle \sum _{j=0}^{L-1}}{A}_j{x}^{Wj},0\le j<L.\hfill \end{array}$$

(26)

The product $P=A\times B$ is given by

$$P={\displaystyle \sum _{i=0}^{2L-2}}{P}_i{x}^{Wj}.$$

(27)

The bitwise iterations in Equations (15)–(18) can be expressed as word-wise iterations as follows:

$$\begin{array}{ccc}\hfill A_j^0& =& A_j\hfill \end{array}$$

(28)

$$\begin{array}{ccc}\hfill A_j^i& =& A_{j-1}^{i-1}+a_{m-1}^{i-1}{d}_j\hfill \end{array}$$

(29)

$$\begin{array}{ccc}\hfill P_j^i& =& P_j^{i-1}+b_i{A}_j^i\hfill \end{array}$$

(30)

$$\begin{array}{ccc}\hfill P_j& =& P_j^{m-1},\hfill \end{array}$$

(31)

where the indices have the ranges $0\le i<m$ and $0\le j<L$.

4. Proposed Embedded Multicore PMR Algorithm

The PMR algorithm in Section 3 is inherently bit-serial in nature. The iterations to calculate the partial product shift the multiplier by the factor $x{A}^{i-1}$ in Equation (16). Our aim is to partition the multiplication operation among C accelerators in the embedded multicore system shown in Figure 3.

Figure 3. Multicore system for parallel implementation of the PMR modular multiplication algorithm.

First, we should note that iteration i of the simple PMR algorithm in Equation (16) determines when the iteration is performed on the accelerator. The multiple accelerator system requires determining three tasks associated with each iteration value i:

1.

How to divide the modular multiplication among the cores;

2.

When to do the different iterations;

3.

Which accelerator core is assigned to do iteration i.

We propose two multicore design options, as explained in the following two sections.

5. Multicore PMR with Column Division (PMR-CD)

Our primary architecture achieves spatial concurrency by segmenting the L multiplier words across the multicore grid. The resulting allocation factor J, representing the number of words mapped to each core, is defined by

$$J=⌈{\displaystyle \frac{L}{C}}⌉.$$

(32)

The upper bound on the number of scalable cores in this architecture is governed by L, the number of words per row.

The mapping criteria that binds a specific multiplier word $A_j$ to its designated processing core c is established by the following expression:

$$c=⌊{\displaystyle \frac{j}{J}}⌋,0\le j<J,0\le c<C$$

(33)

The mapping scheme for allocating the multiplier words $A_j$ and the corresponding partial product components $P_j$ across the processing grid is demonstrated in Table 2. This example is configured for an architectural environment where $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$.

Table 2. Assigned multiplier and partial product words $A_j$ and $P_j$. Case when $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$.

	${\mathit{c}}_0$	${\mathit{c}}_1$	${\mathit{c}}_2$	${\mathit{c}}_3$
Assigned Multiplier Words $A_j$	$A_0$–$A_7$	$A_8$–$A_{15}$	$A_{16}$–$A_{23}$	$A_{24}$–$A_{31}$
Assigned Partial Product Words $P_j$	$P_0$–$P_7$	$P_8$–$P_{15}$	$P_{16}$–$P_{23}$	$P_{24}$–$P_{31}$

To summarize the proposed design of the PMR-CD architecture, each processing core is allocated J contiguous multiplier words. Each core is responsible for processing the m rows associated with its designated block. Figure 4 illustrates the distribution of columns and rows for each core in the scenario where $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

Figure 4. Multicore PMR algorithm with column division (PMR-CD). Column-wise workload distribution across the multicore processing array for an architectural configuration defined by $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

The allocation of multiplier words to the processing cores necessitates data exchange between them, as indicated by the black and red arrows. This intercore communication is facilitated through the interconnection network depicted in Figure 3.

Our strategy for the PMR-CD algorithm involves applying Equation (33) to distribute the multiplier and partial product words among the cores. Consequently, the iterations in Equations (16)–(18) can be modified within our proposed approach as follows:

$$\begin{array}{ccc}\hfill A_c^{\left(0\right)}& =& A_c,P_c^{\left(0\right)}=b_0{A}_c^{\left(0\right)},0\le c<C\hfill \end{array}$$

(34)

$$\begin{array}{ccc}\hfill A_c^{\left(i\right)}& =& x{A}_c^{(i-1)}\mathrm{mod}Q\left(x\right),0<i<m\hfill \end{array}$$

(35)

$$\begin{array}{ccc}\hfill P_c^{\left(i\right)}& =& P_c^{(i-1)}+b_i{A}_c^{\left(i\right)}\hfill \end{array}$$

(36)

$$\begin{array}{ccc}\hfill P& =& P_0^{(m-1)}\left|\right|P_1^{(m-1)}\left|\right|\cdots \left|\right|P_{C-1}^{(m-1)},\hfill \end{array}$$

(37)

where $A\left|\right|B$ means concatenate word A and word B.

The progressive multiplier reduction flow begins with Equation (34), which initializes the iterations for each core. Subsequently, Equations (35) and (36) execute the core-specific processing phases, before Equation (37) terminates the process to collect the final reduced product. Crucially, the operations defined across Equations (34)–(37) are executed concurrently by all processing cores.

The proposed PMR-CD architecture is specifically engineered to optimize intercore communication and eliminate interconnection overhead. As illustrated in Figure 4, data exchanges during execution are strictly confined to direct, point-to-point neighbor-to-neighbor links and a single broadcast line. In each iteration, the rightmost processing element transmits the reduction terms of the shifted polynomial from the preceding cycle across the shared bus. Because this broadcast originates from a single dedicated source per iteration, the network remains completely free of bus access conflicts and arbitration contention, requiring no multi-master routing or buffering hardware. Furthermore, upon algorithm completion, each core natively yields its portion of the final result, entirely bypassing the need for a final data aggregation phase or post-processing communication. Consequently, the intercore communication network operates with negligible silicon area impact and zero execution delay overhead.

6. Multicore PMR with Row Division (PMR-RD)

The second architectural scheme introduced herein processes the variables localized at iteration i and column j. Within this framework, three distinct categories of data are managed: the intermediate multiplier components $A_j^{\left(i\right)}$, the evolving partial product vectors $P_j^{\left(i\right)}$, and the individual multiplicand bits $b_i$. The underlying data is segmented into N distinct blocks, whereby each respective block is assigned to a designated processing core according to the relation

$$N=\lceil m/C\rceil .$$

(38)

To guarantee that the field dimension m is a strict integer multiple of the core count C, the most significant bit positions of m can be padded with zero values. The data words situated at row i are subsequently allocated to a designated core based on the following mapping criteria:

$$i=nC+c.$$

(39)

In the above equation, the quotient n and remainder c have the bounds

$$0\le n<N,\mathrm{and}0\le c<C,$$

(40)

where N is given by Equation (38).

Multiplicand bit $b_i$ in row i is now double-indexed with n and c:

$$b_i\equiv b_{n,c},$$

(41)

where the indices i, n, and c are interconnected via Equation (39). The notation $b_{n,c}$ specifies that the multiplicand bit $b_i$ is mapped to core c for execution during iteration step n. To clarify this distribution, Table 3 demonstrates the spatial allocation of multiplicand bits across the available core grid for a specific scenario where $m=256$, $C=4$, and $N=64$.

Table 3. Multiplicand bit distribution across the processing cores within the PMR-RD architecture, illustrated for a parameter configuration of $m=256$, $C=4$, and $N=64$.

Core c	Multiplicand Bits
0	$b_{0,0}$	$b_{1,0}$	$b_{2,0}$	$b_{3,0}$	⋯	$b_{63,0}$
1	$b_{0,1}$	$b_{1,1}$	$b_{2,1}$	$b_{3,1}$	⋯	$b_{63,1}$
2	$b_{0,2}$	$b_{1,2}$	$b_{2,2}$	$b_{3,2}$	⋯	$b_{63,2}$
3	$b_{0,3}$	$b_{1,3}$	$b_{2,3}$	$b_{3,3}$	⋯	$b_{63,3}$

Our strategy for the PMR-RD algorithm involves replacing the iteration index i with the quotient n and the remainder c. This approach stems from analyzing the shifted multiplier $\left(x^{i}A\right)$ at iteration i as presented in Equation (14). Utilizing Equation (39), we can express

$$\begin{array}{ccc}\hfill x^{i}A& =& x^{nC+c}A\mathrm{mod}Q\left(x\right)\hfill \\ & =& x^{nC}{x}^{c}A\mathrm{mod}Q\left(x\right)\hfill \\ & =& x^{nC}\left(x^{c}A\right)\mathrm{mod}Q\left(x\right).\hfill \end{array}$$

(42)

The iterations defined in Equations (15)–(18) can now be modified within our proposed technique as follows:

$$\begin{array}{ccc}\hfill A_c^{\left(0\right)}& =& x^{c}A\mathrm{mod}Q,P_c^{\left(0\right)}=b_{n,c}{A}_c^{\left(0\right)},0\le c<C\hfill \end{array}$$

(43)

$$\begin{array}{ccc}\hfill A_c^{\left(n\right)}& =& x^C{A}_c^{(n-1)}\mathrm{mod}Q,0<n<N\hfill \end{array}$$

(44)

$$\begin{array}{ccc}\hfill P_c^{\left(n\right)}& =& P_c^{(n-1)}+b_{n,c}{A}_c^{\left(n\right)}\hfill \end{array}$$

(45)

$$\begin{array}{ccc}\hfill P& =& {\displaystyle \sum _{c=0}^{C-1}}{P}_c^{(N-1)}.\hfill \end{array}$$

(46)

It is worth emphasizing that the initialization tasks defined in Equation (43) comprise C independent components that lend themselves to concurrent execution. Within this execution phase, each accelerator core c evaluates its corresponding initialization variables, $A_c^{\left(0\right)}$ and $P_c^{\left(0\right)}$. Thus, the residual value c directly identifies the specific processing node responsible for the calculation. Furthermore, the quotient index n obtained from Equation (39) is applied to track the iterative progression n within Equations (44) and (45). Adopting this structural notation, Figure 5 maps out the algorithmic dependence graph for the parallel PMR-RD framework under the conditions $m=256$, $W=8$, $L=32$, $C=4$, and $N=64$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

Figure 5. Multicore PMR-RD algorithm dependence graph (DG) for the iterations in core c. Case when $m=256$, $W=8$, $L=32$, $C=4$ and $N=64$. The red arrows show the coefficients of $D\left(x\right)$. Some of those are zero, depending on which $Q\left(x\right)$ is chosen.

As illustrated in the diagram, every word undergoes a leftward shift by a factor of $W=4$ bit positions into the adjacent higher-order word location before advancing to the subsequent row. The highest-order word within each row corresponds to the polynomial $Y\left(x\right)$ derived from Lemma 2 and is visually highlighted using red-bordered rectangles. This shifting operation, equivalent to a multiplication by $x^4$, is designated by the red arrows positioned on the right margin of each respective row.

It is noteworthy that deploying a $C=4$ core architecture decreases the row-processing requirement for each individual core from $m=256$ down to $N=64$. Scaling up the core count yields a proportional reduction in the computational workload per processing element, offering a distinct advantage over the systolic PMR algorithm implementations detailed in [23].

The proposed PMR-RD multicore design is specifically structured to eliminate intercore communication overhead during active iterative execution. By allowing each processing element to maintain and update its intermediate data locally within dedicated registers, the architecture completely avoids intercore bus traffic throughout the main execution phase. Upon completion of all iteration cycles, a single designated core sequentially collects and accumulates the partial results distributed across the remaining $C-1$ cores. Because this final accumulation phase proceeds in a deterministic, turn-based sequence using simple point-to-point transfers, the communication path remains entirely free of bus access conflicts, arbitration delays, or complex interconnect logic. Consequently, the intercore communication network introduces negligible physical resource consumption and zero routing overhead to the system architecture.

6.1. Proposed PMR-RD: Algorithm Stages

We conduct the multicore modular multiplication technique in three distinct stages:

1.

Initialization stage (could be parallelized using accelerator cores);

2.

Iterations stage (could be parallelized using accelerator cores);

3.

Termination stage (inherently sequential).

6.1.1. PMR-RD Initialization Stage

In order to eliminate communication between the cores, the pre-processing or initialization stage ensures that the different shifted versions of $x^{i}A$ are evaluated at each accelerator core and prepared as follows:

1.

The multiplier A is broadcast by the I/O to all of the accelerator cores;

2.

Accelerator core c calculates the initial shifted multiplier and initial partial product

$$\begin{array}{ccc}\hfill A_c^{\left(0\right)}& =& x^{c}A\mathrm{mod}Q\left(x\right),0\le c<C\hfill \end{array}$$

(47)

$$\begin{array}{ccc}\hfill P_c^{\left(0\right)}& =& b_{0,c}{A}_c^{\left(0\right)},0\le c<C,\hfill \end{array}$$

(48)

where the index c in this notation refers to the c-th accelerator core.

Algorithm 1 outlines the steps involved during the initialization phase. Essentially, there are two variables that need to be initialized: the shifted multiplier $x^{c}A$ and the partial product P.

Algorithm 1 Initialization stage of the proposed multicore multiplication algorithm

PARALLEL FOR $c=0:C-1$ DO         $A_c^{\left(0\right)}=x^{c}A\mathrm{mod}Q\left(x\right);$         $P_c^{\left(0\right)}=b_{0,c}{A}_c^{\left(0\right)};$ END PARALLEL FOR

6.1.2. PMR-RD Iteration Stage

The iteration stage replaces the single operations in Equations (16) and (17) with c operations for both variables. All cores operate simultaneously, such that each core performs the single operations specified in Equations (16) and (17). More importantly, the shift value $x^c$ now replaces x.

Fundamentally, the procedure partitions the m computational rows from Table 1 into C distinct segments, where each individual block encompasses $N=\lceil m/C\rceil$ rows. To guarantee that the total row count m is perfectly divisible by the available core count C, supplementary rows are appended at the lower boundary, accompanied by zero-padding at the most significant bit (MSB) positions of the multiplicand operand B. The operational flow of this iterative phase for the proposed multicore PMR multiplier accelerator is formalized in Algorithm 2.

Algorithm 2 PMR-RD iteration stage.

PARALLEL FOR $c=0:C-1$ DO        FOR $n=1:N-1$ DO              $A_c^{\left(n\right)}=x^C{A}_c^{(n-1)}\mathrm{mod}Q\left(x\right);$              $P_c^{\left(n\right)}=P_c^{(n-1)}+b_{n,c}{A}_c^{\left(n\right)};$        END FOR END PARALLEL FOR

As specified in Line 3 of Algorithm 2, the reduction procedure leverages the C higher-order bits of the multiplier component $A_c^{(n-1)}$. The concurrent execution framework, spanning Lines 1 through 6 of Algorithm 2, is managed via a PARALLEL FOR construct where each independent execution branch is mapped to one of the C available hardware accelerator cores.

6.1.3. PMR-RD Termination Stage

The termination stage is entirely sequential and is responsible for producing the required modular product P. One of the accelerator cores is designated to compute the final product, and this core contacts all of the other cores to retrieve their copies of the partial product $P_c^{(N-1)}$. Consequently, the generation of the final output product is conducted as follows:

$$P={\displaystyle \sum _{c=0}^{C-1}}{P}_c^{(N-1)}.$$

(49)

Algorithm 3 summarizes these operations.

Algorithm 3 PMR-RD algorithm termination stage

$P=0$; FOR $c=0:C-1$ DO        $P=P+P_c^{(N-1)};$ END FOR

7. Implementations of Modular Multiplication Algorithms

The subsequent subsections evaluate four primary structural configurations designed for executing modular multiplication over $GF\left(2^m\right)$. Specifically, Section 7.1 explores the multiply-then-reduce (MtR) approach, followed by an analysis of the standard progressive multiplier reduction (PMR) technique in Section 7.2. We then investigate two multicore variants incorporating row division, denoted as PMR-CD and PMR-RD, in Section 7.3 and Section 7.4, respectively. Each hardware implementation reviewed in this study assumes an underlying processor architecture tailored to support the respective algorithmic flow.

7.1. MtR Implementation

The multiply-then-reduce strategy executes polynomial multiplication using two m-term polynomials, A and B, yielding an intermediate product polynomial P comprising $(2m-1)$ terms. It is not practical to use a parallel $m\times m$ multiplier to do the multiplication, due to area limitations. The reason why the parallel multiplier accepts only half-words is to produce a full-word product. Since all algorithms will be implemented on the same multicore embedded system, the clock period of the cores will be chosen to be larger than the largest delay of any of the four algorithms enumerated above. The estimates of delays are derived in Section 8.

Assume that the processor to perform modular multiplication has word size W bits. It is natural therefore to express the polynomials A and B in terms of words:

$$\begin{array}{ccc}\hfill A& =& A_0+x^W{A}_1+\cdots +x^{(L-1)W}{A}_{L-1},\hfill \end{array}$$

(50)

$$\begin{array}{ccc}\hfill B& =& B_0+x^W{B}_1+\cdots +x^{(L-1)W}{B}_{L-1},\hfill \end{array}$$

(51)

where the number of words is L as given in Equation (25).

It is not practical to design an $m\times m$ multiplier, due to several reasons:

1.

It is not practical to move m-bit words on the processor bus, especially when m varies with the $GF\left(2^m\right)$ field in use.

2.

It is not practical to implement an $m\times m$ parallel multiplier, particularly when m varies with the $GF\left(2^m\right)$ field in use.

3.

It is not practical to design m-bit registers, especially when m varies with the $GF\left(2^m\right)$ field in use.

A better approach is to design a partitioned multiplier. Figure 6 shows how an $m\times m$ polynomial multiplier is partitioned using $W\times W$ smaller multipliers for the case when $m=256$, $W=32$, and $L=8$. The general direction for the flow of data among the blocks is from top to bottom and from left to right.

Figure 6. Partitioning an $m\times m$ polynomial multiplier using $W\times W$ smaller multipliers. Case $m=256$, $W=32$, and $L=8$.

The $W\times W$ multiplier is shown in more detail in Figure 7.

Figure 7. Detail of the $W\times W$ multiplier. (a) Inputs and outputs of the multiplier. (b) Detail of a single cell (blue circle).

Figure 7a shows the inputs and outputs of the multiplier. The $W\times W$ multiplier accepts the following inputs:

1.

Input word from the top ($P_t$);

2.

Input word from the left ($P_{\mathsf{\ell }}$).

Similarly, the partitioned multiplier produces the following outputs:

1.

Output word from the bottom ($P_b$);

2.

Output word from the right ($P_r$).

Figure 7b shows details of a single cell (blue circle).

The product has $2m$ bits or $2L$ words, as shown at the right and bottom edges of Figure 6. The numbers inside each block represent the time of executing the block. Each cell is composed of an AND gate to generate the product bit $b_i{a}_j$, and the resulting partial product is given by

$$p_{out}(i,j)=p_{in}(i,j)+b_i{a}_j.$$

The scheduling of the functional blocks is designed to ensure that precisely one multiplier word and one multiplicand word are delivered to a given block at any specific time step. Consequently, the temporal execution assigned to the multiplier unit situated at row i and column j in Figure 6 is defined by the following scheduling function:

$$\begin{array}{ccc}\hfill t\left(\mathbf{p}\right)& =& iL+(L-j-1),0\le i,j<L.\hfill \end{array}$$

(52)

Figure 8 shows the processor that performs the MtR algorithm. The processor’s multiplier/adder is composed of three main modules: The first module is the selector that accepts an input W-bit word and produces two outputs, as will be discussed below. The second module is the multiply–add that performs $W\times W$ multiplication as well as performing the addition operation. The third module is the linear feedback shift register (LFSR) that performs polynomial reduction.

Figure 8. Structural layout of the MtR processor.

As illustrated in Figure 8, the internal architecture of the MtR processor incorporates four distinct register banks:

1.

At the top-left corner of the figure are two W-bit register banks, with L registers each, to store the multiplier A and multiplicand B.

2.

At the top-right corner of the figure are two W-bit register banks $P_{TB}$ and $P_{LR}$, with L registers each, to store the intermediate product results and the final product.

There is specialized hardware to do data shifting and do final product reduction using the LFSR. Figure 9 shows the detail of the selector block in Figure 8.

Figure 9. The bit selector structure.

The selector accepts one word at its input and the bit selector produces two output words Word 1 and Word 2. These two output words are selected according to the following expressions:

$$\begin{array}{ccc}\hfill \mathrm{Input}\mathrm{Word}& =& \begin{array}{ccccccc}{A}_0& A_1& A_2& \cdots & A_{W-3}& A_{W-2}& A_{W-1}\end{array}\hfill \end{array}$$

(53)

$$\begin{array}{ccc}\hfill \mathrm{Output}\mathrm{Word}1& =& \begin{array}{ccccccc}0& 0& 0& \cdots & 0& 0& A_{W-1}\end{array}\hfill \end{array}$$

(54)

$$\begin{array}{ccc}\hfill \mathrm{Output}\mathrm{Word}2& =& \begin{array}{ccccccc}0& A_0& A_1& \cdots & A_{W-4}& A_{W-3}& A_{W-2}.\end{array}\hfill \end{array}$$

(55)

Figure 10 shows the detail of the MtR multiplier/adder of Figure 8.

Figure 10. Structure of the MtR multiplier/adder.

The MtR multiplier/adder has two components: the $W\times W$ multiplier, whose structure is shown in Figure 7; and the W-bit $GF\left(2^m\right)$ adder, which is composed of W two-input XOR gates.

Figure 11 performs the reduction of the $2m$-bit product P using a linear feedback shift register (LFSR). The figure shows a Galois LFSR for the case when the primitive polynomial is $Q\left(x\right)=x^8+x^2+1$, and this is indicated by the two feedback inputs feeding the inputs of flip-flops $D_0$ and $D_2$. The LFSR accepts bit-serial data, and this is accomplished using a parallel-to-serial register converter, as shown on the left of the figure.

Figure 11. Galois LFSR commonly used for reducing an input polynomial P. Case when the primitive polynomial is $Q\left(x\right)=x^8+x^2+1$.

7.2. Implementation of Standard PMR Algorithm

Figure 12 shows the processor that performs the PMR algorithm, as was explained in Table 1 and the corresponding iterations in Equations (28)–(31).

Figure 12. Processor structure for the word-based PMR algorithm.

The details of the PMR selector are shown in Figure 9. Figure 13 shows the detail of the PMR multiply/add module.

Figure 13. Details of the PMR multiplier/adder.

The PMR processor maintains three register banks, as follows:

1.

Two W-bit register banks, with L registers each, to store the multiplier A and multiplicand B;

2.

One W-bit register bank P, with L registers, to store the partial product results and the final product.

The operational orchestration of word processing across the hardware blocks is governed by a precise time-scheduling function. For a multiplier word located at spatial row coordinates i and column coordinates j, the specific execution time slot $t\left(\mathbf{p}\right)$ is systematically allocated using the following linear scheduling relationship:

$$\begin{array}{ccc}\hfill t\left(\mathbf{p}\right)& =& iL+j,0\le i<m,,0\le j<L.\hfill \end{array}$$

(56)

This scheduling function coordinates the sequential routing of operands from the register banks over successive clock cycles, matching the programmatic algorithm iterations.

The mathematical operations are partitioned between two specialized processing units connected to the I/O bus: a PMR selector that interfaces directly with the A and B register files to prepare operand sub-words, and an Add/Mult module that executes calculations through dual logical pathways. As shown in the gate-level diagram of Figure 12, the module’s bit multiplier path passes de-multiplexed operands into registers $R1$ and $R2$ to perform word-based bitwise multiplication using parallel NAND gates and bit-inverters, capturing the results in register $R3$. Simultaneously, the adder path routes operands via registers $R4$ and $R5$ to a parallel array of XOR-based adders for finite-field additions, buffering the sum in register $R6$ before updating the partial product bank P over the system bus.

7.3. Implementation of PMR-CD Option

The spatial partitioning of the multiplier words across the multicore framework is illustrated in Figure 4. Building upon this distribution, Figure 14 presents the complete multicore hardware architecture implementing the parallel PMR-CD algorithm.

Figure 14. Implementation of the PMR-CD algorithm. Each core operates on J columns of the multiplier words and all of the multiplicand bits.

The internal organization of each core follows the architecture illustrated in Figure 12; however, execution within an individual core is restricted to J multiplier words alongside the complete set of multiplicand bits. Specifically, core c manipulates J consecutive words of both the multiplier and the partial product, while simultaneously utilizing all available multiplicand bits.

To implement the PMR-CD algorithm on a multicore system, we need to do two operations: (i) projecting the words shown in Figure 4 to the processor or each core, and (ii) scheduling the workload of each core shown in Table 4.

Table 4. Iteration scheduling for the multicore implementation of the PMR-CD algorithms. Case $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$.

Row	Multiplier Word
$\mathit{i}$	${\mathit{A}}_{\mathbf{0}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{1}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{2}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{3}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{4}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{5}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{6}}^{\left(\mathit{i}\right)}$	${\mathit{A}}_{\mathbf{7}}^{\left(\mathit{i}\right)}$
0	0	1	2	3	4	5	6	7
1	8	9	10	11	12	13	14	15
⋮	⋮
255	2040	2041	2042	2043	2044	2045	2046	2047

7.3.1. Projection Function Design for PMR-CD

Equation (33) defines the selected projection function, which maps each distinct partial product or multiplier word, $P_j$ or $A_j$, within the column limits $0\le j<J$ to a designated processing core.

7.3.2. Scheduling Function Design for PMR-CD

The projection function specified by Equation (33) dictates our choice of the timing function. We have some considerations that must be observed:

1.

All cores processing the L words in a given row operate in parallel;

2.

Each core operates on J words, where J is determined by Equation (32).

The specific time coordinate mapped to the evaluation of the multiplier and partial product words $A_j^{\left(i\right)}$ and $P_j^{\left(i\right)}$ during the i-th iteration at column position j is formulated as follows:

$$t\left(i,j\right)=iJ+j,0\le i<m,0\le j<J.$$

(57)

Table 4 presents the step-by-step iteration timing metrics governing the parallel PMR-CD accelerator design, constrained to the first J column segments under the operational conditions $m=256$, $W=8$, $L=32$, $C=4$, and $J=8$.

7.4. Implementation of PMR-RD Option

Figure 5 shows how the multiplicand bits are assigned to the cores. Each core operates on N multiplicand bits. Figure 15 illustrates the multicore implementation of the PMR-RD algorithm, where core c uses the following:

Figure 15. Hardware implementation of the PMR-RD architecture, where each individual core executes operations across the entire set of multiplier words using a localized subset of N multiplicand bits.

1.

Initial shifted multiplier $x^{c}A$.

2.

Partial product words $P_j^{\left(i\right)}$ or multiplier words $A_j^{\left(i\right)}$ are mapped to the core according to Equation (39).

3.

N multiplicand rows $b(0,c)$ to $b(N-1,c)$, as shown in Table 3.

The PMR-RD dependence graph in Figure 5 is merely a graph showing how the algorithm variables depend on the algorithm indices. It does not give any indication on the scheduling of the operations or on which processing element is assigned to the algorithm tasks. Specifically, scheduling function determines the execution time associated with each node (scheduling function), and the projection function determines which processing element (PE) or software thread is assigned to a node.

The authors of [24] proposed specialized accelerators designed to efficiently implement the PMR algorithm. The main motivations were to control the processor workload and optimize the latency of the algorithm. The primary objective of this study is to map the PMR algorithm onto an embedded multicore platform composed of C processing cores. This architectural deployment directly influences the underlying scheduling and spatial projection functions, as detailed in the subsequent sections. We prioritize the formulation of the projection function first, as it establishes the framework for embedding the algorithm into the multicore system.

7.4.1. Projection Function Design for PMR-RD

Let $A_j^{\left(i\right)}$ and $P_j^{\left(i\right)}$ represent the multiplier and partial product words, respectively, at iteration index i and column index j, defined over the domains $0\le i<m$ and $0\le j<L$. These data words are allocated to a specific core c based on the spatial mapping criteria detailed in Equation (39). To illustrate this distribution framework within an embedded multicore environment, Table 5 outlines the exact allocation of multiplier words to processing units for an architectural instance where $L=32$ and $C=4$.

Table 5. Allocation framework of multiplier words $A_j$ across the processing cores for an architectural configuration where $L=32$ and $C=4$.

Word ${\mathit{A}}_{\mathit{j}}$	${\mathit{A}}_0$	${\mathit{A}}_1$	${\mathit{A}}_2$	${\mathit{A}}_3$	${\mathit{A}}_4$	${\mathit{A}}_5$	${\mathit{A}}_6$	${\mathit{A}}_7$	${\mathit{A}}_8$	⋯	${\mathit{A}}_{30}$	${\mathit{A}}_{31}$
Assigned Core c	0	1	2	3	0	1	2	3	0	⋯	2	3

Under this allocation paradigm, the multiplier and partial product words are divided among the available processing elements such that each core manages an N-word subset determined by Equation (38). As indicated by the table, core $c=0$ handles an eight-word slice of the multiplier array, specifically tracking the elements $A_0,A_4,A_8,\dots ,A_{28}$.

7.4.2. Scheduling Function Design for PMR-RD

The dependence graph $\mathcal{D}$ is mapped into a directed acyclic graph ($DAG$) via the scheduling function. Utilizing a formal design methodology, the authors of [24] derived all feasible and practical scheduling formulations for the PMR algorithm. Among the two identified functions, one specifically enables the system designer to regulate both the quantity of systolic processing elements and the individual processor workload. Equation (39) governs the assignment of multiplier and partial product words to specific cores alongside the execution timeline for the update expressions at each iteration step. This underlying function satisfies two main criteria: every core must compute all of the words within a designated row, and all cores must operate simultaneously on distinct rows. Consequently, the multiplier and product words, $A_j^{\left(i\right)}$ and $P_j^{\left(i\right)}$, are bound by the temporal scheduling function

$$t(i,j)=2(iL+j),$$

(58)

where the scaling factor of 2 accounts for the requirement to update both $A_j^{\left(i\right)}$ and $P_j^{\left(i\right)}$ during every iterative cycle.

8. Complexity Analysis of the Modular Multiplication Algorithms

In this section, we compare the delay, area, and area–delay product to complete the modular multiplication implementations. We start this section with a brief overview of power consumption source in a CMOS integrated circuit. We try to relate this power consumption to the chip area and argue that area × delay product (ADP) is equivalent to the energy consumption of the chip.

8.1. Sources of Power Consumption

Total power dissipation is fundamentally composed of static leakage, dynamic switching, and short-circuit overlap current during logic transitions. Because static leakage is governed by the source and drain diffusion regions that form the semiconductor junctions, it can be closely approximated as being proportional to the total gate area. The dynamic component of power consumption is formally defined by the relation

$$P_{dyn}=Cf{V}_{DD}^2,$$

(59)

where C denotes the parasitic capacitance, f represents the operating frequency, and $V_{DD}$ is the supply voltage. Assuming uniform values for both f and $V_{DD}$, the dynamic dissipation scales primarily with the parasitic capacitance. Given that this capacitance is directly tied to the transistor’s physical source and drain dimensions, dynamic power also exhibits a linear proportionality to the gate area.

Conversely, overlap power dissipation occurs during the finite transition window when a logic gate is switching between states and passes through an intermediate voltage level. Within this transient phase, the current flow scales with the gate’s driving strength, which is a function of channel width rather than total area. Consequently, overlap current is the sole power component independent of gate area. Because automated CAD synthesis tools and circuit designers aggressively minimize short-circuit overlap to prevent performance degradation, this component is omitted from our high-level analysis. We therefore focus exclusively on static leakage and dynamic switching as the predominant power contributors, treating total power as proportional to the aggregate gate area. Furthermore, because all four modular multiplication architectures utilize identical core designs, the total energy consumption scales directly with the execution delay required to complete each respective algorithm.

8.2. Normalizing Gate Delay and Area Based on Basic Inverter Gate

When a system operates, all gates and components have the same f and $V_{DD}^2$ values. The power performance becomes determined mainly by the parasitic capacitances C. The value of the capacitance C also depends on the transistor area. Therefore, we can argue that estimates of area are also proportional to power.

The delay and area performance metrics for the foundational gates and circuits utilized in finite-field arithmetic architectures are summarized in Table 6. To establish a standardized baseline, the physical area is normalized relative to a minimum-area nMOS transistor, while the propagation delay is normalized against a minimum-area inverter. The implementation of the edge-triggered D-type flip-flop is based on the NAND-gate configuration detailed in [25]. Furthermore, all structural optimization choices aimed at achieving minimum gate delay conform to established VLSI design methodologies, such as those presented in [26].

Table 6. Normalized delay and area of major components used in field arithmetic hardware.

Component	Delay Symbol	Delay	Area Symbol	Area
Inverter	${\tau }_{inv}$	1	$A_{inv}$	3
2-Input NAND	${\tau }_{NAND}$	1	$A_{NAND}$	8
2-Input AND	${\tau }_{AND}$	2	$A_{AND}$	11
2-Input NOR	${\tau }_{NOR}$	1	$A_{NOR}$	10
2-Input OR	${\tau }_{OR}$	2	$A_{NOR}$	13
2-Input XOR (NAND based)	${\tau }_{XOR}$	3	$A_{XOR}$	30
2-Input XNOR (NAND based)	${\tau }_{XNOR}$	3	$A_{XNOR}$	30
2-1 MUX (NAND based)	${\tau }_{MUX}$	3	$A_{MUX}$	27
D-Flip Flop (NAND based) [25]	${\tau }_{DFF}$	4	$A_{DFF}$	48
W-bit selector (MUX based)	${\tau }_{select}$	3	$A_{select}$	$2W{A}_{mux}$

Evaluating the propagation delay of the proposed hardware architectures requires a precise estimation of the clock cycle count consumed by each computational phase of the modular multiplication algorithms. To facilitate this analysis, a set of foundational register-transfer level (RTL) instructions is formalized for the various hardware configurations under study. These core RTL operations are summarized in Table 7.

Table 7. Basic RTL instructions for the processors used to effect the modular multiplication algorithms.

Instruction	Comment
ADD R	Add the CPU inputs A & B and place result in R
AND R	AND operation of input A with MSB of B and place result in R
LD_CPU A R	Load register R to register A of the CPU
LD_SHIFT R	Load register R to shifter input
MULT	MtR: perform $A\times B$ with LSW in Out_1 and MSW in Out_2. PMR: perform $b_i·A_j$
SEL	Perform selection and store results in A & B
WR R A	Write move content of A to R

To demonstrate the practical application of the RTL, Figure 16 illustrates the execution of a $W\times W$ multiplication operation within the multiplier architecture of Figure 10. In this setup, the multiplication block generates two distinct W-bit outputs consisting of the least significant word (LSW) and the most significant word (MSW). As detailed in the execution diagram, the complete $W\times W$ multiplication routine requires exactly five clock cycles to compute the final results.

Figure 16. RTL code for loading and multiplying two values stored in registers $R1$ and $R2$ and storing the two LSW products in register $R3$ and MSW product in $R4$.

8.3. Complexity Analysis of the MtR Algorithm

As illustrated in Figure 8, the operational clock period is bounded by the cumulative propagation delay of three critical modules:

$$\begin{array}{ccc}\hfill {\mathrm{CLK}}_{MtR}& =& \arg \max \left({\tau }_{select},{\tau }_{mult\_add},{\tau }_{LFSR}\right).\hfill \end{array}$$

(60)

Examination of Figure 9, Figure 10 and Figure 11 reveals that the maximum delay of the modules is governed by ${\tau }_{mult-add}$. Therefore, we can write

$$\begin{array}{ccc}\hfill {\mathrm{CLK}}_{MtR}& =& {\tau }_{mult\_add}\hfill \\ & =& {\tau }_{DFF}+2{\tau }_{mux}+W\left(T_{XOR}+T_{NAND}+T_{inv}\right).\hfill \end{array}$$

(61)

The total clock cycle count required to execute the MtR algorithm is determined by analyzing its machine-level instruction trace, assuming a single-cycle execution model for each discrete operation. This algorithmic evaluation establishes the following total cycle formulation:

$$\begin{array}{ccc}\hfill {\mathcal{N}}_{MtR}& =& 13L^2+2m.\hfill \end{array}$$

(62)

The total delay of the MtR algorithm is therefore given by

$$\begin{array}{ccc}\hfill T_{MtR}& =& {\mathrm{CLK}}_{MtR}\times {\mathcal{N}}_{MtR}.\hfill \end{array}$$

(63)

With reference to Figure 8, the area of the MtR processor is estimated as

$$\begin{array}{ccc}\hfill A_{MtR}& =& A_{reg}+A_{select}+A_{mult\_add}+A_{LFSR},\hfill \end{array}$$

(64)

where $A_{reg}$ is the area of the registers (Figure 8), $A_{select}$ is the area of the selector (Figure 9), $A_{Mult}$ is the area of the $W\times W$ multiplier (Figure 7), $A_{add}$ is the area of the adder (Figure 10), and $A_{LFSR}$ is the areas of the linear feedback shift register (Figure 11). We can write these areas as follows:

$$\begin{array}{ccc}\hfill A_{reg}& =& 4LW{A}_{DFF}+7W{A}_{DFF}\hfill \end{array}$$

(65)

$$\begin{array}{ccc}\hfill A_{select}& =& 54W+2A_{MUX}+2W{A}_{DFF}\hfill \end{array}$$

(66)

$$\begin{array}{ccc}\hfill A_{\mathrm{mult}\_\mathrm{add}}& =& W^2\left(A_{inv}+A_{NAND}+A_{XOR}\right)+W{A}_{XOR}+7W{A}_{DFF}\hfill \end{array}$$

(67)

$$\begin{array}{ccc}\hfill A_{LFSR}& =& W{A}_{DFF}+m{A}_{DFF}+2A_{XOR}.\hfill \end{array}$$

(68)

The area–delay product estimate to perform the MtR algorithm is given by

$${\mathit{ADP}}_{MtR}=A_{MtR}\times T_{MtR}.$$

(69)

8.4. Complexity Analysis of the PMR Algorithm

As illustrated in Figure 12, the operational clock period is bounded by the cumulative propagation delay through two primary modules:

$$\begin{array}{ccc}\hfill {\mathrm{CLK}}_{PMR}& =& \arg \max \left({\tau }_{select},{\tau }_{mult\_add}\right).\hfill \end{array}$$

(70)

Examination of Figure 9 and Figure 13 reveals that the maximum delay of the modules is governed by ${\tau }_{mult\_add}$. Therefore, we can write

$$\begin{array}{ccc}\hfill {\mathrm{CLK}}_{PMR}& =& {\tau }_{mult\_add}\hfill \\ & =& {\tau }_{DFF}+{\tau }_{XOR}+2{\tau }_{mux}.\hfill \end{array}$$

(71)

The total clock cycle count required to execute the PMR algorithm is derived by tracking its machine-level instruction trace under a single-cycle execution model. This structural analysis provides the following mathematical expression for the total cycles:

$$\begin{array}{ccc}\hfill {\mathcal{N}}_{PMR}& =& m(1+8L).\hfill \end{array}$$

(72)

Based on these timing metrics, the cumulative delay profile for the PMR algorithm is determined by

$$\begin{array}{ccc}\hfill T_{PMR}& =& {\mathrm{CLK}}_{PMR}\times {\mathcal{N}}_{PMR}.\hfill \end{array}$$

(73)

Based on the architectural layout presented in Figure 12, the total hardware area footprint of the PMR processor is approximated by

$$\begin{array}{ccc}\hfill A_{PMR}& =& A_{reg}+A_{select}+A_{mult\_add},\hfill \end{array}$$

(74)

where we have

$$\begin{array}{ccc}\hfill A_{reg}& =& 3WL{A}_{DFF}\hfill \\ \hfill A_{mult\_add}& =& W(A_{inv}+A_{XOR}+A_{NAND})+7W{A}_{DFF}+2W{A}_{mux}\hfill \\ \hfill A_{select}& =& W{A}_{mux}+2W{A}_{DFF}.\hfill \end{array}$$

The area–delay product estimate to perform the PMR algorithm is given by

$${\mathit{ADP}}_{PMR}=A_{PMR}\times T_{PMR}.$$

(75)

8.5. Complexity Analysis of the PMR-CD Algorithm

The hardware operating clock period is dictated by Equation (71). To calculate the cumulative cycle count of the PMR-CD architecture, we trace the underlying machine-level micro-operations under a uniform single-cycle execution model, which establishes the following mathematical expression for the total cycles:

$$\begin{array}{ccc}\hfill {\mathcal{N}}_{\mathrm{PMR}\text{-}\mathrm{CD}}& =& m(1+8J).\hfill \end{array}$$

(76)

Consequently, the aggregate execution delay of the PMR-CD algorithm is formulated as follows:

$$\begin{array}{ccc}\hfill T_{\mathrm{PMR}\text{-}\mathrm{CD}}& =& {\mathrm{CLK}}_{PMR}\times {\mathcal{N}}_{PMR-CD}.\hfill \end{array}$$

(77)

Utilizing the component breakdown illustrated in Figure 12, the structural area complexity of the PMR-CD execution unit is formalized by

$$\begin{array}{ccc}\hfill A_{\mathrm{PMR}\text{-}\mathrm{CD}}& =& A_{reg}+A_{select}+A_{mult\_add}+2A_{mux},\hfill \end{array}$$

(78)

where we have

$$\begin{array}{ccc}\hfill A_{reg}& =& 3WJ{A}_{DFF}\hfill \\ \hfill A_{mult\_add}& =& W(A_{inv}+A_{XOR}+A_{NAND})+7W{A}_{DFF}+2W{A}_{mux}\hfill \\ \hfill A_{select}& =& W{A}_{mux}+2W{A}_{DFF}.\hfill \end{array}$$

The area–delay product estimate to perform the PMR-CD algorithm is given by

$${\mathit{ADP}}_{\mathrm{PMR}\text{-}\mathrm{CD}}=A_{\mathrm{PMR}\text{-}\mathrm{CD}}\times T_{\mathrm{PMR}\text{-}\mathrm{CD}}.$$

(79)

8.6. Complexity Analysis of the PMR-RD Algorithm

The operating clock period is given by Equation (71). To determine the overall cycle count for the PMR-RD algorithm, we monitor the machine-level instruction trace under a uniform single-cycle execution model, which establishes the following expression for the total cycles:

$$\begin{array}{ccc}\hfill {\mathcal{N}}_{\mathrm{PMR}\text{-}\mathrm{RD}}& =& N(1+8L).\hfill \end{array}$$

(80)

Based on these timing metrics, the cumulative delay profile for the PMR-RD scheme is determined by

$$\begin{array}{ccc}\hfill T_{\mathrm{PMR}\text{-}\mathrm{RD}}& =& {\mathrm{CLK}}_{\mathrm{PMR}}\times {\mathcal{N}}_{\mathrm{PMR}\text{-}\mathrm{RD}}.\hfill \end{array}$$

(81)

Based on the architectural layout presented in Figure 12, the total hardware area footprint of the PMR-RD processor is approximated by

$$\begin{array}{ccc}\hfill A_{\mathrm{PMR}\text{-}\mathrm{RD}}& =& A_{reg}+A_{select}+A_{mult\_add}+2A_{mux},\hfill \end{array}$$

(82)

where we have

$$\begin{array}{ccc}\hfill A_{reg}& =& 3WL{A}_{DFF}\hfill \\ \hfill A_{mult\_add}& =& W(A_{inv}+A_{XOR}+A_{NAND})+7W{A}_{DFF}+2W{A}_{mux}\hfill \\ \hfill A_{select}& =& W{A}_{mux}+2W{A}_{DFF}.\hfill \end{array}$$

The area–delay product estimate to perform the PMR-RD algorithm is given by

$${\mathit{ADP}}_{\mathrm{PMR}\text{-}\mathrm{RD}}=A_{\mathrm{PMR}\text{-}\mathrm{RD}}\times T_{\mathrm{PMR}\text{-}\mathrm{RD}}.$$

(83)

9. Results and Discussion

In this section, we present a comprehensive performance evaluation and comparative analysis of the proposed progressive multiplier reduction (PMR) architectures. To demonstrate scalability and hardware efficiency, we compare the PMR-CD and PMR-RD variants against baseline MtR and conventional PMR designs over the parameter range $100\le m\le 1000$, with $W=32$ and core counts $C\in \{2,4,6,8\}$. This evaluation focuses specifically on three key metrics: normalized hardware area, normalized execution latency, and normalized area–delay product (ADP)/energy overhead.

9.1. Performance of PMR-CD Algorithms

The normalized hardware area overhead for the MtR, PMR, and PMR-CD configurations is illustrated in Figure 17, evaluated across the key parameter spaces $100\le m\le 1000$, a word size of $W=32$, and core counts $C\in \{2,4,6,8\}$. The results indicate that the baseline MtR architecture consumes the largest area footprint among all evaluated schemes. Conversely, both multicore PMR strategies yield a substantial reduction in silicon area compared to the traditional implementations, highlighting the physical resource efficiency inherent to the decentralized multicore topology.

Figure 17. Normalized area comparison for MtR, PMR, and PMR-CD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

The execution delay profiles for the MtR, PMR, and PMR-CD configurations are plotted in Figure 18, evaluating performance over the range $100\le m\le 1000$ with a word width of $W=32$ across core counts $C\in \{2,4,6,8\}$. Among the evaluated architectures, the standard PMR system exhibits the maximum processing latency. Conversely, the PMR-CD variants display distinct step-like latency variations, which stem directly from the discrete boundary parameters J and L formulated in Equations (25) and (32). The lower bounds of the plot correspond to the multicore implementations, which deliver the most substantial latency savings. This optimization is driven by allocating multiplier segments and partial product blocks across parallel processing elements. Although expanding the core count yields shorter delays, this performance advantage starts to saturate beyond eight cores, indicating a practical scaling threshold under current operational constraints. This trend of diminishing returns is analytically explained by the inverse dependence on C in Equation (32), where the derivative (${\displaystyle \frac{dJ}{dC}}\propto -{\displaystyle \frac{1}{C^2}}$) bounds the marginal latency reduction per additional core. Furthermore, because the architecture employs dedicated point-to-point and broadcast links, this saturation is strictly governed by workload division limits rather than interconnect network bottlenecks or routing contention.

Figure 18. Normalized delay comparison for MtR, PMR, and PMR-CD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

The normalized ADP/energy profiles for the MtR, PMR, and PMR-CD configurations are illustrated in Figure 19, assuming a parameter space of $100\le m\le 1000$, a word size of $W=32$, and core scaling factors $C\in \{2,4,6,8\}$. The curves indicate that the baseline MtR framework incurs the maximum ADP, marking it as the most resource-intensive design under evaluation. Conversely, the PMR-CD strategy yields a substantial enhancement in hardware efficiency, where ADP metrics scale down monotonically with the integration of additional processing cores. Given that power dissipation scales with total silicon area, the normalized ADP provides a dependable metric for evaluating relative energy overhead. These findings thus verify that the system energy consumption diminishes as a direct function of core expansion. This characteristic emphasizes the efficiency advantages of the multicore PMR-CD topology, which effectively minimizes the operational energy footprint by simultaneously accelerating execution paths and compacting physical resource usage.

Figure 19. Normalized ADP/energy comparison for MtR, PMR, and PMR-CD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

9.2. Performance of PMR-RD Algorithms

The normalized hardware area overhead for the MtR, PMR, and PMR-RD implementations is illustrated in Figure 20, evaluated across the parameter space $100\le m\le 1000$, a word size of $W=32$, and core counts $C\in \{2,4,6,8\}$. A prominent finding is that the normalized area for every PMR-derived variant remains completely static across all core variations, as evidenced by the coincident red plotline. This behavior indicates that the physical resource footprint of the PMR-RD architecture is invariant to changes in the degree of hardware parallelism. As expected, the traditional MtR framework consumes the largest silicon area among all considered configurations. Although the PMR-RD variants secure a substantial area reduction over the baseline MtR design, they lack the multicore area-scaling dynamics characteristic of alternative topologies. This outcome underlines that while PMR-RD provides superior area efficiency relative to MtR, its architectural benefits are optimized for performance indices outside of physical area minimization during core scaling.

Figure 20. Normalized area comparison for MtR, PMR, and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

The execution delay metrics for the MtR, PMR, and PMR-RD architectures are plotted in Figure 21, evaluated across a parameter sweep of $100\le m\le 1000$, a word size of $W=32$, and parallel core scales $C\in \{2,4,6,8\}$. Analogous to the CD variant, the PMR-RD framework displays distinct step-like latency variations dictated by the discrete parameters J and L from Equations (25) and (38). Among the analyzed systems, the conventional PMR scheme exhibits the highest processing latency, outperforming neither the MtR nor the parallelized PMR options. The lower bounds of the plot correspond to the multicore PMR-RD implementations, which yield the most substantial speedups. By partitioning and mapping specific word segments of the multiplier or partial products across concurrent cores, the design successfully accelerates the workload as C expands. Nonetheless, this latency optimization follows a trend of diminishing returns, where scaling past the eight-core threshold produces increasingly marginal performance gains. This behavior is theoretically governed by the inverse dependence on C in Equation (38), whose derivative (${\displaystyle \frac{dN}{dC}}\propto -{\displaystyle \frac{1}{C^2}}$) limits per-core delay reductions as the core count scales. Moreover, this performance saturation is strictly a property of workload partitioning rather than interconnected network bottlenecks, as the dedicated point-to-point communication topology eliminates routing contention.

Figure 21. Normalized delay comparison for MtR, PMR, and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

The normalized ADP/energy trends for the MtR, PMR, and PMR-RD architectures are depicted in Figure 22, assuming a parameter sweep of $100\le m\le 1000$, a word size of $W=32$, and parallel core scales $C\in \{2,4,6,8\}$. The numerical results demonstrate that the baseline MtR framework incurs the largest ADP, representing the least optimized configuration in this evaluation. In contrast, the PMR-RD strategy secures prominent gains in design efficiency, exhibiting a steady contraction in ADP as the hardware scales to higher core numbers. This behavioral profile directly influences the operational power and energy dynamics of the system. Because total power dissipation scales with the physical gate area, the normalized ADP functions as a reliable analytical estimator for relative energy expenditure. Consequently, these performance slopes verify that the system energy consumption diminishes in a nearly linear fashion as additional processing elements are integrated.

Figure 22. Normalized ADP/energy comparison for MtR, PMR, and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C\in \{2,4,6,8\}$).

9.3. Performance of PMR-CD vs. PMR-RD Algorithms

The normalized ADP and energy profiles comparing the proposed variants are plotted in Figure 23, Figure 24, Figure 25 and Figure 26, evaluating performance over the range $100\le m\le 1000$ and $W=32$ for parallel execution factors $C\in \{2,4,6,8\}$. Across all analyzed setups, the PMR-CD framework systematically achieves a lower ADP than the PMR-RD design, reflecting a more balanced trade-off between silicon resource allocation and execution velocity. Notably, the simulation curves demonstrate that expanding the core count monotonically reduces the aggregate ADP for both topologies, verifying that these architectures scale efficiently with enhanced hardware parallelism. This contraction in ADP maps directly to an improvement in electrical efficiency. Because dynamic power dissipation scales with total gate area, the minimized ADP of the PMR-CD topology proves its superior energy optimization relative to PMR-RD. Consequently, PMR-CD establishes itself as the more area-conscious and energy-efficient solution for multicore hardware scaling under the specified operational parameters.

Figure 23. Normalized ADP/energy comparison between PMR-CD and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C=2$).

Figure 24. Normalized ADP/energy comparison between PMR-CD and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C=4$).

Figure 25. Normalized ADP/energy comparison between PMR-CD and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C=6$).

Figure 26. Normalized ADP/energy comparison between PMR-CD and PMR-RD algorithms ($100\le m\le 1000$, $W=32$, $C=8$).

10. Summary and Conclusions

This paper presents two innovative parallel mapping architectures designed to optimize finite-field modular multiplication across multicore embedded platforms: the progressive multiplier reduction with column division (PMR-CD) and progressive multiplier reduction with row division (PMR-RD) frameworks. Developed as scalable alternatives to single-core hardware setups, both topologies leverage a systematic multicore execution grid to distribute computation blocks across localized rows or columns. This targeted partitioning strategy effectively localizes intermediate data feedback within individual processing cores, minimizing cross-core communication traffic and preventing routing bottlenecks common in classic MtR pipelines. Experimental and hardware complexity metrics demonstrate that both multicore PMR designs achieve profound performance gains over standard word-based PMR and conventional multiply-then-reduce (MtR) baselines. By dividing the multiplier or partial product words across parallel core arrays, both systems yield a massive reduction in operational latency and execute with highly optimized workload distributions. Notably, the PMR-RD architecture maintains a stable, constant physical footprint during scaling, whereas the PMR-CD architecture delivers distinct area-scaling benefits and consistently demonstrates a lower ADP relative to PMR-RD across all evaluated field lengths. This minimized ADP translates into a superior energy-efficiency profile, although scaling benefits encounter diminishing returns beyond a core count of eight. Ultimately, these verified parallel execution models provide a secure, high-throughput, and energy-conscious cryptographic framework tailored for resource-constrained edge infrastructure.

Future work will focus on extending these parallel architectural frameworks from binary extension fields $\mathrm{GF}\left(2^m\right)$ to prime fields $\mathrm{GF}\left(p\right)$. Implementing this parallel mapping in prime fields introduces two primary hardware complexities: First, inter-word carry propagation must be efficiently managed across the parallel processing cores without introducing critical path bottlenecks or timing stalls. Second, and more critically, prime-field arithmetic requires dynamic modular reduction following intermediate additions. Determining whether an intermediate sum exceeds the modulus p necessitates a hardware comparison step that typically requires an additional subtraction or addition operation. Future research will explore hardware-efficient mechanisms—such as deferred carry-save representations, redundant arithmetic formats, and speculative reduction structures—to eliminate these comparison cycles and mitigate carry-propagation overheads across parallel core grids.