# Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs

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## Abstract

**:**

^{2}.

## 1. Introduction

## 2. DVCCTA—Building Block and Its Properties

_{1}and Y

_{2}are very high, so that the current through these terminals is zero. Terminal X provides the difference between the voltages appearing at terminals Y

_{1}and Y

_{2}. The same current flows through both Z and X terminals. Transconductance (g

_{m}) is responsible for converting the current at terminal O to an analogous voltage at terminal Z. The tuning of the transconductance can be achieved by external voltage V

_{c}. Equation (1) denotes the port relationship in matrix form for an ideal DVCCTA:

_{m}) [23] is expressed in (2):

_{DD}and V

_{SS}respectively for positive and negative voltage. V

_{t}represents the threshold voltage of the MOS transistor. The transconductance (g

_{m}) can be controlled by adjusting the bias voltage V

_{c}. The aspect ratio for MOS transistors used in the DVCCTA design implemented here is shown in Table 1. The simulation is performed using 0.25 µm TSMC process technology with the supply voltage of ±1.5 V.

## 3. Mathematical Model of the Proposed Full-Wave Rectifier Circuit

_{A}, M

_{B}, M

_{C}, M

_{D1}, and M

_{D2}are 30/0.5, 25/0.5, 23/0.5, 5/0.5, and 5/0.5 respectively where W and L are in µm. The implementation using transistor M

_{D1}and M

_{D2}represents an active resistor (R

_{D}) and its resistance can be controlled by using an external terminal (V

_{g}) as shown in Figure 3. The active resistor provides the required resistance without the cost of wasting large area on the chip. The effect of parasitic is least using active resistor compared to passive resistor and also provides relaxation in the matching requirements. Moreover, the resistance can be controlled using the external terminal of active resistor. A sinusoidal input signal voltage is applied at terminal Y

_{1}of DVCCTA-1 for rectification. For the positive half-cycle of the applied input signal (V

_{in}(t)+), transistor M

_{A}is in the cut-off region, transistors M

_{B}, and M

_{C}is in the saturation region. The applied input voltage is conveyed from the terminal Y

_{1}of DVCCTA-2 to its X terminal using the port relationships given in (1), giving rise to a current through the NMOS transistor M

_{B}. Since the transistor M

_{A}is in the cut-off region, the current through terminal X and Z of DVCCTA-1 is zero. Using the port relationships of DVCCTA given in (1), the same current in the same direction passes through transistor M

_{B}and M

_{C}. The current passing through transistor M

_{B}can be written as:

_{tn}denotes the threshold voltage and K

_{n}depicts the device parameter of the NMOS transistor. The expression for the current through the transistor M

_{C}can be written as:

_{B}and M

_{C}is same, the voltage appearing at terminal Z of DVCCTA-2 is the same as the positive half-cycle of applied input voltage and can be written as:

_{A}, M

_{B}, and M

_{C}are in saturation, cut-off, and saturation region respectively. The applied input voltage is conveyed from the terminal Y

_{1}of DVCCTA-1 to its X terminal using the port relationships given in (1) and produces current passing through the NMOS transistor M

_{A}. The same current in the same direction flows across the terminal X and Z of DVCCTA-1. Since the transistor M

_{B}is in the cut-off region, the current through terminal X of DVCCTA-2 is the same as the current through the Z terminal of DVCCTA-1. Using the port relationships given in (1), the current flowing through terminal Z and X of DVCCTA-2 is identical in the same direction. The current passing through transistor M

_{A}can be written as:

_{A}and M

_{C}. The current passing through the transistor M

_{C}is given in (4). The voltage appearing at terminal Z of DVCCTA-2 can be obtained by manipulating Equations (4) and (6). The voltage at the Z terminal of DVCCTA-2 is found to be the same as the negative half-cycle of applied input voltage and can be written as:

_{D1}and M

_{D2}connected at terminal O of DVCCTA-2. The input signal level must be taken into consideration while implementing the full-wave rectifier circuit using DVCCTA. The presented design of the full-wave rectifier circuit provides high input impedance and low output impedance. The proposed design is capable of providing tunability features and possesses the ability to rectify small-amplitude analog signals.

## 4. Non-Ideal Analysis of the Proposed Rectifier Circuit

_{i}and α

_{j}are the non-unity voltage gain, β

_{i}is the non-unity current gain and γ

_{i}is the non-unity transconductance gain. Considering non-ideal current and voltage gain, (3) can be rewritten as:

_{i}, β

_{i}, and γ

_{i}, a slight adjustment in the biasing voltage used to bias the NMOS transistor is needed.

## 5. Parasitic Analysis of the Proposed Rectifier Circuit

_{X1}, R

_{X2}, R

_{Z1}, R

_{Z2}, R

_{Y11}, R

_{Y12}, and R

_{O}are the parasitic resistances at terminal X, Z, Y, and O respectively. C

_{X1}, C

_{X2}, C

_{Z1}, C

_{Z2}, C

_{Y11}, C

_{Y12}, and C

_{O}are the parasitic capacitances at the terminal of X, Z, Y, and O respectively. The value of parasitic resistances and capacitances connected in parallel at Y, Z, and O terminals are R

_{Y}= very high, R

_{Z}= 190 kΩ, R

_{O}= 175 kΩ, C

_{Y}= 40 fF, C

_{Z}= 0.9 pF, C

_{O}= 12 fF. The parasitic resistance connected in series at X terminal is 11 Ω. The parasitic resistance at the X terminal of DVCCTA has not been considered for the sake of calculation. These resistances will not have much effect at a higher frequency, but make the calculation much more complex.

_{d2}and I

_{d3}for the positive half-cycle of the applied input signal can be written as:

_{d1}can be written as:

## 6. Simulation Results

_{b}= −1 V. The W/L or commonly known as the aspect ratio of transistors used for implementing DVCCTA is provided in Table 1. The threshold voltage of NMOS transistor M

_{A}, M

_{B}, and M

_{C}used in Figure 3 are 0.425 V, 0.423 V, and 0.44 V respectively are chosen to compensate for the current gain and voltage gain due to non-ideality as discussed in Section 4. The transconductance parameter of DVCCTA varied depending on the range of controlling voltage V

_{c}. The value of V

_{c}lies in the range of −0.5–0.5 V. The output of the rectifier circuit is obtained from terminal O of DVCCTA-2 by controlling V

_{g}. The value of the R

_{D}resistor is around 2.5 kΩ. Figure 5 shows the DC voltage transfer characteristic of the full-wave rectifier circuit at V

_{c}= 0.5 V, V

_{g}= 0.6 V and it can be observed that the maximum input signal amplitude obtained is approximately 200 mV. The transistor at the input stage of the internal structure of DVCCTA shown in Figure 2 is no longer in the saturation region when the input voltage lies outside this range.

_{C}= 0.3 V and 0.35 V considering the constant value of Vg = 0.56 V when the input signal is of 30 mV amplitude at 1 MHz frequency. It can be observed from Figure 7 that the rectified output signal is obtained at V

_{C}= 0.38 V, 0.40 V, and 0.42 V considering the constant value of Vg = 0.56 V when the amplitude of the applied input signal is 50 mV at 1 MHz frequency. The rectified output coincides with the input signal at V

_{C}= 0.40 V. It can be observed from Figure 8 that the rectified output signal is obtained at V

_{C}= 0.40 V, 0.42 V, and 0.44 V considering the constant value of Vg = 0.56 V taking input signal as 100 mV in amplitude and having 1 MHz frequency. The rectified output coincides with the input signal at V

_{C}= 0.42 V. It can be observed from Figure 9 that the rectified output signal is obtained at Vg = 0.54 V, 0.56 V, and 0.60 V considering the constant value of V

_{C}= 0.34 V while using input signal of amplitude 50 mV at 1 MHz frequency. The rectified output coincides with the input signal at Vg = 0.56 V. Figure 6, Figure 7, Figure 8 and Figure 9 show that the rectified output of the proposed rectifier circuit can be tuned by changing the value of V

_{C}and Vg. The radical temperature change in the time domain and the DC characteristic is shown in Figure 10.

_{ox}) of all transistors as shown in Figure 11a. The DC Monte Carlo analysis is shown in Figure 11b. It is seen that the rectifier circuit is still operational within acceptable limits despite having a slight deviation in the output response. Corner analyses, such as SS, FF, and TT, have been carried out as shown in Figure 12 and even these analyses show that the rectifier circuit presented here is capable of exhibiting superior operational performance. Henceforth, this makes the proposed circuit suitable in operation under radical conditions and over a wide range of temperatures as well. The layout of the proposed full-wave rectifier circuit is created and depicted as shown in Figure 13 and post-layout simulation has been done to present the effect of the involved parasitics on the overall performance of the rectifier circuit. It covers an overall layout area of 9044 µm

^{2}(133 µm × 68 µm). It can be observed from Figure 13c that the transient response of the pre and post-layout simulation differs slightly with respect to one another which clearly shows the effects of parasitic in the design. Due to the presence of significant interconnection resistance, the distributed resistance and parasitic capacitance will influence the overall performance of the rectifier design and even lead to delays between pre- and post-layout results. The important performance parameter of the rectifier circuit is the DC value transfer (P

_{DC}) and RMS error (P

_{RMS}) [27,28], which are used to show the accuracy of the rectifier. In the ideal case, the values of P

_{DC}and P

_{RMS}should be 1 and 0, respectively. The simulation results of P

_{DC}and P

_{RMS}have been shown in Figure 14. It can be seen that the deviations in the actual output voltage can be observed by increasing the frequency and decreasing the magnitude of the input signal. The P

_{DC}decreases below one and P

_{RMS}increases when the magnitude of the input signal decreases from 100 mV to 10 mV. The simulation results obtained at frequency 1 MHz and V

_{in}= 100 mV have been compared with the results provided in [8,29,31] as shown in Figure 15 and it can be observed that [8] responds slowly and has a dead zone due to the presence of diode. Initially, [29] shows phase difference compared to the input signal, and [31] shows variations in the magnitude of the output response.

## 7. Experimental Results

_{D}of 2.2 kΩ is considered to obtain the output waveform curve as shown in Figure 17. Commonly available Keysight—DSOX3054A digital storage oscilloscope is used for this purpose. The amplitude of the output waveform depends on the bias current and increment in the amplitude is observed with the increment in bias current. The experiment is performed at a frequency of 500 kHz. Commercially available IC CA3080 is current biased (I

_{B}) as shown in the DVCCTA implementation in Figure 17 and it is exploited for varying the amplitude of the output waveform. It is clearly apparent that the amplitude of the output waveform in the presented precision rectifier varies in accordance with the bias current of the OTA used in the implementation of DVCCTA.

## 8. Comparison

## 9. Conclusions

^{2}. Moreover, the simulation results and experimental implementation carried out are in agreement with the theoretical model. The impact of non-ideality and tracking errors was assessed to analyze the performance of the proposed rectifier circuit. Moreover, the corner analysis and Monte Carlo sampling were performed to examine the robustness of the presented rectifier circuit design.

## Author Contributions

## Funding

## Conflicts of Interest

## References

- Tietze, U.; Schenk, C.; Gramm, E. Electronic Circuits-Handbook for Design and Application; Springer: Berlin/Heidelberg, Germany, 2015. [Google Scholar]
- Monpapassorn, A.; Dejhan, K.; Cheevasuvit, F. A full-wave rectifier using a current conveyor and current mirrors. Int. J. Electron.
**2001**, 88, 751–758. [Google Scholar] [CrossRef] - Toumazou, C.; Lidgey, F.J.; Chattong, S. High frequency current conveyor precision full-wave rectifier. Electron. Lett.
**1994**, 30, 745–746. [Google Scholar] [CrossRef] - Anuntahirunrat, K.; Tangsrirat, W.; Riewruja, V.; Surakampontorn, W. Sinusoidal frequency doubler and full-wave rectifier using translinear current controlled conveyors. In Proceedings of the 2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium (Cat. No.00CH37119), Kuala Lumpur, Malaysia, 24–27 September 2000; pp. 166–169. [Google Scholar]
- Kumngern, M. High frequency and high precision CMOS full-wave rectifier. In Proceedings of the 2010 IEEE International Conference on Communication Systems, Singapore, 17–19 November 2010; pp. 5–8. [Google Scholar]
- Yuce, E.; Minaei, S.; Cicekoglu, O. Full-wave rectifier realization using only two CCII+s and NMOS transistors. Int. J. Electron
**2006**, 93, 533–541. [Google Scholar] [CrossRef] - Minaei, S.; Yuce, E. A new full-wave rectifier circuit employing single Dual-X current conveyor. Int. J. Electron.
**2008**, 95, 777–784. [Google Scholar] [CrossRef] - Gift, S.G.; Maundy, B. Versatile precision full-wave rectifiers for instrumentation and measurements. IEEE Trans. Instrum. Meas.
**2007**, 56, 1703–1710. [Google Scholar] [CrossRef] - Koton, J.; Herencsar, N.; Vrba, K. Minimal configuration precision full-wave rectifier using current and voltage conveyors. IEICE Electron. Express
**2010**, 7, 844–849. [Google Scholar] [CrossRef] [Green Version] - Koton, J.; Herencsar, N.; Vrba, K. Current and voltage conveyors in current and voltage-mode precision full-wave rectifiers. Radio Eng.
**2011**, 20, 19–24. [Google Scholar] - Monpapassorn, A. Low output impedance dual CCII full-wave rectifier. Int. J. Electron.
**2013**, 100, 648–654. [Google Scholar] [CrossRef] - Stiurca, D. Truly temperature independent current conveyor precision rectifier. Electron. Lett.
**1995**, 31, 1302–1303. [Google Scholar] [CrossRef] - Beg, P.I.; Khan, A.; Maheshwari, S. Biphase amplifier based rectifiers using current conveyors. Int. J. Comput. Appl.
**2012**, 42, 14–18. [Google Scholar] - Yildiz, M.; Minaei, S.; Yuce, E. A high performance full-wave rectifier using a single CCII-, two diodes and two resistors. Sci. Iran.
**2017**, 24. [Google Scholar] [CrossRef] [Green Version] - Kumngern, M. New versatile precision rectifier. IET Circuits Devices Syst.
**2014**, 8, 141–151. [Google Scholar] [CrossRef] - Ibrahim, M.A.; Yuce, E.; Minaei, S. A new DVCC based fully cascadable voltage-mode full-wave-rectifier. J. Comput. Electron.
**2016**, 15, 1440–1449. [Google Scholar] [CrossRef] - Yuce, E.; Minaei, S.; Ibrahim, M.A. A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs. Analog. Integr. Circ. Sig. Process
**2017**, 93, 351–362. [Google Scholar] [CrossRef] [Green Version] - Petrović, P.B. Voltage Mode Electronically Tunable Full-wave Rectifier. J. Microelectron. Electron. Compon. Mater.
**2016**, 46, 229–237. [Google Scholar] [CrossRef] [Green Version] - Safari, L. A new versatile full wave rectifier using voltage conveyors. AEU Int. J. Electron. Commun.
**2020**, 122, 153267. [Google Scholar] [CrossRef] - Safari, L.; Yuce, E.; Minaei, S. A new low-power current-mode MOS only versatile precision rectifier. AEU Int. J. Electron. Commun.
**2018**, 83, 40–51. [Google Scholar] [CrossRef] - Vesković, M.; Vulović, A.; Vujičić, D.; Popović, B.; Milutinov, M. Precision Full-Wave Rectifier-Practical Realization in Discrete Technology. In Proceedings of the 2020 19th International Symposium INFOTEH-JAHORINA (INFOTEH), East Sarajevo, Bosnia and Herzegovina, 18–20 March 2020; pp. 1–5. [Google Scholar]
- Kumar, A.; Chaturvedi, B. Realization of ASK/BPSK modulators and precision full-wave rectifier using DXCCII. AEU Int. J. Electron. Commun.
**2019**, 99, 146–152. [Google Scholar] [CrossRef] - Ranjan, R.K.; Raj, N.; Bhuwal, N.; Khateb, F. Single DVCCTA based high frequency incremental/decremental memristor emulator and its application. AEU Int. J. Electron. Commun.
**2017**, 82, 177–190. [Google Scholar] [CrossRef] - Kushwaha, A.; Paul, S.K. Inductorless realization of Chua’s oscillator using DVCCTA. Analog. Integr. Circuits Signal Process.
**2016**, 88, 137–150. [Google Scholar] [CrossRef] - Das, R.; Paul, S.K. Resistorless current mode precision rectifier using EXCCII. Analog. Integr. Circuits Signal Process.
**2020**, 103, 511–522. [Google Scholar] [CrossRef] - Kumari, S.; Nand, D. Current-mode Positive and Negative Rectifier based on DDCC suitable for Higher Frequency operations. IOP Conf. Ser. Mater. Sci. Eng.
**2021**, 1084, 012079. [Google Scholar] [CrossRef] - Koton, J.; Lahiri, A.; Herencsar, N.; Vrba, K. Current-mode dual-phase precision full-wave rectifier using current-mode two-cell winner-takes-all (WTA) circuit. Radioengineering
**2011**, 20, 428–432. [Google Scholar] - Koton, J.; Vrba, K.; Herencsar, N. Fast voltage-mode full-wave rectifier using CCII and DXCCII. In Proceedings of the 2013 8th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 28–30 November 2013. [Google Scholar] [CrossRef]
- Mehmet, S.; Minaei, S.; Ayten, U.E. Component reduced current-mode full-wave rectifier circuits using single active component. IET CircuitsDevices Syst.
**2016**, 10, 1–11. [Google Scholar] - Petrović, P.B. Current/voltage mode full-wave rectifier based on a single CCCII. Int. J. Circuit Theory Appl.
**2020**, 48, 1140–1153. [Google Scholar] [CrossRef] - Sahu, P.P.; Singh, M.; Baishya, A. A novel versatile precision full-wave rectifier. IEEE Trans. Instrum. Meas.
**2010**, 59, 2742–2746. [Google Scholar] [CrossRef] - Athipong, V.; Knobnob, B.; Kumngern, M. CMOS precision full-wave and half-wave rectifier. In Proceedings of the 2011 IEEE International Conference on Computer Science and Automation Engineering, Shanghai, China, 10–12 June 2011. [Google Scholar]
- Minhaj, N. Electronically controlled precision full-wave rectifier circuits. In Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, India, 27–28 October 2009; pp. 240–243. [Google Scholar]
- Oruganti, S.; Gilhotra, Y.; Pandey, N.; Pandey, R. New topologies for OTRA based programmable precision half-wave and full-wave rectifiers. In Proceedings of the 2017 Recent Developments in Control, Automation & Power Engineering (RDCAPE), Noida, India, 26–27 October 2017; pp. 327–331. [Google Scholar]
- Koton, J.; Herencsar, N.; Vrba, K.; Minaei, S. Precision full-wave current-mode rectifier using current differencing transconductance amplifier. In Proceedings of the 2011 IEEE 3rd International Conference on Communication Software and Networks, Xi’an, China, 27–29 May 2011; pp. 460–463. [Google Scholar]
- Khucharoensin, S.; Varakorn, K. High performance CMOS current-mode precision full-wave rectifier (PFWR). In Proceedings of the 2003 International Symposium on Circuits and Systems, Bangkok, Thailand, 25–28 May 2003. [Google Scholar]

**Figure 6.**Transient response of full-wave rectifier circuit at frequency f = 1 MHz and V

_{P}= 30 mV considering variable V

_{C}.

**Figure 10.**Temperature analysis of the proposed rectifier circuit (

**a**) Transient response (

**b**) Input and output DC characteristics.

**Figure 11.**Monte Carlo sampling response of the presented rectifier circuit (

**a**) Time response (

**b**) Input-output DC characteristics.

**Figure 13.**Layout of the proposed rectifier circuit (

**a**) Layout of DVCCTA (

**b**) Layout of the full-wave rectifier (

**c**) Transient response of pre and post-layout simulation.

**Figure 14.**(

**a**) Transfer value P

_{DC}for different input signal magnitude (

**b**) RMS error P

_{RMS}for different input signal magnitude.

**Figure 16.**Macro model circuit (

**a**) DVCCTA (

**b**) Rectifier circuit (

**c**) Breadboard implementation using commercial ICs.

**Figure 17.**Experimental result obtained using commercial ICs (

**a**) At bias current 50 µA (

**b**) At bias current 100 µA (

**c**) At bias current 200 µA (

**d**) DC transfer characteristic.

Transistors | W (µm)/L (µm) |
---|---|

M_{1}–M_{4} | 10/0.5 |

M_{5}, M_{6} | 5/0.5 |

M_{7}, M_{8} | 27/0.5 |

M_{9}, M_{11} | 44/0.5 |

M_{10}, M_{12} | 8.5/0.5 |

M_{13}–M_{23} | 15/0.5 |

Ref. No | Number of Active Components | Tunability | Number of Floating Resistors | Number of Grounded Resistors | High Input Impedance | Low Output Impedance |
---|---|---|---|---|---|---|

[2] | 1 CCII + 1 CM | No | 2 | 2 | Yes | No |

[3] | 2 CCIIs | No | 2 | 1 | Yes | No |

[4] | 3 CCCIIs | No | 5 | 2 | Yes | No |

[5] | 1 DO-OTA | No | 1 | 1 | Yes | No |

[6] | 2 CCIIs 3 NMOS | No | 0 | 0 | No | No |

[7] | 1 DXCCII 3 NMOS | No | 0 | 0 | Yes | No |

[8] | 1 CCII 1 Op-Amp | No | 3 | 2 | Yes | Yes |

[9] | 1 CCII 1 UVC | No | 2 | 2 | Yes | Yes |

[10] | 1 CCII 1UVC | No | 3 | 3 | Yes | No |

[11] | 2 CCIIs | No | 3 | 1 | Yes | No |

[12] | 2 CCIIs | No | 2 | 1 | Yes | No |

[13] | 2 DVCCs 1 NMOS 1 VF | No | 3 | 0 | No | Yes |

[14] | 1 CCII- | No | 2 | 1 | No | No |

[15] | 1 CCII 28 MOS | No | 1 | 1 | Yes | Yes |

[16] | 2 DVCC + | No | 2 | 2 | Yes | Yes |

[17] | 2 CFOAs | No | 0 | 0 | Yes | Yes |

[18] | 1 MO-CCII 1 ZCD 2 MOS | Yes | 0 | 1 | No | Yes |

[19] | 2 VC 2 Diode | No | 0 | 1 | Yes | Yes |

[20] | 1 DO-CCII 12 MOS | No | 0 | 0 | No | No |

[21] | 1 OC 4 CM | No | 0 | 2 | NA | NA |

[22] | 1 DX-CCII 2 MOS | No | 1 | 1 | Yes | No |

[25] | 1 EXCCII 2 MOS | No | 0 | 0 | No | No |

[26] | 1 DDCC 2 MOS | No | 0 | 3 | Yes | No |

[27] | 2 WAT | No | 0 | 0 | No | No |

[28] | 1 CCII 1 DX-CCII 2 Diode | No | 1 | 1 | No | No |

[29] | 1 OTA 2 Diode | Yes | 0 | 2 | Yes | No |

[30] | 1 CCCII 4 MOS | No | 0 | 1 | Yes | No |

[32] | 1 COMP 2 CM 2 Diode | No | 0 | 0 | No | No |

[33] | 1 OTA 2 MOS | Yes | 0 | 2 | Yes | No |

[34] | 3 OTRA 6 MOS | Yes | 8 | 0 | No | No |

[35] | 1 CDTA 4 Diode | Yes | 0 | 1 | No | Yes |

[36] | 2 CM | No | 1 | 0 | No | No |

Our work | 2 DVCCTA 5 NMOS | Yes | 0 | 0 | Yes | Yes |

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**MDPI and ACS Style**

Raj, N.; Sagar; Ranjan, R.K.; Priyadarshini, B.; Bizon, N.
Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs. *Electronics* **2021**, *10*, 1262.
https://doi.org/10.3390/electronics10111262

**AMA Style**

Raj N, Sagar, Ranjan RK, Priyadarshini B, Bizon N.
Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs. *Electronics*. 2021; 10(11):1262.
https://doi.org/10.3390/electronics10111262

**Chicago/Turabian Style**

Raj, Niranjan, Sagar, Rajeev Kumar Ranjan, Bindu Priyadarshini, and Nicu Bizon.
2021. "Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs" *Electronics* 10, no. 11: 1262.
https://doi.org/10.3390/electronics10111262