- Article
An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS
- Javad Tavakoli,
- Hossein Miri Lavasani and
- Samad Sheikhaei
17 December 2023
A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase t...

