# Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

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## Abstract

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^{2}. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

## 1. Introduction

## 2. DLL Architecture and Operation

## 3. Circuit Implementation

#### 3.1. Current-Starved Delay Cell

#### 3.2. XOR Logic

#### 3.3. Duty Cycle Correction Loop

#### 3.4. Simulation Results of a Single 2× Multiplication Stage

## 4. Experimental Results

^{2}. The layout and micrograph of the circuit is shown in Figure 9.

_{min}), operating bandwidth (BW in %), and Area (A). The comparison of performance is summarized in Table 1. The proposed multiplier achieves the best FOM due to lower power consumption, wider operating bandwidth, and better multiplication factor/area ratio. Note that a lower FOM is an indication of better performance.

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Sansoy, M.; Buttar, A.S.; Goyal, R. Empowering Wireless Sensor Networks with RF Energy Harvesting. In Proceedings of the 2020 IEEE 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 27–28 February 2020; pp. 273–277. [Google Scholar]
- Hou, B.; Chen, H.; Wang, Z.; Mo, J.; Chen, J.; Yu, F.; Wang, W. A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks. Sensors
**2017**, 17, 223. [Google Scholar] [CrossRef] [PubMed] - Vauche, R.; Bergeret, E.; Gaubert, J.; Bourdel, S.; Fourquin, O.; Dehaese, N. A remotely UHF-powered UWB transmitter for high precision localization of RFID tag. In Proceedings of the 2011 IEEE International Conference on Ultra-Wideband (ICUWB), Bologna, Italy, 14–16 September 2011; pp. 494–498. [Google Scholar]
- Finkenzeller, K. RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, 2nd ed.; Wiley: West Sussex, UK, 2003; pp. 134–136. [Google Scholar]
- Papotto, G.; Carrara, F.; Finocchiaro, A.; Palmisano, G. A 90-nm CMOS 5-Mbps crystal-less RF-powered transceiver for wireless sensor network nodes. IEEE J. Solid-State Circuits
**2014**, 40, 335–346. [Google Scholar] [CrossRef] - Saavedra, C.E.; Zhang, Y. A clock frequency doubler using a passive integrator and emitter-coupled comparator circuit. In Proceedings of the 2004 IEEE Canadian Conference on Electrical and Computer Engineering, Niagara Falls, ON, Canada, 2–5 May 2004; Volume 1, pp. 137–140. [Google Scholar]
- Du, Q.; Zhuang, J.; Kwasniewski, T. A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier with Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Expr. Briefs
**2006**, 53, 1205–1209. [Google Scholar] [CrossRef] - Foley, D.J. CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator. IEEE J. Solid-State Circuits
**2001**, 36, 417–423. [Google Scholar] [CrossRef] - Wei, G.-Y.; Stonick, J.T.; Weinlader, D.; Sonntag, J.; Searles, S. A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25 µm CMOS. In Proceedings of the 2003 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 3 February 2003; Volume 1, pp. 464–465. [Google Scholar]
- Farjad-Rad, R.; Dally, W.; Ng, H.T.; Senthinathan, R.; Lee, M.J.; Rathi, R.; Poulton, J. A Low-Power Multiplying DLL for Low-Jitter Multi-gigahertz Clock Generation. IEEE J. Solid-State Circuits
**2002**, 37, 1804–1811. [Google Scholar] [CrossRef] - Cochet, M.; Clerc, S.; Naceur, M.; Schamberger, P.; Croain, D.; Autran, J.L.; Roche, P. A 28 nm FD-SOI standard cell 0.6–1.2 V open-loop frequency multiplier for low power SoC clocking. In Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 22–25 May 2016; pp. 1206–1209. [Google Scholar]
- Lee, W.; Dinc, T.; Valdes-Garcia, A. Reconfigurable 60-GHz Radar Transmitter SoC with Broadband Frequency Tripler in 45-nm SOI CMOS. In Proceedings of the 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Boston, MA, USA, 2–4 June 2019; pp. 43–46. [Google Scholar]
- Balasubramaniyan, A.; Bellaouar, A. Digital Frequency Multiplier for LO Generation using 22-nm FDSOI. In Proceedings of the 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 15 October 2018; pp. 1–2. [Google Scholar]
- Celis, J.-P.; Prakash, B. Chapter 4—Surface Modification of Materials by Plasma Immersion Ion Implantation. In European Materials Research Society Series, Materials Surface Processing by Directed Energy Techniques; Pauleau, Y., Ed.; Elsevier: Amsterdam, The Netherlands, 2006; pp. 111–149. [Google Scholar]
- Nam, K.-H.; Hong, N.-P.; Park, J.-S. A 16-Times Frequency Multiplier for 5G Synthesizer. IEEE Trans. Microw. Theory Tech.
**2021**, 69, 4961–4976. [Google Scholar] [CrossRef]

**Figure 10.**Post−layout simulation of the input vs. output frequency of the proposed circuit showing 8× multiplication.

**Figure 11.**Post layout simulated response of the duty cycle correction loop. The circuit takes 40 μs to achieve a 50% duty cycle.

This Work | [11] | [12] | [13] | |
---|---|---|---|---|

Supply Voltage (V) | 0.8 | 0.6–1.2 | 1 | N/A |

Multiplication Factor | 8× | 32× | 3× | 3× |

Input/Output Frequency (GHz) | 0.305/2.44 | 0.017/0.574 | 20/60 | 3.5/10.5 |

Timing jitter (Simulated) (ps) | 24 ps @ 2.44 GHz (pk-pk) | 97 ps @ 0.574 GHz (pk-pk) | N/A | N/A |

Normalized periodic jitter (jitter/period) | 0.0586 | 0.055 | N/A | N/A |

Power consumption (mW) | 0.13 | 2.71 | 50 | 5.5 |

Active area (mm^{2}) | 0.09 | 0.014 | 0.4 | 0.075 |

Technology | 22 nm FD-SOI | 28-nm FD-SOI | 45 nm SOI CMOS | 22 nm FD-SOI |

FOM | 74.01 | 91.76 | 111.85 | 114.53 |

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**MDPI and ACS Style**

Naveed; Dix, J.
Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI. *J. Low Power Electron. Appl.* **2023**, *13*, 64.
https://doi.org/10.3390/jlpea13040064

**AMA Style**

Naveed, Dix J.
Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI. *Journal of Low Power Electronics and Applications*. 2023; 13(4):64.
https://doi.org/10.3390/jlpea13040064

**Chicago/Turabian Style**

Naveed, and Jeff Dix.
2023. "Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI" *Journal of Low Power Electronics and Applications* 13, no. 4: 64.
https://doi.org/10.3390/jlpea13040064