Review Reports - Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameters

Round 1

Reviewer 1 Report

In the current manuscript, authors verified the fitting of the current-voltage characteristics function that was previously reported by the same group in the references : 7, 8, 21,23, 24 and 27. In addition, a very similar work was published in the same journal [Reference 27] where the same authors determined the parameters kN, Vth and lambda. Moreover, In table 1 and 2, authors mention Gate bias (4 voltage values), however, the voltage wasn't mentioned in the tables (only in text), therefore, it is confusing.

In my opinion, since the model was previously verified and confirmed, and in this report authors looks only for the dependence of some parameters as function of others, I think manuscript is not of sufficient novelty, therefore, I recommend rejection of the paper.

Author Response

To the honored reviewer 1 (thanks for pointing out the confusion The Gate bias should be corrected to “Gate Sizes”, which is our fault.)

(1)In the beginning, this fitting skill was reasonably tried with the only possibility that the conventional I-V characteristic formula had to be modified in the triode region. (2) Even so, some confusing results were not convincing until the reference [24] first noticed the size associated unreasonable issues as quoted in the paper: “The authors may focus on the devices with fin width W=0.120 microns in the future” (3) The reference [27] thus examined the three width splits including 0.120 microns, 0.115 microns, and 0.110 microns and fully support the suggestion of the only availability of W=0.120 microns. (4) In this paper, only 120 microns wide FinFET transistors are paid attentions. A lot of effort makes three parameters separately fixed and the minimum deviations are found with three advisable reached conclusions. For Kn’s fixed, three found Kn’s with minimum deviations are linear against the inverse of channel lengths as shown in reference [27], And the thickness of strong inversion layer in the channels is possibly calculated to be 203 angstroms. For lambda’s fixed, three lambda’s with minimum deviations are found to be the most minimum deviations among all those fittings which suggest fitting starts. For Vth’s fixed, three found Vth’s with minimum deviations are linear against channel lengths (100nm, 160nm, and 240nm), which invite another transistor whose channel length are 500nm with 120 wide Fin. The measured I_DS-V_GS curve suggests 0.25 volt threshold voltage, which is really approaching.

Author Response File: Author Response.pdf

Reviewer 2 Report

Dear authors, your manuscript need some needful corrections. It is summaries below :

1: Abstract is not appropriate. Number of symbols has been used. Re- write in attractive fashion by using good quality English

2: Figures quality is too poor . Edit all figures using appropriate font size and color. Results should attractive and error free.

3: Conclusion is not appropriate. Please r-edit it also

4: In manuscript, numbers of grammatical error have fond. Re- edit all contents . Remove errors

5: Introduction seem weak . Re- write this section using some more published articles reslted to 3 D FET devices. You can use some advanced reference like:

Y. S. Song, S. Tayal, S. B. Rahi, J. H. Kim, A. K. Upadhyay and B. -G. Park, "Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET," 2022 5th International Conference on Circuits, Systems and Simulation (ICCSS), 2022, pp. 135-140, doi: 10.1109/ICCSS55260.2022.9802341.

6: What is limitation of FinFET device. Why research scholars is looking toward, GAA, and Nanosheet FET?

Author Response

Dear authors, your manuscript need some needful corrections. It is summaries below :

We appreciate your advices. We would follow what you advise us to do.

1: Abstract is not appropriate. Number of symbols has been used. Re- write in attractive fashion by using good quality English

(Abstract has been re-written.)

2: Figures quality is too poor . Edit all figures using appropriate font size and color. Results should attractive and error free.

(Figures have been re-modified.)

3: Conclusion is not appropriate. Please r-edit it also

(Conclusion has been re-edited.)

4: In manuscript, numbers of grammatical error have fond. Re- edit all contents . Remove errors

(Manuscript has been re-examined to correct the errors.)

5: Introduction seem weak . Re- write this section using some more published articles reslted to 3 D FET devices. You can use some advanced reference like:

S. Song, S. Tayal, S. B. Rahi, J. H. Kim, A. K. Upadhyay and B. -G. Park, "Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET," 2022 5th International Conference on Circuits, Systems and Simulation (ICCSS), 2022, pp. 135-140, doi: 10.1109/ICCSS55260.2022.9802341.

(It is a good paper, and is referred.)

Nevertheless, there still exist some limitations, e.g., heat dissipation. As electrical signals or power flow, Ohm’s heat inevitably increases as the size shrinks. The temperature may soar up, and electrical performances of a single transistor may just degrade unless heat sink is found and heat dissipation gets resolved. GAA(Gate all around) MOSFET thus provides a possible solution using Al₂O₃ as an insulator compared to HfO₂ and SiO₂.[13]

6: What is limitation of FinFET device. Why research scholars is looking toward, GAA, and Nanosheet FET?

For fixed lambda, three respective lambda’s of the three transistors with the most minimum deviations determine the corresponding Early Voltage values, which are plotted linearly against the inverse of channel lengths as shown in Figure 4b. That characterizes the channel length dependent leakage current, i.e., the shorter the channel length is, the leakier the transistor across Source and Drain is. This Early-Voltage-related leakage current may get larger which is not expected as the channel length gets shorter.

Negative Vth’s for shorter channel length in NFinFET may be interpreted as process related size issues addressing dry-etching consuming processes since the threshold voltage depends on space charge in the depletion region. [27] That means Vth may be as low as -0.4 volt as channel length approaches to 10 nanometer scales, which may lead to extra current beyond control.

The modified current-voltage formula used for fitting I-V characteristic curves is quite encouraging and impressive. Those fitting skills help give some underlying physical interpretations, which, unfortunately, set up a limitation for how far FinFET can go. In addition, FinFET also suffers from generated heat, thus performances down-graded, and reliability issues. Therefore, effective heat dissipation substantially needs posing. By applying bias-induced depletion technique, GAA and Nanosheet FET may be good candidates for the coming age.

Author Response File: Author Response.pdf

Reviewer 3 Report

This paper presents the test data of C-V characteristics curves of FinFET with various fixed parameters. The conclusion is well-supported by its data. However, the novelty of this work is not clear. What is the motivation for this work? What is the difference and promotion of this work compared with vast previous works? Please inform more about the novelty of this paper, which is the most important for a research article. I would suggest reconsidering after major revision for this manuscript.

Author Response

In the first place, the fitting skill here became acceptably possible only if the conventional I-V characteristic formula had to be modified in the triode region.[7, 8, 21, 23] Even so, some confusingly ambiguous results like the size associated and process related issues thus suggested that “The authors may focus on the devices with fin width W=0.120 microns in the future”.[24] Therefore, the three width splits including 0.120 microns, 0.115 microns, and 0.110 microns were examined in details and followed by the conclusion that the only availability of W=0.120 microns is fully supported.[27]

One of the three parameters (Kn, Vth, lambda) is individually fixed and the other two are tuned to find the corresponding minimum deviations, followed by three conclusive results as follows:

For fixed Kn, three respective Kn’s of the three transistors with the most minimum deviations are found to be linear against the inverse of channel lengths as shown in Figure 4a, and the thickness of strong inversion layer in the channels is possibly calculated and determined to be 203 angstroms.[27]

For fixed Vth, three respective Vth’s of the three transistors with the most minimum deviations are plotted linearly against channel lengths (100nm, 160nm, and 240nm) in Figure 5a, which invite another transistor whose channel length are 500nm with 120 wide Fin to ensure if the tendency is still true. The measured I_DS-V_GS curve suggests 0.25 volt threshold voltage as presented in Figure 5c. Negative Vth’s for shorter channel length in NFinFET may be interpreted as process related size issues addressing dry-etching consuming processes since the threshold voltage depends on space charge in the depletion region. [27] That means Vth may be as low as -0.4 volt as channel length approaches to 10 nanometer scales, which may lead to extra current beyond control.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Authors cleared up the confusion between the current manuscript and their previously reported papers. In my opinion , this work may interest the readers in the present form , therefore, I recommend that the paper can be accepted for publication.

Reviewer 3 Report

The manuscript could be accepted in its present form after revision.