Search Results (114)

This paper presents a low-power 30/60 GHz dual-band CMOS voltage-controlled oscillator (VCO) for 5G applications. The design employs an LC-VCO core that simultaneously generates differential fundamental-frequency outputs and a single-ended second-harmonic output. To improve second-harmonic spectral purity, a second-harmonic quarter-wavelength (λ/4) transmission line is inserted in the V_DD bias path of the VCO core. A body-to-ground-with-resistor (B-to-GND-with-R_B) NMOS varactor configuration is adopted to provide a wide, monotonic tuning range while suppressing substrate leakage and noise coupling. In addition, a fundamental-frequency λ/4 transmission line is introduced in the control-voltage bias path to improve AC grounding of the differential varactor center node. The VCO consumes 2.19 mW and achieves a tuning range of 24.59–30.5 GHz (21.5%). At 27.48 GHz, it exhibits a phase noise of −117.69 dBc/Hz at a 10 MHz offset, corresponding to a figure of merit (FoM) of 189.72 dBc/Hz. The second-harmonic output covers 49.18–61 GHz, with the same fractional tuning range. The VCO core occupies a compact chip area of only 0.021 mm². Full article

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain K_VCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset. Full article

Aggressive technology scaling has led to a significant increase in manufacturing process variations and transistor aging effects, which critically degrade the performance of radio frequency (RF) circuits. These reliability challenges are particularly pronounced in voltage-controlled oscillators (VCOs), where phase noise and operating frequency stability are compromised. While design strategies incorporating micro-electromechanical systems (MEMS) actuators enhance VCO performance by leveraging MEMS varactors or inductors with substantially higher quality factors (Q), this benefit is progressively undermined over time by process variations and aging-induced shifts in the threshold voltage and carrier mobility of the VCO’s transistors. This work presents an ultra-low-power current-reuse voltage-controlled oscillator (VCO) designed to maintain stable performance under process variability and reliability-induced parameter shifts. Robust operation is achieved using a self-detecting–correcting (SDC) bias scheme that senses performance drift and applies corrective feedback through body-bias control in the VCO core. Analytical relations are derived to describe the impact of threshold voltage and mobility variations, and the approach is validated via post-layout simulations in a 130 nm complementary metal-oxide semiconductor (CMOS). Under 18% variations in threshold voltage and carrier mobility, the proposed SDC scheme preserves oscillation frequency, phase noise, and figure of merit (FoM) while also mitigating the intrinsic output amplitude imbalance of conventional current-reuse VCOs. Monte Carlo analysis (500 runs) demonstrates low sensitivity to fabrication uncertainty, with a standard deviation below 0.14 dBc/Hz for phase noise, 210 kHz for oscillation frequency, and 0.4 dBc/Hz for FoM. The VCO operates from a 0.9 V supply, consumes 175 μW, and achieves −124 dBc/Hz phase noise at 1 MHz offset near 2.4 GHz (FoM ≈ −199 dBc/Hz). Full article

This paper presents a secure 2.4 GHz frequency shift keying (FSK) transmitter front-end with minimal overhead on the data stream using analog obfuscation techniques applied to the modulated waveform. An off-chip true random number generator (TRNG) unit is used to generate the required key for the encryption. Moving away from traditional FSK schemes, which benefit from constant local oscillator (LO) frequency within the channel, the proposed secure FSK scheme shifts the LO frequency in very small steps using an innovative capacitor-bank structure with a calibrated digitally controlled oscillator (DCO). The proposed capacitor bank uses a combination of parallel switches and series capacitors to minimize the impact of the layout parasitics on the minimum capacitor in the bank, thereby reliably creating sub-fF unit capacitors. When combined with the proposed capacitor bank, the cross-coupled CMOS LC voltage-controlled oscillator (VCO) forms a digitally controlled oscillator (DCO). The post-layout simulation results of the DCO reveal that the proposed scheme can achieve a resolution of <20 kHz for the LO frequency shifting while maintaining the phase-noise performance. The reported phase shift allows an equivalent entropy > 6 bits in the implemented analog-inspired secure transmitter front-end. Full article

The miniaturization of dielectric sensing has driven the development of both oscillator- and receiver-based sensors. Wide-frequency-range and low-power-consumption voltage-controlled oscillators (VCOs) are required as a reference clock for receiver-based dielectric spectroscopy. In this paper, we propose a switched coupled inductor VCO offering sufficiently wide bandwidth in a power-efficient manner. The proposed switched coupled inductor offers higher coupling factor and mutual inductance compared to direct switched inductor schemes along with a higher quality factor and tuning range. The proposed switched coupled inductor improved the frequency tuning range by 21% compared to the conventional VCO. The measurement results show that the proposed VCO oscillates from 4.7 to 8.8 GHz frequency, suitable for dielectric spectroscopy sensors. With only 4.5 mW power consumption, the proposed VCO can achieve −103.3 dBc/Hz phase noise at 1 MHz offset, with a resulting tuning range figure-of-merit (FOM_T) of −187.4 dBc/Hz. Full article

This paper presents a terahertz (THz) dual-band transmitter for a wideband sparse synthetic bandwidth radar. The transmitter employs an innovative single-path-reuse dual-band architecture. This architecture utilizes a proposed quad-transformer-coupled voltage-controlled oscillator (VCO) as an on-chip local oscillator source. It also incorporates an innovative dual-harmonic generator and a dual-band antenna, which work together within the single signal path to generate both the fundamental frequency and its second harmonic, thereby creating the dual bands required for a sparse synthetic bandwidth radar. Fabricated in a TSMC 40 nm CMOS technology, measurement results show that the transmitter achieves a peak equivalent isotropically radiated power (EIRP) of −7.95 dBm in the low-frequency band (121.34∼126.85 GHz) and −7.86 dBm in the high-frequency band (242.68∼253.7 GHz), validating the proposed architecture’s capability to generate dual-band signals simultaneously. The entire chip occupies a compact area of only 0.54 × 0.62 ${\mathrm{m}\mathrm{m}}^2$ and consumes 136 mW of DC power. Full article

The integration of AI-driven optimization into Electronic Design Automation (EDA) enables smarter and more adaptive circuit design, where symmetry and asymmetry play key roles in balancing performance, robustness, and manufacturability. This work presents a model-driven optimization methodology for sizing low-phase-noise LC voltage-controlled oscillators (VCOs) at 5 GHz, targeting Wi-Fi, 5G, and automotive radar applications. The approach uses the EKV transistor model for analytical CMOS device characterization and applies a diverse set of metaheuristic algorithms for both single-objective (phase noise minimization) and multi-objective (joint phase noise and power) optimization. A central focus is on how symmetry—embedded in the complementary cross-coupled LC-VCO topology—and asymmetry—introduced by parasitics, mismatch, and layout constraints—affect optimization outcomes. The methodology implicitly captures these effects during simulation-based optimization, enabling design-space exploration that is both symmetry-aware and robust to unavoidable asymmetries. Implemented in CMOS 180 nm technology, the approach delivers designs with improved phase noise and power efficiency while ensuring manufacturability. Yield analysis confirms that integrating symmetry considerations into metaheuristic-based optimization enhances performance predictability and resilience to process variations, offering a scalable, AI-aligned solution for high-performance analog circuit design within EDA workflows. Full article

This work presents a low-power photoplethysmography (PPG) readout integrated circuit (IC) that achieves a wide dynamic range (DR) through the direct integration of a voltage-controlled oscillator (VCO)-based quantizer into the photodiode driver. Conventional PPG readout circuits rely on either transimpedance amplifier (TIA) or light-to-digital converter (LDC) topologies, both of which require auxiliary DC suppression loops. These additional loops not only raise power consumption but also limit the achievable DR. The proposed design eliminates the need for such circuits by embedding a linear regulator with a mirroring scale calibrator and a time-domain quantizer. The quantizer provides first-order noise shaping, enabling accurate extraction of the AC PPG signal while the regulator directly handles the large DC current component. Post-layout simulations show that the proposed readout achieves a signal-to-noise-and-distortion ratio (SNDR) of 40.0 dB at 10 µA DC current while consuming only 0.80 µW from a 2.5 V supply. The circuit demonstrates excellent stability across process–voltage–temperature (PVT) corners and maintains high accuracy over a wide DC current range. These features, combined with a compact silicon area of 0.725 mm² using TSMC 250 nm bipolar–CMOS–DMOS (BCD) process, make the proposed IC an attractive candidate for next-generation wearable and biomedical sensing platforms. Full article

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits. Full article

This work proposes two voltage-controlled oscillators using noise-filtering technique. The first one is a 24-GHz voltage-controlled oscillator, and the second one is based on a push–push architecture with a $\mathsf{\lambda }$/4 transmission line to further increase the frequency up to 48 GHz. The designs are implemented and verified in a standard 90-nm CMOS process. Typically, the current mirror transistor in the tail current has a nonlinear effect. When the transistor operates in the nonlinear region, noise will be introduced. Therefore, a set of LC filters with a resonant frequency at 2$f_0$ are added to the design of this section to filter the noise at 2$f_0$ through the capacitor to the ground. The measurement results show that the design of a single oscillator has an oscillation frequency of 24.37 GHz, a tuning range of 6.5%, and a phase noise of −97.19 dBc/Hz @1MHz. The measurement results of the push–push architecture show that the double oscillation frequency is 49.8 GHz, the tuning range is 7.2%, and the phase noise is −80.52 dBc/Hz @1MHz. The chip areas of 24-GHz LC VCO and 48-GHz push–push LC VCO are 0.68 mm × 0.69 mm and 0.7 mm × 0.7 mm, respectively. Full article

This study proposes a derivative-based, carrierless pulse position modulation (PPM) scheme utilizing a voltage-controlled oscillator (VCO) and a monostable multivibrator. In contrast to conventional PPM systems that rely on reference carriers or complex demodulation methods, the proposed architecture simplifies signal generation by directly modulating the time derivative of the message signal. The modulated signal, when processed through standard analog demodulators, inherently yields the derivative of the original message. This behavior is first established through theoretical derivations and then confirmed by simulations and circuit-level experiments. The proposed method includes a differentiator feeding into a VCO, followed by a monostable multivibrator to generate a carrierless PPM waveform. Experimental validation confirms that, under all tested demodulation approaches—integrator-based, PLL-based, and quasi-FM—the recovered output aligns with the differentiated message signal. The integration of this output to retrieve the original message was not performed to maintain focus on verifying the modulation principle. Additionally, the study aimed to ensure the consistency of derivative recovery. Signal-to-noise ratio (SNR) expressions for each demodulator type are presented and discussed in the context of their relevance to the proposed system. Limitations and directions for further study are also identified. Full article

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW. Full article

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices. Full article

Wireless sensor networks (WSNs) for self-driving vehicles are growing rapidly, requiring high-performance radar systems with strong communication abilities. The key component of these systems is the voltage-controlled oscillator (VCO), which performs at 24 GHz with low phase noise, low power consumption, and a wide range of tuning. In this paper, the adaptive particle swarm optimization (PSO) algorithm incorporates adaptive scaling to speed up the optimization process. The new adaptive PSO minimizes the number of calculations required for complex engineering problems where rapid optimization is crucial and finding the best solution quickly is important. In order to test the adaptive PSO, benchmark functions are used. When applied to the proposed VCO circuit design, it facilitates more efficient adjustment of component values and improved performance, resulting in faster optimization. This optimized VCO achieves low phase noise of −120 dBc/Hz with a 1 MHz offset and a tuning range of 21.2%, operates at just 0.9 V, and consumes just 1.35 mW of power. A comparison of adaptive PSOs with traditional PSO methods shows that they improve the performance of the VCO, making them a promising choice for future automotive radar systems. Full article

In this paper, a novel Colpitts voltage-controlled oscillator (VCO) with low phase noise and an octave frequency tuning range is presented. To achieve low phase noise and a wide tuning range concurrently, the designed VCO employs quad-core-coupled structures, series resonators, dual-mode-coupled inductors, and push–push structures. The quad-core-coupled structures are used for phase noise improvement. The presented series resonators effectively expand the tuning range while reducing phase noise deterioration from amplitude-to-phase modulation (AM/PM) conversion. The dual-mode operation based on coupled inductors and quad-core structures further expands the tuning range. In addition, the adopted push–push structure increases the output frequency. Designed in a 180 nm SiGe BiCMOS process, the proposed Colpitts VCO operates from 7.2 to 14.5 GHz with an octave tuning range of 67.3%. The phase noise ranges from −131.4 to −121.8 dBc/Hz with a peak figure-of-merit (FoM) of 183.0 dBc/Hz and figure-of-merit-tuning (FoM_T) of 199.5 dBc/Hz at a 1 MHz offset. The proposed VCO exhibits superior performance in phase noise and tuning range and achieves an octave tuning range for the first time in Colpitts VCOs. Full article