Search Results (1,022)

Achieving high reliability remains the critical challenge for pulsed power supplies (PPS), whose core components are susceptible to severe degradation and catastrophic failure due to long-term operation under electrical, thermal and magnetic stresses, particularly those associated with high voltage and high current. This reliability challenge fundamentally limits the widespread deployment of PPSs in defense and industrial applications. This article provides a comprehensive and systematic review of the reliability challenges and recent technological progress concerning PPSs, focusing on three hierarchical levels: component, system integration, and extreme operating environments. The review investigates the underlying failure mechanisms, degradation characteristics, and structural optimization of key components, such as energy storage capacitors and power switches. Furthermore, it elaborates on advanced system-level techniques, including novel thermal management topologies, jitter control methods for multi-module synchronization, and electromagnetic interference (EMI) source suppression and coupling path optimization. The primary conclusion is that achieving long-term, high-frequency operation depends on multi-physics field modeling and robust, integrated design approaches at all three levels. In summary, this review outlines important research directions for future advancements and offers technical guidance to help speed up the development of next-generation PPS systems characterized by high power density, frequent repetition, and outstanding reliability. Full article

The integration of solar energy into smart grids requires high-efficiency power conversion to support grid stability. However, Partial Shading Conditions (PSCs) remain a primary obstacle by inducing multiple local maxima on P–V characteristic curves. This paper presents a hardware-aware and memory-enhanced Maximum Power Point Tracking (MPPT) approach based on a modified Dragonfly Algorithm (DA) for grid-connected microinverter-based photovoltaic (PV) systems. The proposed method utilizes a quasi-switched Boost-Switched Capacitor (qSB-SC) topology, where the DA is specifically tailored by combining Lévy-flight exploration with a dynamic damping factor to suppress steady-state oscillations within the qSB-SC ripple constraints. Coupling the MPPT stage to a seven-level Packed-U-Cell (PUC) microinverter ensures that each PV module operates at its independent Global Maximum Power Point (GMPP). A ZigBee-based Wireless Sensor Network (WSN) facilitates rapid data exchange and supports ‘swarm-memory’ initialization, matching current shading patterns with historical data to seed the population near the most probable GMPP region. This integration reduces the overall response time to 0.026 s. Hardware-in-the-loop experiments validated the approach, attaining a tracking accuracy of 99.32%. Compared to current state-of-the-art benchmarks, the proposed model demonstrated a significant improvement in tracking speed, outperforming the most recent 2025 GWO implementation (0.0603 s) by approximately 56% and conventional metaheuristic variants such as GWO-Beta (0.46 s) by over 94%.These results confirmed that the modified DA-based MPPT substantially enhanced the microinverter efficiency under PSC through cross-layer parameter adaptation. Full article

The pulsed power switch serves as a critical component in pulsed power systems. The electric radiation generated by switching operations threatens the miniaturization of pulsed power systems, causing significant electromagnetic interference (EMI) to nearby signal circuits. The pseudospark switch’s (PSS) exceptionally fast transient response, a key enabler for sophisticated pulsed power systems, is also a major source of severe EMI. This study investigated the electric field radiation from a high voltage PSS within a capacitor discharge unit (CDU), using a near-field scanning system based on an electro-optic probe. The time-frequency distribution of the radiation was characterized, identifying contributions from three sequential stages: the application of the trigger voltage, the main gap breakdown, and the subsequent oscillating high voltage. During the high-frequency oscillation stage, the distribution of the peak electric field radiation aligns with the predictions of the dipole model, with a maximum value of 43.99 kV/m measured near the PSS. The spectral composition extended to 60 MHz, featuring a primary component at 1.24 MHz and distinct harmonics at 20.14 MHz and 32.33 MHz. Additionally, the impacts of circuit parameters and trigger current on the radiated fields were discussed. These results provided essential guidance for the electromagnetic compatibility (EMC) design of highly-integrated pulsed power systems, facilitating more reliable PSS applications. Full article

With the advancement of power electronics technology, converters achieve compactness and high power density by increasing switching frequency and reducing passive components. However, this compromises the filtering capability to suppress high-frequency harmonics and intensifies high-frequency resonance issues in multi-machine interconnected systems. The problem becomes even more complex in grid-following (GFL) and grid-forming (GFM) converter interconnected systems due to their distinct dynamic characteristics. Traditional active damping methods fail to effectively mitigate such high-frequency resonances. For GFL converters, this paper investigates the interaction mechanisms between various active damping techniques and high-frequency harmonics, and proposes a virtual-filter-based active damping method that feeds back capacitor voltage through a quasi-resonant controller. This approach effectively suppresses high-frequency resonance, maintains high control bandwidth, and avoids the drawback of conventional capacitor-voltage feedforward, which tends to amplify high-frequency disturbances. For GFL-GFM interconnected systems, the paper further analyzes how different active damping strategies affect system damping characteristics and the interaction between GFL and GFM converters, leading to a rational active damping configuration. The proposed scheme successfully suppresses high-frequency resonance while preserving fast dynamic response, with experimental results confirming its effectiveness and feasibility. Full article

Active distribution networks (ADNs) with high DER penetration require coordinated decisions to ensure voltage security, limit losses, and support low-carbon targets. However, most reconfiguration-centric studies prioritize loss/cost and rarely integrate carbon pricing and emission accounting into a unified framework with verifiable optimality. This study develops a DistFlow-based mixed-integer second-order cone programming (MISOCP) model that co-optimizes feeder reconfiguration and resource active/reactive dispatch under a price-calibrated loss–emission objective. The framework coordinates PV/WT generation, MTs, aggregated PHEVs (V2G), and reactive-support devices (SVCs and switched capacitor banks (CBs)) and is solved by commercial CPLEX to global optimality for the SOCP-relaxed problem. On the IEEE 33-bus feeder, device coordination reduces losses from 0.203 MW to 0.0382 MW (81.18%) and CO₂ emissions from 2.3872 to 0.3433 tCO₂ (85.62%), while reducing operating cost from CNY 354.9357 to CNY 56.6271 (84.05%). Enabling reconfiguration further reduces losses to 0.0205 MW (89.90%), emissions to 0.2580 tCO₂ (89.19%), and operating cost to CNY 37.4677 (89.44%), while keeping voltages within 0.99–1.01 p.u. Relative to device-only operation, reconfiguration yields 46.34% loss reduction, 24.85% emission reduction, and 33.83% operating-cost reduction. The mixed-integer optimality gap is ~10⁻⁷, and the solution quality for the original non-convex model depends on the tightness of the SOCP relaxation, which is numerically tight in the cases we studied. These results show interpretable technical and environmental gains via coordinated dispatch and topology control in radial ADNs at scale. Full article

This paper proposes a novel seven-level switched-capacitor multilevel inverter featuring a shared front-end DC-link structure that achieves triple voltage gain with reduced component count. A distinctive feature of this design is its inherent capacitor voltage self-balancing capability, thereby eliminating the need for complex control algorithms typically associated with multilevel converters. Moreover, the topology demonstrates particularly significant advantages in three-phase implementations, where a single DC source, front-end switching devices, and capacitors can be shared across all phases—thus substantially reducing component count and system complexity compared to conventional designs. Additionally, this paper proposes an improved carrier-based modulation strategy for this topology requiring only a single triangular carrier, along with a systematic method for determining optimal capacitance values. Through detailed comparative assessment against state-of-the-art switched-capacitor seven-level inverters, the superior performance characteristics of the proposed topology are clearly demonstrated. Finally, simulation results under various operating conditions are presented and subsequently validated through experimental testing on a laboratory prototype, confirming the practical viability of the proposed solution. Full article

This article presents the design of a perovskite photovoltaic (PV)-based power management system, which uses a power converter (a four-stage bootstrap charge pump) to boost the output of the solar cell and supply selectable rectified power rails to CMOS image sensor circuit blocks. A perovskite photovoltaic, also known as a perovskite solar cell (PSC) was fabricated in the laboratory. The PSC has an open-circuit voltage of 1.14 V, short-circuit current of 1.24 mA, maximum power of 0.88 mW, and a current density of 20.68 mA/cm² at 62% fill factor. These measured forward scan parameters were closely reproduced with a solar cell simulation model. In a Cadence simulation that used 180 nm CMOS process, the power converter efficiently boosts the maximum output voltage of the PSC from 0.85 V to a rectified 3.7 V. Stage modulation and level shifting enable selectable output rails in the 1.2–3.3 V range to supply the image sensor circuit blocks. Keeping the output capacitance of the power converter much larger than the flying capacitance reduces the ripple voltage to approximately 73 µV, much smaller than the typical 1 mV in several other literatures. Through simulation, this work demonstrates the concept of directly using PSC (to be implemented on an outer ‘packaging’, not on a die) to supply CMOS image sensor power rails, in the same sense as in wearable devices and other consumer devices. This work highlights a path toward self-powered image sensors with improved conversion efficiency, compactness, and adaptability in low-light and variable operating environments. Full article

This work presents a direct conversion transmitter (DCT) for 5G new radio (NR) that eliminates the RF driver by directly feeding a single stage cascode PA through a baseband buffer amplifier and passive up-conversion mixer. The baseband interface uses Class-AB buffers to hold the output capacitor voltage, enabling accurate sampling at the PA input. A mixer switch is selected for minimal on-resistance variation over the required baseband swing. The PA is designed with separate I and Q voltage inputs and a current summing structure. The PA operates at 2.5 V; other blocks use 1.2 V. Post-layout two-tone simulations at 5 GHz indicate 21 dBm output saturation power and −36.1 dBc of IMD3 at 9 dB PBO power while removing the driver to inter stage matching network of a two-stage design. The results validate a compact, driverless architecture for integrated transmitters. Full article

This paper proposes a small-signal model of a DC–DC parallel resonant converter operating in continuous conduction mode based on asymmetric pulse-width modulation (APWM) under light-load conditions. The parallel resonant converter enables soft switching and no-load control over a wide load range because the resonant capacitor is connected in parallel with the load. However, the resonant energy required for soft switching is already sufficient, and the current flowing through the resonant tank is independent of the load magnitude; therefore, as the load decreases, the energy that is not delivered to the load and instead circulates meaninglessly inside the resonant tank increases. This results in conduction loss and reduced efficiency. To address this issue, APWM with a fixed switching frequency is required, which reduces circulating energy and improves efficiency under light-load conditions. Precise small-signal modeling is required to optimize the APWM controller. Unlike PFM or PSFB, APWM includes not only sine components but also DC and cosine components in the control signal due to its asymmetric switching characteristics, and this study proposes a small-signal model that can relatively accurately reflect these multi-harmonic characteristics. The proposed model is derived based on the Extended Describing Function (EDF) concept, and the derived transfer function is useful for systematically analyzing the dynamic characteristics of the APWM-based parallel resonant converter. In addition, it provides information that can systematically analyze the dynamic characteristics of various APWM-based resonant converters and control signals that reflect various harmonic characteristics, and it can be widely applied to future control design and analysis studies. The validity of the model is verified through MATLAB (R2025b) and PLECS (4.7.5) switching-model simulations and experimental results, confirming its high accuracy and practicality. Full article

This study presents a versatile single-phase multilevel inverter designed to accommodate varying input voltages and output levels. Unlike conventional fixed topologies, the proposed design utilizes a unified structure of 13 switches and three capacitors to realize two distinct configurations: a nine-level circuit employing three series-connected single-voltage clamping sets, and a thirteen-level variant utilizing a hybrid of single- and half-voltage clamping sets. A critical advantage of this architecture is its capability to achieve capacitor self-voltage balancing within a single AC cycle, thereby simplifying the control strategy. Verification through PSIM 9.1 simulations and a TI F280025C-based hardware prototype confirms the circuit’s operational effectiveness. Notably, the thirteen-level configuration demonstrates superior performance, achieving a total harmonic distortion (THD) of 1.25% and a peak efficiency of 97.5%, significantly outperforming the 1.43% THD and 94.5% efficiency of the nine-level counterpart. Full article

This paper presents a high-efficiency bidirectional multidevice interleaved SEPIC–ZETA DC–DC converter for electric mobility applications. The proposed converter offers key advantages, including reduced current and voltage ripple at both the input and output ports, achieved through a port ripple frequency six times higher than the switching frequency. Additionally, the required magnetic and capacitor volume is significantly reduced due to an inductor ripple frequency twice the switching frequency, leading to minimized power losses, reduced stress on power components, and enhanced efficiency. The use of a multidevice structure facilitates more efficient inductor volume optimization and provides improved fault redundancy. The converter is particularly suited for electric vehicle energy management systems, enabling efficient energy management among the various subsystems. It operates in open-loop mode, and this manuscript details the steady-state operating principle under continuous conduction mode. Design guidelines for parameter selection, comprehensive mathematical derivations, and a comparative analysis with existing DC-DC converters are presented. To validate the proposed topology, a 5 kW laboratory prototype was developed and tested across a wide range of load conditions. The experimental results confirm the converter’s high performance, achieving a peak efficiency of 98.6% at rated power. Full article

This paper proposes a single-phase AC-AC solid-state transformer (SST) that eliminates bulky energy storage components. The proposed matrix-type structure comprises a line-frequency (LF) rectifier, a half-bridge (HB) LLC resonant converter, a buck–boost converter, and an LF inverter. The HB LLC resonant converter not only achieves high efficiency at unity voltage gain but also provides high-frequency (HF) isolation as a DC transformer (DCX). Meanwhile, the buck–boost converter ensures precise voltage regulation. The replacement of traditional DC-link electrolytic capacitors with small film capacitors effectively suppresses the second-harmonic power ripple, leading to a significant improvement in both power density and operational reliability. Experimental results from a 1 kW prototype demonstrate high-quality sinusoidal input and output, a wide range of zero-voltage switching (ZVS) operations, and stable output voltage control. Full article

This paper proposes a coordinated hybrid VAR compensation strategy that leverages the dynamic support capabilities of a grid-forming (GFM) battery energy storage system (BESS) and solar photovoltaic (PV) plant to enhance the stability of inverter-dominated power systems. The hybrid compensator integrates a VSC-based static synchronous compensator (STATCOM) with a thyristor-switched capacitor (TSC), combining the fast dynamic response of the STATCOM with the high reactive power capacity of the TSC. A coordinated control framework is developed to enable seamless interaction between the hybrid VAR compensator and the GFM-controlled PV and BESS units, ensuring improved voltage regulation and transient stability under varying operating conditions. The PV plant operates at maximum power Point while maintaining its grid-forming capability, thereby maximizing renewable energy utilization while contributing to frequency and voltage support. The effectiveness of the proposed strategy is validated through FPGA-based real-time simulations under scenarios including large load variations, solar irradiance fluctuations, and grid disturbances. Results show that the coordinated operation enhances voltage stability, strengthens reactive power support, mitigates low-frequency oscillations, and significantly improves the dynamic performance of low-inertia, inverter-dominated grids. Full article

This paper introduces a novel stochastic optimization framework for the optimal sizing of thyristor-switched capacitors (TSCs) in medium-voltage distribution networks. Unlike conventional deterministic approaches, the proposed model explicitly incorporates load demand variability through multiple probabilistic scenarios, thereby enhancing the robustness and reliability of reactive power compensation. The methodology employs advanced nonlinear programming techniques, i.e., the IPOPT solver within a scenario-based framework, in order to determine the TSC sizes that minimize the expected total system costs, including those associated with energy losses and investments. According to extensive simulations on a standard 33-bus distribution system, our stochastic approach yields cost savings of approximately 12.3–12.4% while significantly improving voltage stability and operational efficiency under various load conditions. Assessments regarding voltage profile performance and average processing times, as well as a comparative analysis considering deterministic results, were also conducted in order to validate the effectiveness and computational efficiency of the approach. This study underscores the importance of probabilistic modeling for a smarter, more resilient grid operation, laying a solid foundation for integrating adaptive reactive power devices to support sustainable and reliable power distribution in evolving smart grid environments. Full article

Computational analysis using PSpice has become an indispensable tool for evaluating power electronics circuits, as it allows accurate simulation of transient effects, ripple, and component dynamics, enabling reliable assessment of complex topologies before physical implementation. In single-phase systems, electrolytic components are commonly used due to their high energy density, which helps mitigate low-frequency ripple caused by power oscillations between the DC and AC sides. However, these components have a limited lifespan, which compromises the system’s long-term reliability. This work proposes and evaluates the Stacked Switched Capacitor (SSC) topology as a power decoupling technique, implemented within a 200 W Cuk converter. The proposed SSC design enables a substantial reduction in required capacitance, replacing a conventional 600 μF capacitor with only three 36 μF capacitors, while maintaining voltage stability and output power performance. Simulation results show a high efficiency of 94% and a DC-link energy of 0.992 J, confirming the SSC’s ability to effectively mitigate voltage ripple at twice the grid angular frequency (2ω, rad/s) without compromising system durability. Comparative analysis with conventional decoupling strategies demonstrates that the SSC topology offers a compact, efficient, and reliable alternative, reducing the number of required passive components and switching devices. These results provide a strong basis for further exploration of SSC-based designs in space- and cost-constrained single-phase DC-AC applications. Full article