Perovskite PV-Based Power Management System for CMOS Image Sensor Applications

Abstract

This article presents the design of a perovskite photovoltaic (PV)-based power management system, which uses a power converter (a four-stage bootstrap charge pump) to boost the output of the solar cell and supply selectable rectified power rails to CMOS image sensor circuit blocks. A perovskite photovoltaic, also known as a perovskite solar cell (PSC) was fabricated in the laboratory. The PSC has an open-circuit voltage of 1.14 V, short-circuit current of 1.24 mA, maximum power of 0.88 mW, and a current density of 20.68 mA/cm² at 62% fill factor. These measured forward scan parameters were closely reproduced with a solar cell simulation model. In a Cadence simulation that used 180 nm CMOS process, the power converter efficiently boosts the maximum output voltage of the PSC from 0.85 V to a rectified 3.7 V. Stage modulation and level shifting enable selectable output rails in the 1.2–3.3 V range to supply the image sensor circuit blocks. Keeping the output capacitance of the power converter much larger than the flying capacitance reduces the ripple voltage to approximately 73 µV, much smaller than the typical 1 mV in several other literatures. Through simulation, this work demonstrates the concept of directly using PSC (to be implemented on an outer ‘packaging’, not on a die) to supply CMOS image sensor power rails, in the same sense as in wearable devices and other consumer devices. This work highlights a path toward self-powered image sensors with improved conversion efficiency, compactness, and adaptability in low-light and variable operating environments.

1. Introduction

The growing demand for low-power vision sensors, especially in autonomous systems, has driven research into energy-efficient vision systems that combine renewable energy harvesting with efficient on-chip power management. Due to its widespread commercial use, complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are at the heart of said research. However, the CIS often requires supply voltages higher than those sourced from ambient energy harvesters. Therefore, power conversion and regulation stages are essential to boost and stabilize the harvested energy to power rails suited to the operation of CIS circuit blocks. When it comes to energy harvesting, perovskite solar cells (PSCs) show a lot of promise, offering a high absorption coefficient, tunable bandgap, and rising power conversion efficiencies (PCEs). Additionally, they can be fabricated on flexible, lightweight substrates, making them attractive for wearable and embedded devices, as well as for autonomous energy-independent systems. The PSC’s open-circuit voltage, $V_{oc}$, depends on the absorber bandgap, material composition, and whether the device is single-junction or tandem. The typical open-circuit voltage of a single-junction lead-halide PSC unit is in the 0.7–1.2 V range, and in the 1.8–2.2 V range for tandem devices [1]. Additionally, the typical maximum power point voltage, $V_{mpp}$, for the former is 0.7–0.95 V and 1.4–1.6 V for the latter [1]. While the tandem device can obviously generate more voltage, it takes up more area, in comparison to a single PSC. These referenced voltage rails are insufficient to drive the analog and digital circuit blocks of a CMOS image sensor that often require bias and rail voltages that range from 1.2 to 5 V.

This work proposes a power management system (PMS) that comprises a perovskite solar cell (fabricated on a 20 mm × 20 mm × 1 mm glass substrate), which generates the supply rail to a power converter (four-stage bootstrap charge pump, BCP) and stage modulation circuit blocks, that in turn supply the power rails needed by all the CIS circuit blocks. It follows that devices grown on bigger substrates produce more energy upon illumination and can support higher energy needs. An equivalent circuit that tracks the electrical characteristics of the PSC is designed and used as the input rail while simulating the power management system in Cadence Virtuoso. Compared to conventional Dickson Charge Pumps (DCP), bootstrap charge pumps reduce threshold voltage losses and improve transfer efficiency, particularly at low voltages. The proposed system uses 180 nm CMOS technology and flying capacitors of 35.6 fF per stage, boosting the input voltage (from the solar cell model) from 0.85 V up to 3.7 V. Additionally, the PMS also adopts rectification and noise-reduction methods. It also addresses output ripple voltage, which has a bearing on power efficiency. Simulation results show a peak efficiency of 86.83% at a load current of 1.2 µA.

With the growing efficiency of PSCs, researchers have begun to rely more on them as the power source in many wearable electronics [2], biometric sensors [3,4] and environmental sensors [5]. CMOS image sensor research which adopt different perovskite photodiodes (PePD) with silicon read-out integrated circuit (ROIC), instead of the typical silicon photodetectors, is also gaining ground [6,7,8,9]. This work is about using a PSC as a dedicated energy source to drive CMOS image sensor circuit blocks. A review of literature in this research theme shows multi-mode CMOS image sensors that operate in energy harvesting (EH) and imaging modes (IM) using the same silicon photodetector arrays [10,11]; as well as systems that use a combination of dedicated energy harvesting and multi-mode photodetector arrays [12]. In [13,14], researchers employed reconfigurable photodetectors and a flying-inductor DC-DC converter in a 0.5 µm CMOS process to generate up to 3.9 V for CMOS image sensor blocks. While it is true that using photodetectors in multimode is area-efficient, extra energy is spent on mode-switching, especially in event-driven imagers. Furthermore, while in EH mode, the photodetectors used in EH are unavailable for image capture, negatively impacting image resolution. Yadid-Pecht et al. [15] tried to solve this problem by introducing a separate power-generating diode (PGD) in-pixel, with resulting negative impacts on the pixel area and reset voltage [13]. The use of switched-inductor power converters in [13,14] has the obvious disadvantage of bulky inductors, which are difficult to integrate on-chip.

While it is impractical to integrate dedicated crystalline solar cells and silicon circuitry on-chip, thin-film solar cells provide a workaround. Performed through simulation, the proposed system is a proof of concept in using perovskite solar cells (to be implemented on a CIS ‘packaging’), to drive CMOS image sensor circuit blocks, in the same way as in SC-powered wearable devices, consumer devices (like calculators and some smart TV remote controls) and sensors. This will eliminate the need for mode switching and loss in image resolution in dual-mode energy harvesting imagers. In the proposed system, the PSC feeds into a fully integrated switched capacitor power converter to boost the PSC’s output to higher rails. Our design employs small flying capacitors in its power converter. Despite the advantages of a BCP, it has the drawback of requiring non-simple clocking and more area for the bootstrap stages. Whereas this work presents a more area-efficient design, with 35 fF and 5 pF flying and output capacitors, respectively, Alenin et al. [16] used 50 pF and 100 pF, respectively, whereas Vanselow et al. [17] used 56 pF. Furthermore, Das et al. have 40 pF and 80 pF capacitors in their design [18], 10 pF is used in [19], whereas Yi et al. [20] have huge nF off-chip capacitors. Use of level shifters and delay elements made a single clock signal ‘reuse’ feasible. The proposed system has a robust, flexible and tunable current-starved voltage-controlled oscillator (VCO) for clock signal generation. This is better compared to the single frequency of the typical ring oscillator. Additionally, although the design of the proposed system is not fully adaptive in stage modulation, it is capable of supplying 1.2–3.3 V voltage rails through a transmission gate-based multiplexer to different circuit blocks in an image sensor. The large output capacitance of the charge pump, relative to the flying capacitors, reduces the ripple voltage in the voltage rails, from the typical 1 mV [16,20] to about 72 µV, with a leakage current of about 6 pA.

Figure 1 below shows the concept of the proposed PMS. A PSC traps energy from the sun or ambient sources. The trapped energy becomes the input into a charge pump that is subsequently boosted by a power converter. The boosted voltage rails at the four stages of the charge pump are then rectified, with a provision to select a desired number of charge pump stages using external select bits in the stage modulation circuitry. The remainder of the article is arranged as follows: Section 1.1 and Section 1.2 provide some background on charge pumps and solar cell models, while Section 2 deals with design specifications of the proposed system. Whereas Section 3 delves into the research method, Section 4 discusses the results obtained. The paper ends with drawn conclusions in Section 5.

1.1. Theoretical Framework-Solar Cell Models

Two regimes exist for the photovoltaic cell modeling, namely: static and dynamic modes [21]. Typically, a capacitor in parallel with a p-n junction diode is used to model dynamic behavior. With each generation of solar cell, as well as the mode and base material, the characteristics, as well as the equivalent circuit of the solar cell, vary. Accurate design and analysis require the use of the proper model in the appropriate situation.

Since SCs generate current independent of the load connected to them, they are generally modeled as current sources. The current generated by the cells, however, is dependent on the intensity of the incident light falling on the PV. Other factors like the exposed surface area of the photo-sensitive material used, as well as its quantum efficiency, are non-varying, post-process. As in a diode, leakage currents, resulting from the SC voltage, are known to flow under dark conditions. Additionally, the generated current under illumination impacts the diode characteristics at the terminal. It makes sense, therefore, to include the diode in the equivalent circuit of the solar cell. Other effects, such as voltage drop, current loss, and carrier recombination, are modeled using circuit components like resistors and current sources [21].

In the discussion on solar cell models above, quantities/effects encountered in an SC are modeled using circuit components in a brick-by-brick, bottom-up approach. A fuller, more accurate and regularly encountered equivalent circuit begins to take shape and increasingly accounts for more of the effects of significance from Figure 2c. Finally, a justification for the choice of the simulation model is provided, out of the examined options.

A solar cell is often modeled as a current source. When illuminated, photo-generated electrons move to the terminals under the influence of an applied potential. To represent the current-voltage (I-V) characteristics, a forward-biased diode D is placed in parallel with the (photo) current source, $I_{ph}$ [21]. The current I delivered at its output comprises the photocurrent and the diode’s dark current $I_D$. This model, shown in Figure 2a above, does not account for potential drops in SCs. As shown in Figure 2b, the series resistance $R_s$ accounts for the voltage drop in the solar cell and shows the relationship between the solar cell’s maximum power and open-circuit voltage [21,22]. A resistor in parallel with the dark current diode, as in Figure 2c, can be used to model current leakages around the SC’s edges, as well as the diffusion paths along dislocations and the small internal short circuits [21,23]. In Figure 2d, which considers current losses, voltage drops, and carrier recombination, $D_1$ represents the diffusion current, while $D_2$ represents generation-recombination in the depletion region. However, the recombination current $I_{D2}$ is usually very small in wafer-based silicon cells, which is why this model is not widely used, especially since most solar cells on the market are silicon-based [23]. For thin film solar cells shown in Figure 2e, aging begins right after fabrication and reduces the cell’s power as carriers recombine in degraded charge-space layers. To model this, Figure 2e adds another current source to the circuit of Figure 2c. The extra recombination current, $I_{recomb}$, increases with the photo-generated current and the cell’s thickness, but decreases as the drift length increases.

The focus of this work is PSCs, which are thin-film solar cells. The SC model in Figure 2e is adopted for our simulation of the power management system.

1.2. Theoretical Framework-Charge Pumps

1.2.1. Charge Pump Operation

A charge pump (CP) is a DC–DC converter that uses only capacitors and switches (usually MOSFETs) to raise, lower, or invert a supply voltage. Because it does not use an inductor, it is preferred for fully integrated circuits.

Figure 3 shows an N-stage charge pump, the result of cascading N pumping stages. From the diagram and as it pertains to the proposed system, $V_{in}$ is the output of the solar cell. $S_1-S_N$ are stage switches, typically MOSFETs, in modern designs. The literature on CPs has a variety of switch configurations [24,25,26], motivated by the need to improve output voltage rail, switch efficiency and reduce leakage. A tradeoff between switch configuration and the adopted topology’s performance in terms of efficiency and leakage plays a major role in determining the choice of the CP switch.

In its most basic form, the CP needs two non-overlapping clocks, ${\Phi }_1$ and ${\Phi }_2$ in Figure 3. More advanced or complex CP topologies like the bootstrap and double charge pumps [27] or interleaved charge pumps [28] need up to four non-overlapping clock pulses with different phases and amplitudes. In Figure 3 and in the first clock half cycle, only ${\Phi }_1$ is low, closing only the odd-numbered stages. $C_1$ charges to $V_{in}$ while the capacitors in the other odd stages receive charge from the flying capacitors in the preceding stage. In the next half cycle, ${\Phi }_1$ is high and ${\Phi }_2$ is low, enabling the capacitors in the even stages to receive charge from the capacitors in the odd stages.

The relationship between the flying capacitors ($C_{fly}$) in the intermediate stages (1 to N) and the load $C_L$, which draws an output current $I_L$, is described by Equation (1) below. The load or output capacitor, $C_L$ plays a major role in reducing the ripples in the CP’s output. The bigger the $C_L$ (within design constraints), and the smaller the ripples. A value much larger than the flying capacitor value is recommended [24,25,26,27].

$$Load capacitor,C_L\gg Flying capacitor,C_{fly},$$

(1)

According to Palumbo et al. [27], the output voltage $V_{out}$, of an N-stage charge pump is given by Equation (2) below. The term on the right represents the losses in the CP.

$$V_{out}=V_{in}\left(N+1\right)-N{\displaystyle \frac{I_L.T}{C_{fly}}},$$

(2)

Once a flying capacitor is charged and then connected to the supply or the previous stage, it sends a set amount of current to the output. Between these transfers, the load continues to draw current, causing the output voltage to drop slightly until the next transfer occurs. This cycle of charging and discharging creates a voltage ripple $V_r$. Factors that influence a CP’s ripple voltage include load current, flying capacitance, clock frequency and parasitic resistances and capacitances. Higher load currents and the presence of parasitics cause bigger ripple voltages, while a faster clock frequency reduces their effect. Ripples in a CP’s output are undesirable. The smaller the better. Ripple voltage, $V_r$ is described mathematical by Equation (3) [27]:

$$V_r={\displaystyle \frac{I_L.T}{C_{fly}}},$$

(3)

1.2.2. Charge Pump Topologies

The proposed solution in this work uses a bootstrap charge pump (BCP), see Figure 4a, for power conversion. With the same number of stages (i.e., 1 to N in Figure 4a, or 1* to N* in Figure 4b), input voltage, clock frequency, flying and output capacitance as well as transistor dimensions, the advantage of the BCP over the regular Dickson Charge Pump (DCP) in Figure 3, lies in the BCP’s lower ripple voltage, higher voltage transfer efficiency (higher output voltage), and better performance at low supply voltages due to lower $V_{th}$ loss in the BCP compared to the regular DCP [29]. The double bootstrap charge pump topology (DBCP), see Figure 4b, has the additional advantage of reduced switch on-resistance, further minimization of threshold voltage loss, even higher achievable output voltage for the same number of stages as the BCP, and better current drive under resistive load [30]. The downside is that the topology takes up more area for the additional transistors and capacitors.

2. System Design

2.1. Solar Cell

The PSC used in this work is of the form ${ABX}_3,$ where A is a monovalent organic cation (i.e., ${\mathrm{N}\mathrm{H}}_3{\mathrm{C}\mathrm{H}}_3^{+}$), B is metal cation (i.e., Pb III or Sn II), and X is a halide (${\mathrm{C}\mathrm{l}}^{-}\mathrm{o}\mathrm{r} {\mathrm{I}}^{-}$). A glass substrate of dimensions 20 mm × 20 mm × 1 mm is used to grow the thin film. Figure 5 shows the layers of the PSC in 3D as well as the scanning electron micrograph of the fabricated cell. Aidarkhanov et al. [31] describes the fabrication method adopted for the PSC used in this work. This fabrication method is documented in the supplementary material (also [32,33]). Pylnev et al. [34] and Wen et al. [35] detail recent methods of improving the power conversion efficiency of PSCs.

In Figure 5a, FTO stands for Fluorine-doped Tin-Oxide (FTO), while NP and QD stand for nanoparticles and quantum dots, respectively; these are electron transport layers (ETL). PMMA:PCBM represents a mixture of poly (methyl methacrylate) (PMMA) with [6,6]-phenyl C61 butyric acid methyl ester (PCBM), used to create interfacial layers to enhance the performance and stability of the solar cell devices. Lastly, Spiro-MeOTAD is an abbreviation for the organic compound 2,2′,7,7′-Tetrakis (N,N-di-p-methoxyphenylamine)-9,9′-spirobifluorene. It is a widely used hole transport material (HTM), which is a crucial component for high-performance devices.

Figure 5b shows the cross-section of the PSC as seen through a scanning electron microscope (SEM) at a magnification of 100 nm, while Figure 6 shows the PSC’s J-V characteristic curve, with a current density of 20.68 $\mathrm{m}\mathrm{A}/{\mathrm{c}\mathrm{m}}^2$ in the forward scan and 20.61 $\mathrm{m}\mathrm{A}/{\mathrm{c}\mathrm{m}}^2$ in the reverse scan. Data for the J-V plot is obtained by irradiating the fabricated PSC in the laboratory and taking measurements.

Table 1. Measured perovskite solar cell electrical properties in forward and reverse scans.

Parameter	Reverse Scan	Forward Scan
Open Circuit Voltage, $V_{OC} \left(\mathrm{V}\right)$	1.14	1.14
Short Circuit Current, $I_{SC} \left(\mathrm{m}\mathrm{A}\right)$	1.24	1.24
Current Density, $J_{SC} (\mathrm{m}\mathrm{A}/{\mathrm{c}\mathrm{m}}^2)$	20.61	20.68
Maximum Current, $I_{max} \left(\mathrm{m}\mathrm{A}\right)$	0.99	1.04
Maximum Voltage, $V_{max} \left(\mathrm{V}\right)$	0.83	0.85
Maximum Power, $P_{max} \left(\mathrm{m}\mathrm{W}\right)$	0.82	0.88
Fill Factor (%)	58.13	62.22
Efficiency (%)	13.64	14.63

outlines the electrical properties of the grown device. The effect of hysteresis (differing electrical properties in forward and reverse scan) is observed, but mild. The forward scan values are used in simulating the PMS. After fabrication, the PSC is always carefully placed in an air-tight container with silica crystals to keep moisture away and forestall degradation, between characterization stations.

The stability characterizations under maximum power point tracking were performed using the PAS-GV photovoltaics aging system from Enli Tech, Taiwan. The system was installed inside the nitrogen-filled glove box. The IV measurements were performed with an interval of two minutes, and between measurements, the samples were kept under constant 1-sun illumination and $V_{mpp}$ bias, whose value was extracted from the last I-V measurement.

2.2. Power Converter

Section 1.2 covers charge pump operation and topologies and highlights the theoretical advantages of the DBCP over the BCP. However, to justify the choice of either topology, a comparison is made under the same conditions of input voltage, flying and output capacitance, switch type (charge transfer device) and clocking, through simulation.

In the design of a DBCP, Palumbo et al. [27] seem to suggest that the size of the flying capacitors should be half of their value in the BCP topology. However, doing this erases the inherent advantages of the DBCP, and at least doubles the ripple voltage, according to Equation (3).

Table 2. Comparison of BCP and DBCP power converters.

Topology	Output Voltage, ${\mathit{V}}_{\mathit{o}\mathit{u}\mathit{t}} \left(\mathbf{V}\right)$	Output Current, ${\mathit{I}}_{\mathit{o}\mathit{u}\mathit{t}} \left(\mathbf{m}\mathbf{A}\right)$	Ripple Voltage, ${\mathit{V}}_{\mathit{r}} \left(\mathbf{\mu }\mathbf{V}\right)$	Leakage Current, ${\mathit{I}}_{\mathit{l}\mathit{e}\mathit{a}\mathit{k}} \left(\mathbf{p}\mathbf{A}\right)$
BCP	3.713	1.273	72.735	6.695
DBCP	3.711	1.581	57.009	13.099

records the output voltage, load current and ripple voltage of the BCP and DBCP, obtained through simulation. Note from this table that both topologies have nearly identical output voltages of approximately 3.71 V, but the DBCP has marginally better load current and ripple voltage performance. With regard to leakage current, the DBCP has about twice the leakage current of the BCP. While double the leakage current is expected, given that the DBCP has almost twice the number of switches in the BCP, it is the authors’ opinion that the marginally better load and ripple currents of the DBCP do not justify the twofold increase in component count (power converter area) and twice leakage current. Hence, a BCP is used in this work.

To extract the data in Table 2, both topologies are simulated under the same conditions, i.e., both have four stages, 0.85 V input voltage, 35.6 fF and 5 pF flying and output capacitance, respectively, a 6.67 MHz clock, and the same charge transfer switch device.

To measure leakage in both power converters, once the CP reaches steady state voltage (at ≈ 400 µs), the clocks are turned off, so that the output leaks through the devices in the CP. The change in output voltage over time is measured over a short time frame, i.e., at t = 450 µs, then at t = 550 µs. Leakage current is then calculated using Equation (4).

$$I_{leak}=C_{out}\times {\displaystyle \frac{dV}{dt}},$$

(4)

Notice from the insets in Figure 7, the difference in leakage current between the BCP and DBCP. Using equation four within the chosen time frame, and data from the simulation, the calculated results confirm that the DBCP has more leakage current.

2.3. Clock Generator: Current-Starved Voltage-Controlled Oscillator

A current-starved voltage-controlled oscillator (VCO) is widely used in CMOS design. It is especially common in low-power and fully integrated applications, such as phase-locked loops (PLLs), frequency synthesizers, and clock generation circuits. In this topology, frequency is controlled by limiting the current available to the delay elements of a ring oscillator. Starving the current directly regulates the charging and discharging rates of the capacitive nodes, which in turn controls the oscillation frequency [36].

This basic structure of a current-starved VCO uses a ring oscillator. This oscillator consists of an odd number of inverters connected in a loop to sustain oscillation. Each inverter stage is starved of current by an added NMOS and PMOS transistor pair. These act as current sources or current-limiters. The transistors are controlled by a bias voltage ($V_{ctrl}$) applied to $M_5$. When $V_{ctrl}$ increases, more current flows through the limiting transistors. The inverter’s load capacitance then charges and discharges faster. This shortens the delay per stage and increases oscillation frequency. Lowering $V_{ctrl}$ reduces the available current. This lengthens the delay and decreases the oscillation frequency [37]. Additionally, it allows for a wide tuning range and makes the design useful in situations where flexibility is important. On the other hand, this approach has some drawbacks. It tends to have higher phase noise than LC oscillators because noise from the current sources and delay cells leads to timing jitter.

This work uses a current-starved voltage-controlled oscillator (VCO) shown in Figure 8a to generate clock signals. A level shifter is used to achieve the required $2V_{in}$ clock amplitude from a $V_{in}$ input. The 4-phase clock signals generated using the designed VCO are as shown in Figure 8b above. The connections of the clocks F1, F2, FB1, and FB2 are as shown in Figure 4a.

2.4. Transmission Gate (TG)-Based 4:1 Multiplexer

Stage modulation in this work is achieved using a TG-based 4:1 multiplexer (MUX). The multiplexer is shown in Figure 9b, while Figure 9a describes the transmission gate.

A transmission gate (TG) consists of an NMOS and a PMOS transistor in parallel (see Figure 9a). The NMOS conducts well near ground, but struggles to pass a strong logic ‘1′ due to threshold voltage drop. The PMOS conducts well near VDD, but has difficulty near ground. Pairing them in parallel and driving their gates with complementary control signals enables full-rail signal transfer from 0 to VDD with low resistance. This property makes the transmission gate ideal for selecting analog signals. The output of a transmission-gate design can carry not only analog signals but also logic values. For example, it can pass the intermediate boosted voltages in a charge pump. This flexibility surpasses a multiplexer built with standard CMOS logic gates only, which would clip or distort analog signals. The truth table of the MUX is shown in

Table 3. Truth table of a TG-based MUX.

Select 1 (S1)	Select 0 (S0)	Selected Output
0	0	A0
0	1	A1
1	0	A2
1	1	A3

.

The proposed power management system supplies a CMOS image sensor. This power management solution is capable of providing the supply rails required by different parts of an image sensor, typically 1.2–3.3 V.

Table 4. CMOS image sensor circuit blocks and associated voltage ratings.

Circuit Block	Typical Voltage Rating (V)
Image sensor active pixel array	2.8–3.3
Image sensor analog circuitry (CDS/column amplifiers)
ADC (peripheral/column-parallel)-Analog
Digital control/sequencer	1.2–1.8
Timing generator/clock driver	1.8–3.3
Voltage references/on-chip regulators	1.2/1.8/2.8/3.3
Image Signal Processor (ISP) if integrated	1.2–1.8

shows representative circuit blocks in a CMOS image sensor and their voltage requirements. Note that the voltage required by these circuit blocks is in the 1.2–3.3 V range, which would be provided using the stages of the proposed power management circuit in tandem with level shifters (up or down) to deliver a clean rectified supply at minimal ripple voltage.

Image sensor circuit blocks, like the lens actuator/autofocus driver (supply voltage range: 2.8–5.0 V) and the flash LED driver at system-level (supply voltage range: 3.3–5.0 V) not listed on Table 4. Their voltage requirement exceeds what the MOSFET devices in the proposed system can reliably handle. The object of this block in the proposed system is to deliver 1.2–3.3 V to the circuit blocks in the CMOS image sensor in Table 4.

3. Method

Using the electrical characterization data for the PSC in Table 1 and the equivalent circuit model in Figure 2e, a DC simulation is designed to validate the suitability of the chosen model to reproduce the electrical characteristics of the fabricated thin-film solar cell device. It is observed that the chosen model emulates the PSC with fidelity. This is performed by comparing Table 1 to Figure 10 below. The open circuit voltage, short circuit current and maximum power point are identical. It follows that the simulated model is equivalent to the fabricated PSC.

The output of this simulation model is coupled to the input of the power converter. The BCP is able to generate up to 3.71 V at 1.24 µA from a 0.85 V input voltage, with much smaller 72.74 µV ripples in the output.

With the MUX, it is feasible to select the desired number of stages to supply a required rail (1.2–3.3 V) to a desired image sensor block, using the select pins. The selected stage (s) then undergoes rectification at the end of the stage modulation block, to remove/reduce ripples and supply a clean DC rail.

4. Results and Discussion

Using data from Table 1 and the SC model of Figure 2e, an SC is designed and simulated to reproduce the electrical properties of the fabricated device. The I-V and P-V curves of the SC model are shown in Figure 10 above. Note that the electrical characteristics of the model (especially $I_{sc},V_{oc},V_{mpp}$) tracks that of the actual thin film device, from Table 1. The output of the SC simulation model feeds into the BCP for boosting. This step is followed by the stage modulation block, wherein the TG-based MUX can select the number of CP stages and connect to CIS circuit blocks as appropriate, using external select inputs. Depending on the supply need, the MUX connects a stage, through a level shifter, to the output capacitor, which rectifies the rail and presents its output to drive a load.

The BCP boosts the 0.85 V ($V_{max}$) input from the PSC model up to 3.71 V. Figure 11 captures the boost operation of the power converter and the voltage at the intermediate CP stages. A clean $V_{out}$ = 3.71 V is clearly seen with a relatively very tiny ripple voltage. The charge pump is run until its output stabilizes. At steady state, the first stage of the charge pumps rails between 0.85 and 1.52 V, the second stage from 1.52 to 2.22 V, the third stage from 2.22 to 2.96 V, while the fourth stage rails between 2.96 and 3.71 V, as shown in Figure 11. Additionally, the ripple voltage in the output is shown to be 0.73 µV in the same figure.

Figure 11 also illustrates the stage modulation scenario where both select pins are high, connecting the fourth stage of the CP to the output, in line with the MUX truth table in Table 3. Similar clean output voltages, the size of the maximum positive swing of the node (or level shifter) is observed when each of the other nodes is connected to the output through the MUX. Rectification is basic, and with the use of a large output capacitor.

The clocks driving the flying and bootstrap capacitors are not shown in Figure 11 because the individual clock cycles cannot be distinguished when the clock cycles are displayed for the entire 350 µs of the charge pump operation. Instead, a few cycles of the clocks used are shown in Figure 8b. Insets of the steady state node voltages (N1–N4) and output voltage, $V_{out}$, are shown to clearly describe the behavior.

5. Conclusions

In this work, a perovskite PV-based PMS that uses a power conversion block, stage modulation, and level-shifting for the supply of selectable rectified power rails to CMOS image sensor circuit blocks was presented. Using laboratory-fabricated PSC and a validated thin-film solar cell model, a four-stage bootstrap charge pump implemented in 180 nm CMOS technology, efficiently boosts a low input voltage of 0.85 V to a rectified output of up to 3.7 V. Stage modulation, level shifting and transmission-gate multiplexing enable the generation of selectable 1.2–3.3 V rails suitable for diverse CIS circuit blocks, while maintaining ultra-low ripple voltage (~73 µ). Simulation results showed peak conversion efficiency of 86.83% at 1.24 µA load current, outperforming comparable switched-capacitor designs in ripple voltage and area efficiency. This work highlights a path toward self-powered image sensors with improved conversion efficiency, compactness, and adaptability in low-light and variable operating environments.