Computational Analysis of Unipolar Stacked Switched Capacitor Architecture for Active Power Decoupling in Single-Phase Systems

Abstract

Computational analysis using PSpice has become an indispensable tool for evaluating power electronics circuits, as it allows accurate simulation of transient effects, ripple, and component dynamics, enabling reliable assessment of complex topologies before physical implementation. In single-phase systems, electrolytic components are commonly used due to their high energy density, which helps mitigate low-frequency ripple caused by power oscillations between the DC and AC sides. However, these components have a limited lifespan, which compromises the system’s long-term reliability. This work proposes and evaluates the Stacked Switched Capacitor (SSC) topology as a power decoupling technique, implemented within a 200 W Cuk converter. The proposed SSC design enables a substantial reduction in required capacitance, replacing a conventional 600 μF capacitor with only three 36 μF capacitors, while maintaining voltage stability and output power performance. Simulation results show a high efficiency of 94% and a DC-link energy of 0.992 J, confirming the SSC’s ability to effectively mitigate voltage ripple at twice the grid angular frequency (2ω, rad/s) without compromising system durability. Comparative analysis with conventional decoupling strategies demonstrates that the SSC topology offers a compact, efficient, and reliable alternative, reducing the number of required passive components and switching devices. These results provide a strong basis for further exploration of SSC-based designs in space- and cost-constrained single-phase DC-AC applications.

1. Introduction

Electrolytic capacitors are essential in power conversion applications due to their high energy density. However, despite their widespread use, these devices face significant challenges that limit their reliability and lifespan. One of the most critical issues is the degradation of the electrolyte, which is the primary factor determining their performance [1]. Over time, the electrolyte evaporates, leading to an increase in Equivalent Series Resistance (ESR) and a decrease in capacitance, directly affecting the efficiency of the systems. ESR, in particular, generates heat in the capacitor, which can result in excessive heating and a reduced component lifespan, especially in high-power or high-frequency applications [2].

Despite advancements in materials and electrolytes, such as solid electrolytes and improved dielectrics, electrolytic capacitors still need to be aware of these issues. Operating temperature, thermal and electrical stress, and extreme usage conditions continue to be critical factors contributing to the degradation of these devices. For example, temperature directly impacts the lifespan of capacitors, with each 10 °C increase halving their durability [3]. Furthermore, overvoltage and manufacturing defects can accelerate aging and premature failure of capacitors.

In this context, stacked switched capacitors (SSC) emerge as an innovative solution to enhance power conversion systems’ reliability and energy density. This technique involves stacking multiple capacitors in a switched configuration, distributing the electrical and thermal stress across several elements, reducing the risk of premature failure, and extending the system’s lifespan [4]. Switching between capacitors also allows some capacitors to be deactivated while others operate, which improves overall reliability and minimizes the effects of localized degradation in a specific capacitor [5].

Although implementing the SSC architecture may increase system complexity and cost, its ability to enhance reliability and optimize energy density makes it a promising option for critical applications, such as power electronics and systems operating at high temperatures [6]. Through switching, the load can be balanced between capacitors, ensuring consistent and reliable performance, regardless of the technology or material used in the capacitors.

This article examines how the SSC architecture can overcome the inherent issues of traditional electrolytic capacitors while providing a more robust and efficient solution for energy applications. It demonstrates that, regardless of the capacitor material, the stacked switched architecture improves energy density and system reliability overall.

In the early stages of capacitor development, the materials available were limited, and liquid electrolytes were the standard choice for most electrolytic capacitors [7]. However, over time, advancements in materials science have enabled improvements in capacitor properties, addressing some of the most significant issues related to aging, reliability, and energy density [8].

• Electrode materials: Traditional electrolytic capacitors typically use aluminum or tantalum oxide as dielectric materials, which are prone to degradation over time due to gas bubble formation or electrolyte evaporation. In recent years, new dielectric materials such as multilayer ceramic films (BaTiO₃, SrTiO₃) and polymer-based dielectrics (polypropylene, polyethylene naphthalate) have been explored to enhance reliability and thermal performance [9,10]. These alternatives exhibit higher breakdown voltages and improved thermal stability than liquid-based electrolytes, thereby extending the operational lifespan of capacitors in high-temperature applications.
• Solid and polymer electrolytes: Solid-polymer capacitors, particularly those employing polythiophene (PEDOT) and polypyrrole (PPy) electrolytes, have attracted increasing attention. Unlike traditional liquid electrolytes, these solid-state materials eliminate evaporation and leakage issues, resulting in longer lifetime and lower equivalent series resistance (ESR) [11]. Furthermore, the enhanced ionic conductivity of polymer electrolytes enables higher efficiency in circuits with large ripple currents, making them suitable for compact and high-frequency power converters [12].
• New electrolytes: The development of hybrid and non-liquid electrolytes, including niobium oxide, tantalum oxide, and conductive polymer composites, has become a key area of research in advanced capacitor design [13]. These materials combine the stability of solid dielectrics with the high capacitance of electrolytic systems, significantly reducing degradation rates and improving performance under extreme thermal and electrical stress [14]. Consequently, they are increasingly used in high-reliability systems such as automotive, aerospace, and renewable energy converters.

In addition to material and architectural considerations, computational simulation plays a crucial role in evaluating power electronic circuits before physical implementation. In this work, the analysis and validation of the proposed Stacked Switched Capacitor (SSC) topology are performed entirely through OrCAD PSpice simulations, enabling the capture of transient phenomena, quantification of ripple effects, and evaluation of capacitor dynamics under varying load conditions. This simulation-driven approach establishes a solid foundation for design optimization. It aligns the study with widely adopted computational methodologies in modern power electronics research.

1.1. Impact of Material Advancements on Energy Density and Reliability

Energy density is one of the most valued properties in capacitors. Traditionally, electrolytic capacitors have been chosen for their high energy density compared to other technologies [15]. However, their long-term reliability has been challenging due to aging effects, heat, and electrolyte degradation.

• New technologies to improve energy density: with advancements in materials and architecture, SSC provide an innovative solution. By stacking multiple capacitors in a switched configuration, energy density is improved by allowing the system to utilize the total capacity of multiple capacitors while reducing individual stress on each one [16]. This results in improved reliability and thermal efficiency, leading to better space utilization and higher energy density for power systems.
• Capacitors with improved materials: advanced materials such as conductive polymers and ceramics have evolved capacitors to offer better performance, lower ESR [17], and higher energy storage capacity. This advancement in materials has enabled the design of capacitors that operate more efficiently at high frequencies and have excellent resistance to thermal degradation, enhancing the system’s overall reliability.

1.2. Stacked Switched Capacitor Architecture as a Solution to Overcome Limitations

• Despite material advancements, capacitor architecture remains critical to improving system reliability and energy density. SSC directly address the inherent reliability issues of traditional electrolytic capacitors.
• Distribution of electrical and thermal stress: the stacking technique evenly distributes electrical and thermal stress among the capacitors, reducing the risk of premature failure and improving system longevity [18]. This distribution enhances system efficiency regarding charge and discharge capacity, resulting in higher energy density.
• Flexibility and adaptability: SSC systems allow for dynamic switching between capacitors, providing greater flexibility in their operation. This is essential in applications with variable operating conditions, such as in renewable energy systems or high-frequency power electronics [19].

1.3. Simulation-Based Validation Approach

Simulation has become an essential step in evaluating advanced power decoupling techniques. In this work, OrCAD PSpice is employed as the primary environment to model and analyze stacked switched capacitor (SSC) topologies. This computational approach ensures that the proposed architectures are assessed under realistic operating conditions, allowing accurate validation of their behavior before physical implementation.

Ripple at twice the grid frequency is one of the leading causes of issues affecting systems designed for interconnection with the power grid. Table 1 provides a summary of these issues.

Table 1. Effects on systems due to ripple at twice the grid frequency.

References	System	Effect on the System	Cause and Restriction
[6]	Link Capacitor	Low capacitor life	Large equivalent series resistance
[20]	MPPT	Low efficiency	High oscillation ripplel
[21]	Batteries	Affect electrodes and electrolyte	Hysteresis heating
[22]	LED’s	Flicker effect, visual fatigue	Flicker should be limited to 10%

From the above, it is known that electrolytic capacitors unfortunately have temperature limitations and a reduced lifespan, making them undesirable for high-reliability applications. Consequently, the challenge of managing time-varying energy storage for single-phase conversion applications is well established.

In contrast to electrolytic capacitors, ceramic capacitors offer a longer lifespan [23]. However, directly substituting electrolytic capacitors with ceramic ones is not feasible due to the significant difference in energy density between the two technologies. Therefore, it is essential to consider approaches that reduce the amount of energy required to be stored in the DC link, aiming to employ components that, in principle, contribute to extending the overall system lifespan.

2. Decoupling Systems

Power decoupling methods are employed to minimize excess energy in the DC-link of grid-connected converters. These methods, which typically incorporate active switches and energy storage units, apply to AC–DC or DC–AC conversion systems [24].

These methods are broadlyclassified as independent (operating separately from the converter) or dependent (sharing converter switches) [25].

This classification is equivalent to the distinction between passive and active decoupling techniques, as shown in Figure 1.

Figure 1. Classification of decoupling techniques [19].

Passive methods, relying solely on capacitors, are bulky but straightforward due to the large capacitance required to smooth power oscillations. Their main drawbacks include high volume, weight, and limited lifetime. Conversely, active decoupling methods employ semiconductor switches and auxiliary circuits to reduce the required capacitance and improve system compactness [25,26].

2.1. Conventional Active Schemes

Conventional active approaches integrate auxiliary converters or energy buffers to regulate the DC-link voltage. Reported configurations have demonstrated reduced AC distortion, efficient use of film capacitors, and smaller capacitances [27,28,29,30,31,32,33]. However, these methods typically exhibit limitations such as high voltage stress or low efficiency in photovoltaic applications [34,35]

A summary of the main advantages and disadvantages of classical topologies is presented in Table 2.

Table 2. Advantages and disadvantages of conventional schemes.

References	Advantages	Disadvantages
[25,26]	Low AC distortion	Not suitable for grid-connected photovoltaic applications.
[27,28]	Efficient use of film capacitors	The efficiency of this solution is limited.
[29,30]	Enables the use of reduced capacitances	Not suitable for photovoltaic Applications.
[31,32,33]	Achieves a reduction of the bonding component	Generates high voltage across devices.
[34,35]	Uses smaller components	It shows reduced efficiencies and increased system size.

Among these methods, the SSC topology stands out as a more efficient solution. The SSC enables higher energy density and power capability by stacking multiple capacitors in a switched configuration [36,37]. Compared with conventional topologies, SSC architectures achieve higher efficiency, reduced ripple, and lower dependence on electrolytic components [38,39].

2.2. SSC Architecture

The SSC concept distributes electrical and thermal stress among stacked capacitors, improving reliability and energy density [37]. Two main variants are recognized: unipolar and bipolar architectures (Figure 2, Figure 3 and Figure 4) [40]. The unipolar scheme features a single energy path with a limited voltage range. In contrast, the bipolar configuration utilizes an H-bridge, enabling flexible series or parallel capacitor operation to balance voltages dynamically.

Figure 2. Basic scheme by applying an SSC architecture [40].

Figure 3. Unipolar architecture [40].

Figure 4. Bipolar architecture [40].

Both configurations allow controlled charge/discharge among capacitors to maintain DC-link stability. The SSC topology minimizes switching and magnetic losses, thus enhancing efficiency and extending component lifespan density [38,39]. Its modular structure and scalability make it well-suited for renewable energy interfaces where space and lifetime constraints are critical.

2.3. Impact of Energy Regression on DC-Link Capacitor Sizing

The conventional analysis used to determine the size of the DC-link capacitor is generally based on the assumption that energy flows unidirectionally from the DC bus to the inverter. This assumption would be valid in the absence of passive filters, such as L or LCL filters, between the inverter and the grid; however, in real-world applications, these filters are essential to attenuate high-frequency harmonics generated by the inverter and to comply with grid code requirements. The inclusion of such filters introduces a phase shift between the voltage supplied by the inverter and the voltage at the grid side, a situation typically compensated for by the use of a Phase-Locked Loop (PLL), which aligns the inverter output to maintain a unity power factor at the grid connection point. However, this phase shift results in a non-unity power factor at the interface between the inverter and the passive filter, leading to a bidirectional flow of reactive power, with a portion of this energy being reflected back toward the inverter and consequently into the DC-link capacitor [41]. This phenomenon is referred to as energy regression and becomes more pronounced when the power factor at the grid connection point deviates from unity, a condition commonly associated with reactive power injection by the inverter. As a result, a greater amount of reactive energy is returned to the DC-link capacitor, increasing the voltage ripple and potentially compromising system stability. Although the PLL maintains synchronization with the grid, it does not prevent this energy regression toward the capacitor. The traditional solution has been to oversize the DC-link capacitor to ensure it can absorb the returned energy and keep the voltage ripple within acceptable limits. A recent study has presented and analyzed these phenomena in similar configurations in detail [42]; in this work, only the specific case of unity power factor operation at the point of common coupling with the grid is considered. Figure 5 illustrates the power flow through the capacitor between a DC-DC converter and a DC-AC inverter, highlighting the relationship between the input current (i_dc), the inverter current (i_Inv), and the capacitor current (iC_link), which reflects the transient and oscillatory behavior associated with energy regression.

Figure 5. Current flow through the DC-link capacitor [42].

2.4. Design Considerations for SSC Architectures

Various SSC topologies have been proposed, including unipolar and bipolar configurations; however, all energy buffering solutions based on SSCs presented so far employ capacitors without considering the effects of energy regression. This section analyzes capacitors in SSC architectures under new considerations, aiming to further enhance energy density compared to conventional designs. By adjusting the capacitance values and reconfiguring the arrangement of the capacitors, the goal is to maximize both operational efficiency and the system’s energy storage capacity. A key parameter in this analysis is the energy buffering ratio (Γ_b), defined as the ratio between the energy that can be injected and extracted during a charge/discharge cycle and the total energy capacity of the architecture [43].

$${\mathsf{\Gamma }}_b={\displaystyle \frac{2(m+2)R_v}{{(2^2+3^2+\cdots +(m+1)}^2){R_v}^2+{(1+R_v)}^2}}$$

(1)

Here, R_v is the voltage ripple ratio on the DC bus, and mmm is the number of support capacitors.

The higher the value of ${\mathsf{\Gamma }}_b$, the smaller the required energy buffer for a given amount of energy that needs to be absorbed. Therefore, maximizing the energy buffering ratio is a highly desirable objective.

By definition, the energy buffering ratio is given by [44]:

$${\mathsf{\Gamma }}_b={\displaystyle \frac{W_{max}-W_{min}}{W_{rated}}}$$

(2)

where W_max and W_min are the maximum and minimum values of the energy stored in the energy buffer under normal operating conditions, and W_rated is the total energy capacity. In the case of a unipolar SSC energy buffer with unequal capacitances, W_rated = W_max; therefore, the expression simplifies to:

$${\mathsf{\Gamma }}_b=1-{\displaystyle \frac{W_{max}}{W_{rated}}}$$

(3)

The maximum and minimum energy stored in an enhanced unipolar 1-m SSC energy buffer can be expressed in terms of the energy of the individual capacitors at the initial state (when fully charged, (4)) and at the final state (when fully discharged, (5)), respectively:

$$W_{max}={\displaystyle \frac{1}{2}}{C}_{11}{V_{C11\left(ini\right)}}^2+\sum _{j=1}^m{\displaystyle \frac{1}{2}}{C}_{2j}{V_{C2j\left(ini\right)}}^2$$

(4)

$$W_{min}={\displaystyle \frac{1}{2}}{C}_{11}{V_{C11\left(fin\right)}}^2+\sum _{j=1}^m{\displaystyle \frac{1}{2}}{C}_{2j}{V_{C2j\left(fin\right)}}^2$$

(5)

Here, $V_{C1j\left(ini\right)}$ and $V_{C1j\left(fin\right)}$ represent the initial and final voltages across the capacitor C_1j at the beginning and end of the discharge period, respectively.

Figure 6 shows the voltage waveforms for an enhanced unipolar 1-m SSC energy buffer with different capacitance values, under discharge with a constant current during normal operation. These waveforms can be used to express the initial and final voltages across each capacitor in terms of the nominal DC bus voltage (V_nom).

Figure 6. Initial and final voltages.

When the configuration is fully charged (i.e., at the initial state), capacitor C₁₁ is directly connected across the DC bus. Therefore, the initial voltage of C₁₁ is equal to the maximum allowable voltage of the DC bus:

$$V_{C11\left(ini\right)}=(1+R_v)V_{nom}$$

(6)

As the system discharges, the voltage across C₁₁ decreases. When it reaches the minimum allowable value of $(1-R_v)V_{nom}$, capacitor C₂₁ is connected in series with C₁₁ to raise the DC bus voltage.

In order for the DC bus voltage to reach its maximum allowable value again, the initial voltage of C₂₁ must be:

$$V_{C21\left(ini\right)}=2R_v{V}_{nom}$$

(7)

Next, C₁₁ and C₂₁ discharge in series until the total voltage drop across them equals $2R_v{V}_{nom}$, and the DC bus reaches $\left(1+R_v\right)V_{nom}$ once again. Since both capacitors discharge with the same current, their individual voltage drops are inversely proportional to their capacitance values.

Therefore, the final voltage across C₂₁ is given by:

$$V_{C21\left(fin\right)}=2R_v{V}_{nom}-2R_v{V}_{nom}{\displaystyle \frac{C_{11}}{C_{21}+C_{11}}}$$

(8)

To raise the DC bus voltage to its maximum allowable value, C₂₂ is connected in series with C₁₁. Subsequently, C₁₁ and C₂₂ discharge until the total voltage drop across them reaches $2R_v$. Then, C₂₃ is connected in series with C₁₁, and the discharge process continues. This sequence is repeated for all remaining support capacitors until C_2m has also fully discharged [45].

Following the analysis of enhanced capacitor configurations with varying capacitance values to improve energy density in SSC systems, the next section presents a case study that illustrates the effective application of the proposed optimization techniques.

3. Case Study Design

This section presents the design of the case study, which involves implementing a Cuk converter. The selection of this converter topology is based on the requirement for a non-pulsating input current an essential characteristic in photovoltaic applications. Additionally, the Cuk converter enables effective reduction of current harmonics, which is necessary to meet power quality standards imposed by the electrical grid.

To ensure reliable and comparable results, specific performance metrics were established to assess each component’s behavior and design stage accurately. These metrics are essential for validating and quantitatively demonstrating why SSC constitute a substantial improvement over conventional architectures, particularly in terms of efficiency and the stability of the generated current.

3.1. Cuk Converter Design

The design parameters are presented in Table 3, and the design methodology is outlined in Table 4. It is worth noting that the input voltage (V_in) was selected based on the specifications of the photovoltaic module TSM-PDG5, which under standard irradiance conditions of 100 W/m² at 25 °C specifies a maximum power point voltage (V_in) of 30.3 V.

Table 3. Design parameters.

Parameter	Symbol	Value
Average power	P	200 W
Network frequency	fg	60 Hz
Frequency ratio	Β	250
Percentage of voltage ripple	5%	15%
Frequency of angular in the network	ω	120 π rad/s
Voltage of photovoltaic panels	Vin	30.3 V
DC bus voltage	Vdc	210 V
Switching frequency	fsw	100 kHz
Peak-to-peak voltage	Vpp	162 V

Table 4. Results of the design methodology.

Equation	Result	Equation	Result
$i_{L1}={\displaystyle \frac{P}{V_{in}}}$	6.601 A	$R_{DC}={\displaystyle \frac{Vout}{iout}}$	220.5 Ω
$\mathrm{\Delta }{i}_{L1}=0.1\cdot i_{L1}$	0.66 A	$I_{DC}={\displaystyle \frac{P}{V_{pp}}}$	1.235 A
$\mathrm{\Delta }{V}_{C1}=0.05\cdot V_{in}$	1.515 V	$I_0={\displaystyle \frac{4\cdot I_{DC}}{\pi }}$	1.572 A
$C_{AC}={\displaystyle \frac{P}{2\cdot \omega \cdot V_r\cdot V_{DC}}}$	601.4 μF	$R_{AC}=\left({\displaystyle \frac{P}{{I_0}^2}}\right)$	80.86 Ω
$\mathrm{\Delta }{V}_{C0}=0.05\cdot V_{out}$	10.5 V	$C1p=n\cdot {\displaystyle \frac{I_{out}\cdot (1-D)}{\mathrm{\Delta }{V}_{c1}\cdot fsw}}$	22.11 μF
$\mathrm{\Delta }{i}_{L2}=0.01\cdot i_{out}$	0.095 A	$C1s={\displaystyle \frac{I_{out}\cdot (1-D)}{\mathrm{\Delta }{V}_{C0}\cdot fsw}}$	0.455 μF
$L1={\displaystyle \frac{V_{in}D}{\mathrm{\Delta }iL1\cdot fsw}}$	228.4 μH	$C2={\displaystyle \frac{V_{out}(1-D)}{L2\cdot \mathrm{\Delta }{V}_{c0}\cdot fs{w}^2\cdot 8}}$	0.12 μF
$L2={\displaystyle \frac{V_{out}(1-D)}{\mathrm{\Delta }iL2\cdot fsw}}$	11.025 mH

In the initial phase, essential criteria were established to ensure precision and consistency in system operation. Voltage and current ripples were standardized to specific target levels to guarantee design stability and reliability. Voltage ripple is constrained within a 5% margin, while current ripple is limited to a maximum of 10%. Table 4 summarizes the results obtained after applying the design methodology, providing the calculated component values for the proposed system.

In this study, the parameters of the simulated components were determined based on widely used commercial materials in medium-power converter applications. Aluminum electrolytic capacitors and ferrite-core inductors were chosen as reference components for the conventional case, reflecting their everyday use in DC-link designs [46]. In contrast, for the proposed SSC configuration, ceramic film capacitors were modeled due to their superior thermal stability, lower ESR, and extended operational lifetime [47]. Semiconductor devices were defined using silicon based MOSFET models available in the OrCAD PSpice component library. This material selection ensures a realistic and technically consistent comparison between conventional and SSC-based architectures, providing a sound basis for evaluating their performance under identical operating conditions.

3.2. Cuk Converter Simulation

All circuit configurations were modeled and evaluated in OrCAD PSpice (version 17.4) to ensure consistency in the comparative analysis. The simulations were performed using transient analysis with a time step of 1 µs and a total duration of 200 ms, which is sufficient to capture steady-state behavior under grid-frequency ripple conditions. Semiconductor switches were modeled with manufacturer-provided SPICE libraries, while passive components were defined according to the calculated values in Table 3, Table 4, Table 5, Table 6, Table 7 and Table 8. The photovoltaic source was represented by a constant DC input corresponding to the maximum power point voltage of 30.3 V at standard irradiance conditions.

Key performance metrics including DC bus voltage ripple, capacitor current stress, and energy storage behavior were extracted directly from the simulation outputs. This approach allows a precise comparison between conventional electrolytic capacitors, standard SSC configurations, and the enhanced SSC architecture. By standardizing the simulation environment, the results provide reproducible and quantitative evidence of the advantages of SSC systems for power decoupling in single-phase DC–AC applications.

4. Simulation Results

This section presents the simulation results obtained using OrCAD-PSpice for the Cuk converter, the increase in capacitance with an AC port, and the implementation of the unipolar SSC architecture (Section 4.2).

These results are critical for evaluating the practical performance of the proposed design and for validating its effectiveness under simulated operating conditions.

4.1. Simulation Results of the Cuk Converter

Figure 7 shows the schematic diagram of the Cuk converter circuit. This detailed representation provides a visual overview of the circuit configuration, including the layout of key components such as inductors, capacitors, and switching elements.

Figure 7. Cuk converter.

The circuit visualization provides a clear understanding of the Cuk converter’s topology and operational principles

To validate the converter’s operation, it is necessary to obtain the output values through simulation. Figure 8 illustrates an output voltage of 207 V from the converter. This result is notably close to the intended design voltage of 210 V. In terms of power, the simulation yields an output of 195 W, whereas the required power to meet the system specifications is 200 W. This level of approximation demonstrates the converter’s practical ability to meet the system’s power demand.

Figure 8. Cuk converter result.

4.2. Results of the Cuk Converter with AC Port

The schematic of the Cuk converter combined with the AC inverter (H-bridge) is presented. Figure 9 provides a complete representation of the connection between the converter and the inverter.

Figure 9. Cuk converter AC-port.

When the AC port is connected to the converter, the significant increase in DC-link capacitance from 0.12 μF to 601.5 μF is attributed to the system’s inherent nature and its operational demands. The DC-link capacitor plays a critical role in energy conversion and in interfacing the converter with the AC source. Its sizing is essential for fulfilling multiple functions, including voltage ripple mitigation and DC supply stabilization. Upon integration with the AC port, the Cuk converter operates in conjunction with the inverter to accommodate AC fluctuations and ensure a controlled and stable power delivery.

The increased capacitance is directly related to the need for efficient energy buffering, especially considering that AC power varies at twice the grid frequency, as illustrated in Figure 10. This higher capacitance enables the system to effectively manage input fluctuations, smooth the output voltage, and ensure a continuous and reliable energy supply.

Figure 10. AC power fluctuations.

4.3. Results of the Cuk Converter with the SSC Architecture

Table 5 and Table 6 summarize the main design parameters and calculated results for the stacked switched capacitor (SSC) architecture in its unipolar configuration. The design process follows the analytical procedure described in [44], which determines the required capacitance to achieve the desired voltage ripple and energy balance on the DC bus.

This unipolar configuration demonstrates a substantial reduction in the required capacitance, as the system now employs four 15 μF capacitors instead of a single 600 μF capacitor while maintaining equivalent decoupling performance.

Table 5. Key design parameters of the SSC system.

Parameter	Symbol	Value
Power	$P_{dc}$	200 W
Backbone capacitors	n	1
Support capacitors	m	3
Maximum voltage	$V_{max}$	270 V
Minimum voltage	$V_{min}$	140 V
Nominal voltage	$V_{nom}$	210 V
Percentage of ripple on DC bus	$Rv$	10%
Angular frequency	$\omega$	377 rad/s

Table 5. Key design parameters of the SSC system.

Parameter	Symbol	Value
Power	$P_{dc}$	200 W
Backbone capacitors	n	1
Support capacitors	m	3
Maximum voltage	$V_{max}$	270 V
Minimum voltage	$V_{min}$	140 V
Nominal voltage	$V_{nom}$	210 V
Percentage of ripple on DC bus	$Rv$	10%
Angular frequency	$\omega$	377 rad/s

Table 6 presents the calculated capacitance for the SSC system, derived from the design parameters listed in Table 5 and following the methodology described in [44]. This approach ensures that the SSC configuration meets the targeted voltage ripple and energy distribution requirements for the system.

Table 6. Calculated capacitance of the SSC system [44].

Equation	Result
$\mathrm{\Delta }=n\left[{\left(1+\left(m+1\right)Rv\right)}^2-{\left(1-\left(m+1\right)Rv\right)}^2\right]$	1.6
$C={\displaystyle \frac{2\cdot P_{dc}}{\mathrm{\Delta }\cdot {V_{nom}}^2\cdot \omega }}$	15 μF

Table 6. Calculated capacitance of the SSC system [44].

Equation	Result
$\mathrm{\Delta }=n\left[{\left(1+\left(m+1\right)Rv\right)}^2-{\left(1-\left(m+1\right)Rv\right)}^2\right]$	1.6
$C={\displaystyle \frac{2\cdot P_{dc}}{\mathrm{\Delta }\cdot {V_{nom}}^2\cdot \omega }}$	15 μF

Figure 11 provides a representation of the system with the AC port, incorporating the unipolar SSC architecture.

Figure 11. Cuk converter unipolar architecture.

To visualize the results using the unipolar SSC architecture as the DC link, Figure 12 shows the AC power, which varies at twice the grid frequency and reaches a peak of 387 W. Meanwhile, Figure 13 illustrates the voltage stability on the DC side, with a ripple of only 5 V, confirming the SSC architecture’s ability to maintain the desired operating levels.

Figure 12. AC power fluctuations.

Figure 13. DC link voltage.

In DC-AC applications, efficiency and power decoupling performance are critical factors for ensuring optimal system operation. Given the wide variety of active systems available on the market, it is essential to conduct detailed comparisons among different system types to make informed decisions and enhance application design. The need to compare results across various active systems lies in the pursuit of improvements in efficiency, stability, and the dynamic response of DC-AC converters.

4.4. Results of the Cuk Converter with the Enhanced SSC Architecture

Table 7 and Table 8 summarize the design parameters and calculated capacitance values for the SSC system under new considerations related to energy regression. This configuration aims to enhance output power while maintaining voltage ripple constraints. The unipolar 1–2 configuration achieved capacitance values of 36 µF, resulting in improved system performance and reduced energy imbalance across the capacitive stages.

Table 7. Key design parameters of the SSC system under energy regression conditions [44].

Parameter	Symbol	Value
Power	$P_{dc}$	200 W
Backbone capacitors	n	1
Support capacitors	m	2
Maximum voltage	$V_{max}$	270 V
Minimum voltage	$V_{min}$	140 V
Nominal voltage	$V_{nom}$	210 V
Percentage of ripple on DC bus	$Rv$	10%
Angular frequency	$\omega$	377 rad/s

Table 7. Key design parameters of the SSC system under energy regression conditions [44].

Parameter	Symbol	Value
Power	$P_{dc}$	200 W
Backbone capacitors	n	1
Support capacitors	m	2
Maximum voltage	$V_{max}$	270 V
Minimum voltage	$V_{min}$	140 V
Nominal voltage	$V_{nom}$	210 V
Percentage of ripple on DC bus	$Rv$	10%
Angular frequency	$\omega$	377 rad/s

Table 8. Calculated capacitance of the SSC system under the 1–2 configuration [42].

Equation	Result
$C={\displaystyle \frac{2\cdot P_{dc}}{fsw\cdot d{V_{min}}^2}}$	36.28 μF

Table 8. Calculated capacitance of the SSC system under the 1–2 configuration [42].

Equation	Result
$C={\displaystyle \frac{2\cdot P_{dc}}{fsw\cdot d{V_{min}}^2}}$	36.28 μF

To visualize the system behavior, Figure 14 displays the AC power profile, which fluctuates at twice the grid frequency and reaches a peak of 390 W. Understanding the behavior of energy stored in the capacitances is essential especially when comparing different types of capacitors in applications such as the 200 W case, where the goal is to improve performance and reduce the size of the DC-link component.

Figure 14. AC power fluctuations.

Table 9 presents a comparative analysis of energy performance across different DC-link architectures, including the electrolytic capacitor, the standard SSC system, and the improved SSC configuration.

Table 9. Energy distribution in the various DC-Link components [48].

Topology	Link Capacitor	Total Energy (J)	ESR	$\mathbf{Passive} \mathbf{Volume} {(\mathbf{m}\mathbf{m}}^3)$
Electrolytic capacitor	$1 \mathrm{of} 601.4 \mathsf{\mu }\mathrm{F}$	13.26	0.24	2010
Capacitor with energy regression considerations	$1 \mathrm{of} 115.7 \mathsf{\mu }\mathrm{F}$	2.55	0.2	890
SSC	$4 \mathrm{of} 15 \mathsf{\mu }\mathrm{F}$	1.323	0.2	710
Enhanced SSC	$3 \mathrm{of} 36 \mathsf{\mu }\mathrm{F}$	2.3	0.2	630

In this context, it is necessary to analyze how an electrolytic capacitor behaves in terms of energy storage and release, taking into account factors such as energy regression, which can negatively affect its performance. This analysis is crucial for identifying the limitations and advantages of using electrolytic capacitors in high-demand energy applications.

When this behavior is compared to that of capacitors in a standard SSC system, the improvement in energy management becomes evident, with reduced losses and enhanced performance. Furthermore, in an improved SSC system featuring enhanced switching and energy distribution capabilities a significant gain in both efficiency and responsiveness to power fluctuations is demonstrated. This improved performance surpasses the limitations of traditional electrolytic capacitors, providing a more stable and reliable operation over time.

When analyzing the energy distribution results presented in Table 10, it becomes clear that the improved SSC topology offers significant advantages in terms of efficiency, reduced passive component volume, and enhanced energy management. To further contextualize these improvements, Table 10 presents a comparative analysis of the proposed SSC system and other reference topologies from the literature, highlighting their key features, performance metrics, and trade-offs in single-phase grid-connected applications.

Table 10. Comparison of topologies for reducing the passive power-decoupling component in single-phase grid-connected applications.

Feature	Case of Study	Ref. [49]	Ref. [50]	Ref. [51]	Ref. [52]
Topology	Cuk converter with unipolar SSC architecture	CLL resonant microinverter with active power decoupling	Microinverter with active power decoupling	Three-level converter using a ripple port for power decoupling	Solar microinverter with active capacitor
Energy in the DC-link (J)	0.992	2.275	2.64	0.84	3.125
Power, output voltage	200 W, 210 V	220 W, 220 V	200 W, 200 V	250 W, 250 V	250 W, 250 V
Number of switching devices used	10 (1 diode, 9 MOSFETs)	10 (6 diode, 4 MOSFETs)	16 (2 diode, 14 MOSFETs)	11 (1 diode, 10 MOSFETs)	9(1 diode, 8 MOSFETs)
Efficiency (%)	94	94	96	96.1	95
Size of passive elements for power decoupling	Three 15 μF Capacitors	Two 47 μF Capacitors	Four 33 μF Capacitors	A 5 μF capacitor, a 37 μF capacitor and a 300 μH inductor.	Two 50 μF Capacitors
Output filter type	LCL filter	LCL filter	LC filter	LC filter	LCL filter
Output filter values	Lf,L0 = $25\mathrm{mH}{C}_f=1.6\mathsf{\mu }\mathrm{F}$	Lg1 = $1\mathrm{mH},L_{g2}=1\mathrm{mH}{\mathrm{C}}_g=2\mathsf{\mu }\mathrm{F}$	Lf $=11\mathrm{mH},C_f=1\mathsf{\mu }\mathrm{F}$	Ls $=8\mathrm{mH},C_s=5\mathsf{\mu }\mathrm{F}$	(2) Lf = 1 mH, Cf = 30 $\mathsf{\mu }\mathrm{F}$
Switching frequency	100 kHz	230 kHz	200 kHz	100 kHz	50 kHz

5. Comparison of Conventional and Proposed SSC Topologies

Table 10 summarizes the key features of the proposed stacked switched capacitor (SSC) topology and several conventional active decoupling models reported in [33,34,35], which are used here as reference benchmarks. These reference topologies include typical active decoupling circuits and classical SSC-based configurations commonly applied in microinverter and grid-connected systems. The comparison focuses on crucial aspects such as capacitor size, efficiency, energy storage capability, and switching complexity, to highlight the advantages and trade-offs of the proposed SSC approach.

• Advantages of the proposed SSC topology:

The SSC design significantly reduces capacitor size compared to conventional solutions, using only three 15 μF for power decoupling, which is particularly beneficial for space-constrained applications. It achieves high efficiency (94%), comparable to other advanced microinverter designs. The topology employs fewer switching devices (10), simplifying the control strategy compared to more complex configurations, such as the microinverter in Ref. [34], which uses 16 switching devices.

• Disadvantages:

The SSC exhibits lower DC-link energy (0.992 J) than some reference models (e.g., Ref. [35] with 3.125 J), potentially limiting transient energy buffering.

Output filtering options are more constrained by the SSC architecture, potentially limiting flexibility in specific applications.

• Trade-offs and rationale:

The SSC topology prioritizes compactness and reduced component count over maximum energy storage.

Reference models with higher DC-link energy and larger passive elements (Refs. [33,34,35]) provide superior transient buffering but at the cost of increased size, complexity, and number of switching devices.

• Application-based decision-making:

For space- or cost-sensitive microinverters, the SSC topology is advantageous due to its compact design and minimal components.

For applications that require ample transient energy storage or very high DC-link energy, the reference topologies may be more appropriate despite their higher complexity.

This discussion provides a comprehensive comparison of the strengths, weaknesses, and trade-offs of each approach, offering guidance on selecting the most suitable topology for specific application requirements.

6. Concluding Remarks

Following a detailed analysis of the results presented in Table 10, several key conclusions can be drawn:

The SSC topology enables a substantial reduction in required capacitance, replacing a single 600 μF capacitor with just four 15 μF capacitors, thereby improving energy efficiency, optimizing physical space, and lowering passive component costs.

The architecture does not require high-end components and operates at a relatively low switching frequency, further reducing implementation costs and making it a practical solution for DC-AC applications.

A careful balance between system performance and structural complexity is highlighted, as the SSC topology achieves high efficiency with a moderate number of switching devices, in contrast to some conventional designs that require many components.

The SSC reduces reliance on electrolytic capacitors, offering a compact, durable, and sustainable alternative without compromising overall efficiency.

Energy storage and delivery within the DC-link confirm the robustness of the SSC architecture, demonstrating performance comparable to or better than recent proposals.

All results were validated through circuit-level simulations in OrCAD PSpice, providing a reproducible framework for comparing conventional and SSC-enhanced architectures and offering a reliable basis for future experimental validation.

Future Work

Future stages of this research will focus on the experimental validation of the proposed SSC topology through the development of a physical prototype. This implementation will allow the evaluation of energy efficiency, thermal behavior, and component reliability under real operating conditions, providing further insight into the practical feasibility of the SSC-based active decoupling approach.