A Seven-Level Single-DC-Source Inverter with Triple Voltage Gain and Reduced Component Count

Abstract

This paper proposes a novel seven-level switched-capacitor multilevel inverter featuring a shared front-end DC-link structure that achieves triple voltage gain with reduced component count. A distinctive feature of this design is its inherent capacitor voltage self-balancing capability, thereby eliminating the need for complex control algorithms typically associated with multilevel converters. Moreover, the topology demonstrates particularly significant advantages in three-phase implementations, where a single DC source, front-end switching devices, and capacitors can be shared across all phases—thus substantially reducing component count and system complexity compared to conventional designs. Additionally, this paper proposes an improved carrier-based modulation strategy for this topology requiring only a single triangular carrier, along with a systematic method for determining optimal capacitance values. Through detailed comparative assessment against state-of-the-art switched-capacitor seven-level inverters, the superior performance characteristics of the proposed topology are clearly demonstrated. Finally, simulation results under various operating conditions are presented and subsequently validated through experimental testing on a laboratory prototype, confirming the practical viability of the proposed solution.

1. Introduction

The global transition toward renewable energy has driven significant advancements in power conversion technologies. Multilevel inverters (MLIs) have emerged as a critical component in this transition, particularly for photovoltaic (PV) grid-connected applications, due to their superior power quality, reduced harmonic distortion, and lower dv/dt stress [1,2,3]. MLIs can be broadly classified into three traditional categories: Flying Capacitor (FC), Neutral Point Clamped (NPC), and Cascaded H-Bridge (CHB) topologies, each with distinct operational characteristics and application domains [4,5].

Despite their widespread adoption, these conventional MLI topologies face a fundamental challenge when applied to grid-connected photovoltaic systems. The output voltage of individual PV modules is inherently low (typically 30–50 V) [6,7], whereas grid integration requires substantially higher AC voltages (220 V for single-phase or 380 V for three-phase systems). This voltage disparity creates a critical design constraint, as traditional FC, NPC, and CHB topologies function primarily as step-down inverters. Current approaches to address this mismatch include connecting multiple PV modules in series or incorporating transformer-based inverters, both of which introduce disadvantages such as increased system complexity, higher costs, and reduced efficiency.

The switched-capacitor (SC) principle offers a promising solution to overcome these limitations by enabling voltage boosting capabilities within the inverter topology [8,9]. In SC-based configurations, capacitors are strategically connected in parallel with the input voltage source during charging phases, then reconfigured in series to achieve higher output voltages [10]. This approach has sparked considerable research interest as a means to develop step-up multilevel inverters with reduced component count and enhanced performance characteristics.

Recent literature has documented various seven-level switched-capacitor inverters with differing voltage gain capabilities. These can be classified into two main categories based on their voltage gain ratios: those achieving a gain of 1.5 and those reaching a gain of 3. Reference [11] proposed a modified ANPC inverter with a 1.5 voltage gain and seven-level output using eight power switches and a floating capacitor. Similarly, reference [12] developed a self-voltage balancing ANPC inverter with low voltage stress on switches by integrating active neutral point clamped and T-type structures. Reference [13] introduced a dual T-type-based approach, though it required a larger number of switched-capacitors. Reference [14] presented a seven-level improved packed U-cell inverter with reduced power electronic components, enabling voltage boosting capabilities, but limited to single-phase applications.

Recent advances in multilevel inverter design have successfully elevated voltage gain ratios to 3, effectively addressing the higher voltage requirements essential for grid integration applications. A notable approach in [15] features three interconnected H-bridges utilizing two switches with bidirectional voltage blocking capability. In this configuration, only one H-bridge receives direct DC power supply, while the remaining two incorporate switched capacitors charged through the interconnected switches. Despite its effectiveness, this topology demands as many as 16 power switches, significantly increasing component count and system complexity. To address this limitation, references [16,17] introduced more compact seven-level two-stage topologies incorporating load-end H-bridges, thereby reducing the required number of switching devices. However, these designs suffer from a critical drawback: certain switching components must withstand substantially higher voltage stress, compromising reliability and efficiency. References [18,19] subsequently developed single-stage topologies that effectively mitigate the high voltage stress issues inherent in the two-stage architectures. Although these single-stage configurations successfully achieve the desired triple voltage gain, they require separate DC power supplies for each phase in three-phase implementations. Furthermore, most existing triple-gain topologies continue to employ numerous components, inevitably increasing system complexity, manufacturing costs, and potential failure points throughout the power conversion chain.

To address these limitations, this paper proposes a novel seven-level single-DC-source inverter with triple voltage gain (7L-SDS-TVG inverter) with the following distinctive contributions:

(1)

Single-source three-phase implementation: Unlike existing triple-gain topologies [15,16,17,18,19] that require separate DC sources for each phase in three-phase applications, the proposed topology enables all three phases to share a single DC power supply along with the front-stage switched-capacitor network.

(2)

Inherent capacitor voltage self-balancing: The topology achieves natural voltage balancing across all capacitors without requiring complex auxiliary balancing circuits or control algorithms.

(3)

Simplified single-carrier PWM modulation: An improved carrier-based modulation strategy requiring only one triangular carrier is proposed, reducing the control complexity compared to conventional multi-carrier methods.

(4)

Reduced component count in three-phase configuration: Through strategic sharing of front-stage components, the three-phase implementation requires fewer power devices compared to the existing topologies [15,16,17,18,19].

The remainder of this paper is structured as follows: Section 2 introduces the proposed topology and analyzes its operating principles with detailed mode explanations. Section 3 presents the improved PWM modulation method and capacitance value calculation method. Section 4 provides simulation results validating the topology’s performance. Section 5 presents experimental verification using a laboratory prototype. Finally, Section 6 summarizes the key findings of the paper.

2. The Proposed Seven-Level Single-DC-Source Inverter with Triple Voltage Gain

2.1. Topology

The proposed seven-level single-DC-source Inverter with triple voltage gain is shown in Figure 1. The front-end stage comprises fully controlled switching devices T₁ and T₂, diodes D₁ and D₂, and capacitors C_dc1 and C_dc2. Meanwhile, the rear-end stage consists of fully controlled switching devices S₁–S₉ and capacitors C₁ and C₂. All switching devices are integrated with anti-parallel diodes for bidirectional current flow capability. Through strategic control of the on and off states of switching devices S₁–S₉ and T₁–T₂, the topology enables various series and parallel configurations of capacitors C₁, C₂, C_dc1, C_dc2, and the DC source V_dc. This versatile arrangement consequently allows the inverter to generate seven distinct output voltage levels: 0, ±E, ±2E, and ±3E.

2.2. Working Principle

The operational modes of the proposed 7L-SDS-TVG inverter across one fundamental frequency cycle are illustrated in Figure 2, where each output voltage level corresponds to a distinct conduction path indicated by solid lines. To facilitate analytical clarity, parasitic parameters associated with power devices and wiring are neglected, and the DC-link capacitor is assumed sufficiently large such that its voltage ripple is negligible.

Mode 1: The output voltage is +3E. During this mode, switching devices S₁, S₂, S₆, S₇, and S₈ are turned on, enabling capacitors C_dc1, C₁, and C₂ to connect in series and discharge into the load as shown in Figure 2a.

Mode 2: The output voltage is +2E. In this state, switching devices S₂, S₃, S₆, S₇, and S₈ conduct, while all other switches remain off. Consequently, capacitors C_dc1 and C₂ form a series connection to deliver energy to the load as shown in Figure 2b.

Mode 3: The output voltage is +E. Here, switching devices S₁, S₂, S₅, S₆, S₈, and S₉ conduct. Capacitor C_dc1 discharges directly to the load, while simultaneously, capacitors C_dc1 and C_dc2 connect in series to charge C₁ and C₂ as shown in Figure 2c.

Mode 4: The output voltage is 0. In this zero-voltage mode, switching devices S₂, S₃, S₅, S₆, S₈, and S₉ conduct. Meanwhile, capacitors C_dc1 and C_dc2 form a series connection to charge capacitors C₁ and C₂ as shown in Figure 2d,e.

Mode 5: The output voltage is −E. During this negative voltage state, switching devices S₃, S₄, S₅, S₆, S₈, and S₉ are turned on. Capacitor C_dc2 discharges to the load, while capacitors C_dc2 and C_dc1 connect in series to charge capacitors C₁ and C₂ as shown in Figure 2f.

Mode 6: The output voltage is −2E. In this mode, switching devices S₂, S₃, S₅, S₇, and S₉ are turned on, enabling capacitors C_dc2 and C₁ to discharge in series to the load as shown in Figure 2g.

Mode 7: The output voltage is −3E. For this maximum negative voltage state, switching devices S₃, S₄, S₅, S₇, and S₉ are turned on, allowing capacitors C_dc2, C₁, and C₂ to connect in series and discharge collectively to the load as shown in Figure 2h.

To ensure continuous power flow and voltage balancing, the front-end switching devices operate in complementary fashion across the fundamental frequency cycle. Specifically, during the positive half-cycle, switching device T₂ remains continuously on, allowing the DC power supply to charge capacitor C_dc1. Conversely, during the negative half-cycle, switching device T₁ remains on, charging capacitor C_dc2. Through this alternating charging mechanism, the voltages across capacitors C_dc1 and C_dc2 achieve inherent self-balancing without requiring additional control circuitry.

Table 1. Working states of switching devices and capacitors under different modes of inverters.

Output	The Switching Devices in the Conducting State	Capacitor States
		C1	C2	Cdc1	Cdc2
+3E	S1, S2, S6, S7, S8, T2	D	D	C	—
+2E	S2, S3, S6, S7, S8, T2	—	D	C	—
+E	S1, S2, S5, S6, S8, S9, T2	C	C	C	D
0	S2, S3, S5, S6, S8, S9, T2	C	C	C	D
0	S2, S3, S5, S6, S8, S9, T1	C	C	D	C
−E	S3, S4, S5, S6, S8, S9, T1	C	C	D	C
−2E	S2, S3, S5, S7, S9, T1	D	—	—	C
−3E	S3, S4, S5, S7, S9, T1	D	D	—	C

systematically summarizes the switching states of all power devices and the corresponding capacitor operational states across each mode, where “C”, “—”, and “D” denote capacitor charging, voltage holding, and discharging states, respectively.

3. Proposed Single Carrier PWM Modulation and Analysis of Capacitor Characteristics

3.1. Proposed Single Carrier PWM Modulation

The carrier disposition PWM method is a well-established modulation technique for multilevel inverters [20,21]. In conventional implementations, an N-level inverter requires (N − 1) level-shifted triangular carriers, each compared with the modulation signal to generate the corresponding switching signals. To reduce hardware and computational complexity, this paper proposes an improved carrier level-shifted method that simplifies the modulation process by modifying the modulation waveforms. As a result, only a single triangular carrier is required to achieve the desired multilevel output.

The modulation principle proposed is illustrated in Figure 3. The mathematical expression of the modulating wave is defined as follows:

$$V_{\mathrm{ref}}=m\sin \left(\mathsf{\omega }t\right)$$

(1)

where m denotes the modulation depth, 0 < m ≤ 1, and ω represents the angular frequency.

By taking the absolute value of the modulated wave V_ref, the resulting waveform V_R is obtained.

$$V_{\mathrm{R}}=\left|m\sin \left(\mathsf{\omega }t\right)\right|$$

(2)

If 0 < V_R ≤ 1/3, set V_R1 = 0; if 1/3 < V_R ≤ 2/3, set V_R1 = 1/3; if 2/3 < V_R ≤ 1, set V_R1 = 2/3. Thus, the resulting value of V_R1 can be expressed as

$$V_{\mathrm{R}1}=\left\{\begin{array}{ll}0& 0<V_{\mathrm{R}}\le {\displaystyle \frac{1}{3}}\\ {\displaystyle \frac{1}{3}}& {\displaystyle \frac{1}{3}}<V_{\mathrm{R}}\le {\displaystyle \frac{2}{3}}\\ {\displaystyle \frac{2}{3}}& {\displaystyle \frac{2}{3}}<V_{\mathrm{R}}\le 1\end{array}\right.$$

(3)

Subtract Equation (3) from Equation (2) to derive V_R2. Subsequently, compare V_R2 with a triangular carrier having an amplitude of 1/3 and a frequency f_c to generate the main PWM signal G_PWM. The G_PWM is then allocated for each power device according to Figure 4, and then the on/off states of all power devices and output voltage are illustrated in Figure 5.

During operation of the 7L-SDS-TVG inverter, the modulation depth m serves as a critical parameter that directly determines the number of distinct output voltage levels generated by the system.

Table 2. The relationship between the modulation depth and the output voltage level.

Modulation Depth	Output Voltage	Level
$0<m\le 1/3$	0, ±E	3
$1/3<m\le 2/3$	0, ±E, ±2E	5
$2/3<m\le 1$	0, ±E, ±2E, ±3E	7

presents a comprehensive characterization of this relationship, illustrating how the output voltage level distribution systematically varies across different modulation depth ranges. This correlation between modulation depth and output level count provides system designers with a valuable control parameter for optimizing performance based on specific application requirements.

3.2. Capacitor Voltage Self-Balancing Analysis

Maintaining capacitor voltage balance is fundamental to ensuring reliable inverter operation. Voltage imbalances across capacitors can precipitate multiple adverse effects: output voltage offset, elevated voltage stress on semiconductor switching devices, waveform distortion, and potentially hazardous overvoltage or overcurrent conditions—all of which significantly compromise system stability and operational safety.

Analysis of the inverter’s operational principles, as described in the preceding section, combined with the detailed switching states presented in Table 1, reveals an inherent self-balancing mechanism within the topology. During each fundamental frequency cycle, the front-stage capacitors C_dc1 and C_dc2 undergo systematic charging sequences, alternately connecting in parallel with the DC power supply. Specifically, during positive-level output intervals, the DC source charges capacitor C_dc1 through the activated switching device T₂; conversely, during negative-level output periods, capacitor C_dc2 receives charge via switching device T₁.

For the rear-stage capacitors C₁ and C₂, the voltage balancing mechanism operates during specific output states. When the inverter generates either a “0” level or a “±E” level output, the series-connected pair C_dc1–C_dc2 establishes a parallel connection with the series combination of C₁ and C₂, facilitating energy transfer and regulated charging. Through this coordinated switching arrangement, the DC power source sequentially delivers energy to front-stage capacitors C_dc1 and C_dc2, which subsequently transfer appropriate energy to rear-stage capacitors C₁ and C₂. This orchestrated energy flow pathway establishes a voltage self-balancing mechanism across all four capacitors—C_dc1, C_dc2, C₁, and C₂—without requiring additional balancing circuits or control complexity.

3.3. Capacitance Value Calculation

In switched-capacitor multilevel inverters, precise capacitance selection represents a critical design consideration. Inadequate capacitance inevitably results in excessive voltage ripple, compromising output waveform quality and harmonic performance, while oversized capacitance unnecessarily increases system volume, weight, and cost. Consequently, optimal capacitance determination is fundamental to achieving the desired performance–cost balance.

Taking capacitor C₂ for example, when the inverter outputs voltage levels of 0 and E, capacitor C₂ is in a charging state (shown in Figure 2 and Table 1). In contrast, when the output levels are 2E and 3E, capacitor C₂ transits to a discharging state. Under carrier-based PWM modulation, the output voltage of the inverter switches at high frequency between adjacent voltage levels. As depicted in Figure 6, if the output switches between 0 and E, C₂ stays continuously in the charging state, and its voltage stabilizes after reaching the rated value. When the output switches between E and 2E, C₂ alternates frequently between charging and discharging, leading to a relatively small voltage ripple. Nevertheless, when the output switches between 2E and 3E, C₂ continuously discharges. Owing to the extended discharge period, the voltage ripple is relatively larger. Similar operating principles are applicable when the inverter outputs negative voltage levels. Thus, as can be seen from Figure 6, the capacitor voltage remains balanced overall over half of the fundamental cycle.

The capacitance value is governed by the maximum permissible voltage ripple, which correlates directly with both the capacitance magnitude and the maximum discharge quantity ΔQ_C:

$$\Delta Q_C={\displaystyle {\int }_{t_a}^{t_b}{I}_{\mathrm{load}}}\sin \left(\omega t-\phi \right)dt$$

(4)

where t_a and t_b denote the initial and final discharge times of capacitor C, respectively. I_load represents the peak load current, while φ indicates the phase difference between the output voltage and the load current, also known as the power factor angle.

As illustrated in Figure 6, the maximum continuous discharge quantity ΔQ_C2 for capacitor C₂ can be expressed as

$$\Delta Q_{C_2}={\displaystyle {\int }_{t_2}^{t_3}{I}_{\mathrm{Ioad}}}\sin \left(\mathsf{\omega }t-\phi \right)dt$$

(5)

From the perspective of the power factor angle, the capacitor discharge current reaches its maximum when the output voltage and output current are in phase (i.e., the power factor angle φ = 0). In terms of the modulation depth, a larger modulation depth m results in a longer capacitor discharge time. Therefore, under the conditions of a power factor angle φ = 0 and a modulation depth m = 1, the capacitor discharge is the most severe, leading to the maximum voltage ripple. Therefore, time parameters t₂ and t₃ are defined as

$$t_2={\displaystyle \frac{\arcsin \left(2/3\right)}{\mathsf{\omega }}}$$

(6)

$$t_3={\displaystyle \frac{\mathsf{\pi }-\arcsin \left(2/3\right)}{\mathsf{\omega }}}$$

(7)

To ensure reliable operation, the maximum allowable voltage ripple across any capacitor should not exceed 10% of its nominal voltage (V_N). Consequently, capacitor C₂ must satisfy the following dimensional constraint:

$$C_2\ge {\displaystyle \frac{\Delta Q_{C_2}}{10\%V_{\mathrm{N}}}}$$

(8)

During the positive half-fundamental frequency cycle, as delineated in Table 1 and Figure 2, capacitor C_dc1 maintains a continuous parallel connection with the DC power supply, effectively stabilizing its voltage. In contrast, capacitor C_dc2 experiences voltage reduction only during E or 0 output levels, when energy transfers to capacitors C₁ and C₂. Nevertheless, the voltage fluctuation across C_dc1 remains substantially lower than that of C₂. For design standardization purposes, capacitor C_dc2 can be dimensioned identically to C₂. During the negative half-fundamental frequency cycle, the charge–discharge characteristics of C_dc2 and C₁ exhibit symmetrical behavior relative to C_dc1 and C₂, respectively, following analogous principles that require no further elaboration.

3.4. Three-Phase Configuration of the Proposed Inverter

Figure 7 presents the three-phase configuration of the proposed inverter. In this arrangement, all three phases share common central components: the DC power supply V_dc, switching devices T₁ and T₂, diodes D₁ and D₂, and capacitors C_dc1 and C_dc2. While the fundamental operational principles remain consistent with the single-phase implementation, the three-phase structure enables flexible switching strategies that can significantly enhance performance characteristics.

To optimize the voltage ripple across capacitors C_dc1 and C_dc2, the conduction states of transistors T₁ and T₂ can be strategically coordinated based on the three-phase modulating waves defined by Equation (9):

$$\left\{\begin{array}{l}{V}_{\mathrm{refA}}=m\sin \left(\mathsf{\omega }t\right)\hfill \\ V_{\mathrm{refB}}=m\sin \left(\mathsf{\omega }t-2/3\mathsf{\pi }\right)\hfill \\ V_{\mathrm{refC}}=m\sin \left(\mathsf{\omega }t+2/3\mathsf{\pi }\right)\hfill \end{array}\right.$$

(9)

where V_refA, V_refB, and V_refC are three-phase modulation waves, m is the modulation depth, and ω is the angular frequency.

As depicted in Figure 8, the fundamental frequency period can be systematically partitioned into six distinct sectors based on the instantaneous amplitudes of the three-phase modulation waves.

Table 3. List of the on–off states of switching devices in each sector.

Sector	I	II	III	IV	V	VI
Condition	VrefA > 0 VrefB < 0 VrefC > 0	VrefA > 0 VrefB < 0 VrefC ≤ 0	VrefA > 0 VrefB ≥ 0 VrefC < 0	VrefA ≤ 0 VrefB > 0 VrefC < 0	VrefA < 0 VrefB > 0 VrefC ≥ 0	VrefA < 0 VrefB ≤ 0 VrefC > 0
Switching devices	T1 off T2 on	T1 on T2 off	T1 off T2 on	T1 on T2 off	T1 off T2 on	T1 on T2 off

comprehensively details the sector division criteria and the corresponding switching states for power devices. To minimize capacitor voltage ripples, a complementary switching pattern is implemented: switching device T₂ is activated (ON), while T₁ remains deactivated (OFF) throughout Sectors I, III, and V; conversely, T₁ is activated, and T₂ deactivated during Sectors II, IV, and VI.

This sectorial switching approach introduces a significant operational distinction between single-phase and three-phase implementations. While T₁ and T₂ operate at fundamental frequency in the single-phase inverter, their switching frequency increases up to threefold in the three-phase configuration. This elevated switching frequency facilitates more frequent parallel connections between capacitors C_dc1/C_dc2 and the DC power source, enabling accelerated charging and discharging cycles. Consequently, it can result in markedly reduced voltage ripple magnitude across the capacitors.

3.5. Topological Comparative Assessment

A comparative analysis has been conducted between the proposed inverter topology and several seven-level inverters introduced in recent literature. Using the single-phase configuration as the basis for comparison, this assessment examines critical design parameters, including required DC power sources, semiconductor device count (switching devices and diodes), maximum blocking voltage and the total voltage stress (TVS). The TVS can be calculated as follows:

$$\mathrm{TVS}={\displaystyle \frac{{\displaystyle \sum _{i=1}^9{V}_{{\mathrm{S}}_i}}+(V_{{\mathrm{T}}_1}+V_{{\mathrm{T}}_2}+V_{{\mathrm{D}}_1}+V_{{\mathrm{D}}_2})}{V_{\mathrm{dc}}}}$$

(10)

where V_Si, V_Ti, and V_Di denote the voltage stress on the power devices, and V_dc represents the DC-source voltage.

As summarized in

Table 4. Comparison of the proposed 7L-SDS-TVG inverter with existing seven-level topologies.

Single-Phase Configuration						Three-Phase Configuration
Topology	Nsw	Nd	Nc	Maximum Blocking Voltage	TVS/G	Total Number	TVS/G	Share the DC Power Supply
Ref. [11]	8	0	3	1	9/1.5	3 ∗ (Nsw + Nd + Nc)	27/1.5	Yes
Ref. [12]	10	0	3	1	8.5/1.5	3 ∗ (Nsw + Nd + Nc)	25.5/1.5	Yes
Ref. [13]	10	0	4	1	11/1.5	3 ∗ (Nsw + Nd + Nc)	33/1.5	Yes
Ref. [14]	9	0	1	1	6/1.5	3 ∗ (Nsw + Nd + Nc)	18/1.5	No
Ref. [15]	16	0	2	1	16/3	3 ∗ (Nsw + Nd + Nc)	48/3	No
Ref. [16]	10	1	2	3	20/3	3 ∗ (Nsw + Nd + Nc)	60/3	No
Ref. [17]	9	4	2	3	17/3	3 ∗ (Nsw + Nd + Nc)	51/3	No
Ref. [18]	9	2	3	3	17/3	3 ∗ (Nsw + Nd + Nc)	51/3	No
Ref. [19]	12	0	2	2	16/3	3 ∗ (Nsw + Nd + Nc)	48/3	No
Proposed	11	2	4	2	20/3	2.6 ∗ Nsw + Nd + 2 ∗ Nc	52/3	Yes

Note: N_sw, N_d, N_c, TVS, and G denote the number of switching devices, the number of diodes, the number of capacitors, total voltage stress, and the output voltage gain, respectively. Additionally, in terms of the maximum blocking voltage on the power devices, the topology in Ref. [15] exhibits the lowest device voltage stress, while the stress in Refs. [16,17,18] is the highest. The proposed topology is comparable to that in Ref. [19], lying between Ref. [15] and Refs. [16,17,18]. Regarding the total voltage stress, the proposed single-phase topology shows a relatively high total voltage stress. However, in the three-phase topology, thanks to the structural advantage that some power devices can be shared, the total voltage stress is close to that in Refs. [17,18] and is thus significantly reduced.

, the proposed topology demonstrates significant advantages. While the inverter topologies presented in Refs. [11,12,13,14] utilize fewer switching devices than the proposed design, they achieve a maximum voltage gain of only 1.5 times the input DC voltage—substantially limiting their voltage amplification capabilities. Conversely, the topology described in Ref. [15] delivers enhanced voltage gain performance but at the considerable expense of power device count, requiring significantly more components than the proposed topology. The inverters detailed in Refs. [16,17,18,19] achieve triple voltage gain with comparatively fewer switching components, representing a notable achievement in component optimization. However, these topologies exhibit a critical limitation: when implemented in three-phase configurations, they necessitate three separate DC power supplies—a constraint that substantially increases system complexity, cost, and volume.

More importantly, in a three-phase system, the proposed 7L-SDS-TVG inverter can share the DC power source, capacitors C_dc1 and C_dc2, switching devices T₁ and T₂, as well as diodes D₁ and D₂. This strategic component sharing significantly reduces the overall component count. Furthermore, as demonstrated in the previous section, the coordinated switching strategy in the three-phase configuration results in markedly lower voltage ripples across capacitors C_dc1 and C_dc2, enhancing output waveform quality and system reliability.

4. Simulation Results

To verify the feasibility of the proposed 7L-SDS-TVG inverter, a simulation analysis is conducted using the MATLAB/Simulink platform (R2024b, 64-bit(win64), 22 August 2024). The simulation parameters are listed in

Table 5. List of simulation parameters.

Parameter	Value
Three-phase grid voltage	380 V
DC source	120 V
Rated phase current amplitude	15 A
Cdc1, Cdc2	6600 μF
C1, C2	6600 μF
Fundamental frequency	50 Hz
Carrier frequency	10 kHz
Filter inductors	5 mH
Load resistor + inductor	(0~200 Ω) + (0~100 mH)
S1~S9 and T1, T2	AIKW20N60CT (Infineon)
D1 and D2	IDW30C65D1(Infineon)

. Given that the maximum allowable voltage ripple across the capacitor is 10%, the capacitance value of C₂ is calculated to be approximately 5967 μF based on Equations (5) and (8). To provide sufficient design margin, a 6600 μF capacitor is selected for C₂. For consistency and balanced performance, capacitors C_dc1, C_dc2, and C₁ are also chosen with the same capacitance value of 6600 μF.

4.1. Simulation Results for the Single-Phase Configuration

Figure 9 presents simulation results for the single-phase 7L-SDS-TVG inverter operating at a modulation depth of m = 0.9 under purely resistive loading conditions (R = 22 Ω). Figure 9a illustrates the output voltage and current waveforms, demonstrating that the fundamental component of the load voltage achieves an amplitude of approximately 324 V, while the load current reaches approximately 15 A. These results conclusively validate the inverter’s triple voltage gain capability—a distinguishing feature of the proposed topology.

The capacitor voltage waveforms, depicted in Figure 9b, reveal that voltages across capacitors C_dc1 and C_dc2 maintain stable operation within a 112–120 V range, while C₁ and C₂ exhibit voltage ripples between 110 and 120 V. Throughout the entire operational cycle, all four capacitors maintain voltage stability within their designated operating ranges. Notably, the simulation results demonstrate symmetrical behavior between C_dc1/C_dc2 and C₁/C₂ during both positive and negative half-cycles, indicating well-balanced energy distribution. Figure 9c shows the current waveforms of C₁ and C₂. The presence of high-frequency components in the current is attributed to the charging current, which is closely related to the output level state of the inverter.

Under the conditions of a single-phase inverter with a pure resistive load, a modulation index of m = 0.9, and a rated output current amplitude of 15 A, the output power of the inverter is calculated as p = 2430 W. Figure 9d shows the distribution of conduction and switching losses for each power device using PLECS software (standalone-4-2-4_win64). From this, the total loss of the power devices is derived as 43.55 W, resulting in an inverter efficiency of 98.2%. As can be seen from Figure 9d, S5, S6, S8, and S₉ exhibit higher power loss. This is because these four power devices simultaneously carry both the load current and the capacitor charging current, resulting in larger currents flowing through them and consequently increased power loss. In contrast, T₁, T₂, D₁, and D₂ show very low switching loss, because they operate at line frequency with low switching frequency, which leads to minimal switching loss.

Maintaining the modulation depth at m = 0.9 while transitioning to a resistive-inductive load (R + L = 22 Ω + 50 mH), the inverter’s response characteristics are illustrated in Figure 10. The output voltage and current waveforms in Figure 10a exhibit a distinct phase displacement between them, accurately reflecting the power factor angle introduced by the inductive component. Figure 10b presents the capacitor voltage waveforms, demonstrating that all four capacitors—C_dc1, C_dc2, C₁, and C₂—achieve voltage self-balancing within a fundamental frequency cycle.

To evaluate the dynamic performance of the proposed inverter, the modulation depth m was subjected to step changes as illustrated in Figure 11. When m transitions from 0.9 to 0.6, the output voltage waveform correspondingly changes from a 7-level to a 5-level waveform. Subsequently, as m is further reduced to 0.3, the output voltage reconfigures to a 3-level waveform. These results clearly demonstrate the inverter’s capability to operate across the full modulation index range with rapid transient response characteristics. Furthermore, Figure 11b reveals an inverse relationship between modulation depth and capacitor voltage ripple magnitude—as the modulation depth decreases, the capacitor voltage ripple proportionally diminishes.

4.2. Simulation Results for the Three-Phase Configuration

To validate the grid integration capabilities of the proposed inverter, a grid-connected simulation model was implemented based on the three-phase configuration depicted in Figure 7. The system employs a sophisticated voltage-current cascaded control strategy with dual closed-loop architecture—an approach widely adopted in grid-connected converter systems [22,23]. The controller reference parameters were configured with active current command I_d* = 15 A and reactive current command I_q* = 0 A, establishing unity power factor operation where the inverter exclusively delivers active power to the power grid.

Figure 12 presents the key simulation results under these conditions. As evidenced in Figure 12a, the grid voltage and grid-connected current waveforms maintain precise phase alignment, with current defined as positive when flowing from the inverter into the grid. This synchronization confirms successful implementation of the control algorithm and demonstrates the inverter’s capability to accurately track command references while maintaining high power quality at the point of grid interconnection. The capacitor voltage dynamics illustrated in Figure 12b reveal consistent voltage self-balancing behavior across all energy storage elements. Of particular significance is the charging pattern observed for capacitor C_dc1, which undergoes three complete charging cycles within each fundamental frequency period. This tripled charging frequency corresponds precisely with the theoretical analysis presented in Section 2, thereby experimentally validating the mathematical framework developed for the proposed topology. The Fourier analysis of output current is shown in Figure 12c. It can be seen the THD of the output current is relatively low, and the harmonic components are mainly distributed around the carrier frequency and its multiples.

5. Experimental Verification

To verify the feasibility of the proposed topology, a three-phase 7L-SDS-TVG inverter experimental platform was constructed in the laboratory, as illustrated in Figure 13. The Typhoon HIL 402 served as the main controller, implementing the control algorithm and generating PWM signals. Detailed experimental parameters are provided in

Table 6. List of experimental parameters.

Parameter	Value
DC-source	120 V
Cdc1, Cdc2	6600 μF
C1, C2	6600 μF
Fundamental frequency	50 Hz
Carrier frequency	5 kHz
Filter inductors	5 mH
Load resistor + inductor	(0~200 Ω) + (0~100 mH)
S1~S9 and T1, T2	AIKW20N60CT (Infineon)
D1 and D2	IDW30C65D1 (Infineon)

.

Initial testing was conducted under steady-state operating conditions with modulation depth m = 0.9 and resistive load R = 40 Ω. The experimental waveforms are presented in Figure 14.

Figure 14a illustrates the three-phase output voltage waveforms, each exhibiting distinct seven-level stepped transitions with minimal distortion. Spectral analysis confirms that the fundamental component achieves an amplitude of approximately 320 V, experimentally validating the topology’s voltage triple-boosting capability.

The corresponding three-phase output current waveforms, shown in Figure 14b, demonstrate exceptional harmonic performance with near-sinusoidal characteristics, indicating effective filtering and low total harmonic distortion under nominal operating conditions.

Figure 14c,d present the voltage profiles across capacitors C₁, and C₂, respectively. Notably, all capacitor voltages maintain stable oscillation around their nominal 120 V reference value despite the absence of dedicated balancing control loops. This empirically confirms the inherent self-balancing capability theoretically predicted for the proposed switched-capacitor network.

To evaluate transient performance, a dynamic response test was conducted by implementing a step change in modulation depth from m = 0.6 to m = 0.9 at time instant t₀ while maintaining load resistance at R = 40 Ω. The resultant transient waveforms are documented in Figure 15.

The experimental results demonstrate that at the transition point, the output voltage waveform instantaneously reconfigures from a five-level to a seven-level waveform, as evidenced when comparing Figure 15a,b. Concurrently, the output current amplitude increases proportionally with minimal overshoot, exhibiting excellent dynamic response characteristics. This confirms the inverter’s capability to handle sudden reference changes.

6. Conclusions

This paper proposes a triple voltage gain seven-level inverter utilizing switched capacitor technology. Initially, the fundamental working principle of the inverter is thoroughly expounded, establishing its operational framework. Building upon this foundation, a simplified carrier modulation method is then proposed alongside a comprehensive analysis of the capacitor voltage self-balancing mechanism. Through comparative assessment with similar topologies, the proposed inverter demonstrably achieves the higher voltage gain while requiring fewer power devices—a distinct advantage that becomes particularly significant in three-phase implementations where component sharing substantially reduces overall system complexity. To validate these theoretical advantages, both single-phase and three-phase simulation models have been meticulously developed, with the resultant performance characteristics subsequently confirmed through experimental testing on a laboratory prototype.