Search Results (146)

This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems. Full article

p-GaN gate enhancement-mode GaN High Electron Mobility Transistors (HEMTs) are promising normally off power devices, but their high-temperature reliability is strongly affected by the gate-contact scheme. This study compares Pd ohmic and Ni Schottky p-GaN gate HEMTs fabricated on the same GaN-on-Si epitaxial platform by combining temperature-dependent electrical characterization, post-temperature-dependent-test (TDT) room-temperature recovery analysis, and thermoreflectance thermal mapping. Electrical measurements were performed in a temperature range from room temperature to 500 °C using gate leakage, transfer, and output characteristics, while thermal maps were obtained before and after the TDT under identical bias conditions. The Pd ohmic devices exhibited a higher initial current drive but a larger operating gate-current penalty and greater degradation of normalized on-state characteristics at elevated temperature. After the TDT, reduced transconductance and maximum drain current were accompanied by weaker active-channel heating, indicating degradation-type cooling associated with reduced gate–channel modulation efficiency. In contrast, the Ni Schottky devices showed a lower gate-current penalty and better normalized output retention up to approximately 300 °C; however, post-TDT increases in transconductance and drain current occurred together with degraded subthreshold swing and persistent localized heating, indicating apparent on-state activation with weakened gate/depletion control. These results show that p-GaN gate reliability should be assessed through coupled electrical and thermal signatures rather than single electrical or thermal metrics. Full article

Molybdenum disulfide (MoS₂) is a compelling candidate for visible-light detection due to its strong optical absorption and tunable bandgap, yet the development of high-performance MoS₂ photodetectors remains limited by challenges in scalable integration, low-voltage operation, and efficient photoresponse. Here, we report an ion-gel-assisted transfer strategy that enables the fabrication of large-area MoS₂/ion gel films that are suitable for low-power phototransistor applications. The transferred MoS₂/ion gel stack is laminated onto an indium-tin-zinc-oxide (ITZO) layer on a glass substrate to fabricate a MoS₂/ITZO heterojunction phototransistor, with the ion gel serving as an ultrathin, high-capacitance gate dielectric. The resulting phototransistor exhibits a field-effect mobility of 4.12 cm²/Vs, an on/off current ratio of 4.9 × 10⁵, and a subthreshold swing of 0.17 V/dec. Under 635, 520, and 405 nm illumination with a power density of 4.5 mW/cm², it achieves responsivities of 0.58, 1.82, and 5.56 A W⁻¹ and detectivities of 5.90 × 10⁹, 1.86 × 10¹⁰, and 5.68 × 10¹⁰ Jones, respectively. These findings demonstrate that the ion-gel-assisted transfer process offers a robust route to high-performance, low-voltage photodetection and provides a promising platform for next-generation optoelectronic technologies. Full article

Leadership research has long focused on the “high-visibility, high-responsibility” heroic leadership paradigm, while systematically neglecting the critical quadrant of “low-visibility, high-responsibility” (HRLV) leadership. Through ethnographic observation and in-depth interviews with Chinese dragon-boat helmsters as an extreme case, this study constructs a Helmsmanship Leadership theoretical framework, revealing the core operating mechanisms of HRLV leadership. The framework comprises 3 interlocking dimensions: Fade—achieving silent coordination through sub-threshold interventions, decoupling influence from visibility; Fail-safe—safeguarding the system’s floor through preventive authority, with success marked by the “absence of disaster”; Fit—situational attunement and going with the flow, serving as a conduit for environmental forces rather than a controller. The systemic coupling of these 3 dimensions enables helmsters to sustain collective survival under extreme conditions of zero-error tolerance and high interdependence. This study decouples leadership from visibility, revealing how influence is generated under conditions of “not being seen.” It expands the theoretical boundaries of relational leadership, extending relationality from interpersonal interaction to the leader’s relationship with the system, with risk, and with the environment. It contributes to leadership theory a “visibility-responsibility” analytical framework, revealing the core characteristics and operating logic of the long-overlooked leadership form of “high-responsibility, low-visibility.” In doing so, it provides new analytical tools for understanding governance in high-risk, highly interdependent systems. Full article

This paper presents a nanowatt-scale operational transconductance amplifier (OTA) and an electronically tunable third-order low-pass filter (LPF) designed for energy-constrained biomedical signal conditioning. The circuits are implemented in a 65 nm CMOS process and verified through comprehensive schematic-level simulations. Biased in the deep subthreshold region at 1 nA, the OTA achieves a 50 dB low-frequency gain, a 225 Hz unity-gain bandwidth at 10 pF load capacitance and an input-referred noise floor of 1.55 μV/√Hz, with a total power consumption of only 1.75 nW. The integrated third-order LPF provides a wide tuning range (37–668 Hz) via bias current modulation, exhibiting excellent linearity with a THD of 0.059% and a 65.3 dB dynamic range. Monte Carlo and PVT corner analyses demonstrate the design’s theoretical robustness against process variations and environmental fluctuations. ECG signal simulations validate the circuit’s effectiveness in suppressing high-frequency artifacts while preserving morphological integrity, providing a proof-of-concept for ultra-low-power wearable healthcare architectures. Full article

In an era marked by rising stress-related disorders and cardiovascular morbidity, understanding how the brain and heart adapt to environmental, physiological, and social stressors has become an urgent biomedical priority. This review advances an integrative framework centered on sociostasis, defined as the dynamic regulation of physiological state through social interaction, and its intersection with hormesis, a biphasic adaptive response to controlled stress that enhances resilience. We focus on four evolutionarily conserved neuropeptides, vasopressin, oxytocin, corticotropin-releasing hormone, and the urocortins, which serve as molecular bridges linking social behavior, neuroendocrine signaling, autonomic regulation, and cardiovascular function. Operating within an organized autonomic architecture, these systems calibrate responses to acute and chronic stress. Their context-dependent synergy enables adaptive flexibility under manageable challenge but may promote maladaptive cardiovascular remodeling when chronically dysregulated. Genetic vulnerability, developmental adversity, and persistent psychosocial stress can shift neuroendocrine–autonomic set points, increasing susceptibility to hypertension, endothelial dysfunction, and stress-induced cardiomyopathy. Conditioning and preconditioning paradigms illustrate how repeated exposure to subthreshold stressors primes cardiovascular tissues for future insults, enhancing ischemic tolerance and adaptive gene expression. We propose that cardiovascular hormesis depends not only on stimulus intensity but also on the integrity of neuroautonomic regulatory mechanisms that support recovery and flexibility. Vagal efficiency, a dynamic index of cardioinhibitory regulation, is discussed as a potential translational metric of adaptive capacity. By integrating molecular, physiological, and psychosocial perspectives, this framework conceptualizes cardiovascular resilience as an emergent property of coordinated hormetic signaling, neuropeptidergic modulation, autonomic regulation, and social buffering. Translational implications include peptide-based therapies, autonomic biofeedback, and behavioral interventions designed to enhance stress adaptability. Full article

In this study, an ultra-low-voltage operational transconductance amplifier (OTA) operating from a 0.3 V supply, designed in a 45 nm CMOS process, is presented. To overcome the severe headroom constraints, the design employs a bulk-driven differential input stage combined with a current-reuse strategy, effectively enhancing transconductance while operating all transistors in the subthreshold region. This approach enables a rail-to-rail input common-mode range. A multipath Miller zero cancellation compensation technique ensures stability. The resulting OTA achieves an open-loop gain of 44.2 dB and a remarkable common-mode rejection ratio (CMRR) of 87.5 dB, all while consuming 23.3 nW of power. With a gain–bandwidth product of 9.9 kHz, a power supply rejection ratio (PSRR) of 41.1 dB, and an input noise of 1.0 μV/√Hz, this design is highly suitable for energy-constrained, low-frequency applications such as biomedical sensor interfaces and IoT nodes. Full article

This paper investigates the degradation characteristics of a DC/DC converter operating under cold redundancy conditions when subjected to total ionizing dose (TID) effects. An optimized RCC isolated auxiliary power supply circuit was evaluated through ⁶⁰Co γ-ray irradiation up to 100 krad(Si) at dose rates of 3.89, 8.89, and 13.89 rad (Si)/s, with electrical characterizations performed at both the system level and the device level, focusing on the critical VDMOS transistors. The results indicate that the main output voltage and conversion efficiency remain essentially stable after irradiation, whereas the auxiliary supply voltage and efficiency degrade significantly, leading to a pronounced reduction in the controller supply margin. Device-level measurements reveal a negative threshold voltage shift of approximately 0.5–1.0 V with clear dose-rate dependence, while the subthreshold swing shows no obvious variation, suggesting that the degradation is primarily dominated by oxide-trapped charge effects. In addition, a substantial increase in drain current at low gate voltages is observed, which may further exacerbate restart risks under cold redundancy conditions. These findings demonstrate that the auxiliary power supply and startup margin constitute critical vulnerability points of cold-redundant DC/DC converters under TID stress and should therefore be primary targets for radiation-hardened design. Full article

In this work, we report the first systematic examination of how the In composition in the intrinsic In_xGa_1-xAs layer and the p-type doping concentration in the p-type GaAsSb layer affect the device performance of side-gate p-GaAs_0.5Sb_0.5/i-In_xGa_1-xAs/n-In_0.53Ga_0.47As TFETs, using the technology computer-aided design (TCAD) simulations with a non-local band-to-band model. By tuning these two parameters, a moderate staggered alignment is achieved, enabling self-off operation at zero gate bias while maintaining high on-current. This tunability is an intrinsic and significant advantage of the p-GaAsSb/i-In_xGa_1-xAs heterojunction that has not been previously explored. It is found that the best device performance does not occur in the TFET with an In composition of 0.53 in the intrinsic layer, which is lattice-matched to the InP substrate, but rather occurs in the device with a higher In composition of around 0.59 in the InGaAs layer, which has been verified by experimental data to some extent. Optimal parameter combinations yield a minimum subthreshold swing of 13.51 mV/dec and an ON-state current of 35.39 μA/μm at V_DS = V_GS = 0.5 V due to the enhanced tunneling capability. Full article

At an ultra-thin 3 nm SnO₂ channel thickness, a record-high effective mobility (µ_eff) of 301 cm²/V·s, field-effect mobility (µ_FE) of 304 cm²/V·s, and a sharp subthreshold swing (SS) of 201 mV/decade are achieved at a high carrier density (N_e) of 5 × 10¹² cm⁻². These excellent transport properties are attributed to ultraviolet (UV) light annealing. The resulting µ_eff is significantly higher than that of Molybdenum Disulfide (MoS₂) and Tungsten Diselenide (WSe₂), and is more than twice that of single-crystalline Si channel transistors at the same quasi-two-dimensional (2D) thickness of 3 nm (equivalent to five monolayers of MoS₂). UV annealing not only enhances µ_eff and µ_FE but also sharpens the SS, which is crucial for low-power operation. This improved SS is attributed to reduced scattering from charged interface traps, as supported by µ_eff-N_e analysis, thereby increasing the transistor’s mobility. The realization of such high-mobility devices at a quasi-2D thickness of only 3 nm is of particular importance for the further downscaling of ultra-thin-body transistors for high-speed computing and monolithic three-dimensional (M3D) integration. Furthermore, the wide bandgap of SnO₂ (3.7 eV) enables operation at relatively high voltages, paving the way for pioneering ternary logic applications. Full article

In the last few years, Thin Film Transistors (TFTs) based on materials such as amorphous Indium–Gallium–Zinc Oxide (a-IGZO) have gained interest in large-area and low-cost electronics due to their high carrier mobility, high on/off current ratio, low off-state current, and steep subthreshold slope. These characteristics make IGZO TFTs suitable for radio-frequency identification (RFID) tags, analog-to-digital converters (ADCs), logic circuits, sensors, and analog components, including operational amplifiers (OPAMPs). This work presents the implementation and characterization of an OPAMP based on n-type a-IGZO TFTs fabricated on glass substrate. Two previously reported design strategies were integrated: a positive feedback network to increase the output impedance and a topology to enhance the transconductance of the driver transistors, both in the differential input stage. A gain of 26 dB, a bandwidth of 2.4 kHz, a gain–bandwidth product (GBWP) of 48 kHz, and a phase margin of 64° were obtained, which confirms the reliability of the design and the fabrication process. Full article

This study aims to implement universal logic gates using polarity control within a single silicon transistor structure. For this purpose, a reconfigurable transistor based on a p-i-n structure featuring two polarity gates (PGs) and one control gate was proposed, and its electrical characteristics and logic-in-memory (LIM) circuit operations were analyzed via two-dimensional technology computer-aided design simulations. The proposed device could be perfectly reconfigured into p-channel or n-channel modes because virtual doping effects could be induced according to the polarity of the PG voltage. Moreover, based on the positive feedback and latch-up phenomena, a steep subthreshold swing of approximately 1 mV/dec and a high ON/OFF current ratio of the order of 10¹⁰ were achieved. Building on these characteristics, we successfully verified NAND LIM operation in the p-channel mode and NOR LIM operation in the n-channel mode by connecting two of the proposed devices in parallel. The reconfigurable silicon transistor proposed in this study could perform both NAND and NOR LIM operations while sharing the same device structure and can be expected to play a key role in implementing high-density, low-power LIM systems in the future. Full article

An InGaAs/GaAsSb heterojunction dopingless Tunnel FET with a heterogate dielectric is proposed and investigated in this work, aiming to extend the advantages of dopingless TFETs in low-power applications. By employing the InGaAs/GaAsSb heterojunction with a quasi-broken gap energy band structure in dopingless TFET, the HDL-TFET achieves extremely high band-to-band tunneling efficiency. A dual-electrode structure is adopted to improve carrier distribution, which further enhances tunneling efficiency and increases on-state current (I_ON). To suppress off-state tunneling, optimize ambipolar current, and reduce parasitic capacitance, a heterogate dielectric structure is introduced. Results show that the HDL-TFET exhibits an I_ON up to 8.33 × 10⁻⁵ A/μm and a steep subthreshold swing (SS_avg) of 10.18 mV/dec at a low operating voltage of 0.5 V. It also achieves an off-state current (I_OFF) as low as 3.42 × 10⁻¹⁵ A/μm and I_ON/I_OFF ratio up to 2.44 × 10¹⁰, with no obvious ambipolar current. Compared with previously reported works, the proposed HDL-TFET demonstrates significant advantages. Additionally, the introduction of the heterogate dielectric and dual-electrode structure significantly improves the RF performance of the device, with a peak transconductance (G_m) of 333 μS/μm, and a peak cutoff frequency (f_T) and gain bandwidth product (GBP) up to 64 GHz and 49 GHz, respectively. Full article

This paper presents a new operational transconductance amplifier (OTA) design for batteryless biomedical front-ends. The proposed OTA operates in the subthreshold region and utilizes self-cascode devices to achieve ultra-low power, low noise, and a high common-mode rejection ratio ($CMRR$). Post-layout simulations in Cadence, using 45 nm CMOS technology with 0.9 V supply voltage, show a power consumption of 49.3 nW, a $CMRR$ of 144.9 dB, an input-referred noise of 4.51 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$ integrated over 0.5–208 Hz, and a noise efficiency factor of 1.023 with a core silicon area of 0.00138 mm². Using the proposed OTA, we implemented a 10-channel neural recording amplifier for Local Field Potentials (LFPs) based on a capacitively coupled, capacitive-feedback (CC-CF) topology with a body-driven pseudo-resistor high-pass path. The system achieves a total $CMRR$ ≥ 70 dB and an estimated power of 494.2 nW for 10 channels. Compared with prior art, the proposed OTA offers competitive noise efficiency and common-mode rejection at lower power, making it a viable building block for batteryless neural and biomedical sensing front-ends. Full article

We present an analytic compact model for p-type cylindrical gate-all-around (GAA) MOSFETs in the quasi-ballistic/ballistic regime, incorporating drain-induced barrier lowering (DIBL). To describe the potential profile, an undetermined parameter is used to represent the channel potential, which is derived from the Laplace equation in the subthreshold region and from Gauss’s law combined with quantum statistics in the inversion region. A smoothing function is applied to this parameter to ensure a continuous source—drain current across all operating regions. The current model is based on the Landauer approach and captures both quasi-ballistic/ballistic transport and quantum-confinement effects. It is validated against non-equilibrium Green’s function (NEGF) simulation results and implemented in Verilog-A for SPICE circuit-level simulation of a CMOS inverter, demonstrating its applicability for nanoscale design. Full article