Temperature-Dependent Electro-Thermal Characteristics of E-Mode GaN HEMTs with Ohmic and Schottky Gates

Abstract

p-GaN gate enhancement-mode GaN High Electron Mobility Transistors (HEMTs) are promising normally off power devices, but their high-temperature reliability is strongly affected by the gate-contact scheme. This study compares Pd ohmic and Ni Schottky p-GaN gate HEMTs fabricated on the same GaN-on-Si epitaxial platform by combining temperature-dependent electrical characterization, post-temperature-dependent-test (TDT) room-temperature recovery analysis, and thermoreflectance thermal mapping. Electrical measurements were performed in a temperature range from room temperature to 500 °C using gate leakage, transfer, and output characteristics, while thermal maps were obtained before and after the TDT under identical bias conditions. The Pd ohmic devices exhibited a higher initial current drive but a larger operating gate-current penalty and greater degradation of normalized on-state characteristics at elevated temperature. After the TDT, reduced transconductance and maximum drain current were accompanied by weaker active-channel heating, indicating degradation-type cooling associated with reduced gate–channel modulation efficiency. In contrast, the Ni Schottky devices showed a lower gate-current penalty and better normalized output retention up to approximately 300 °C; however, post-TDT increases in transconductance and drain current occurred together with degraded subthreshold swing and persistent localized heating, indicating apparent on-state activation with weakened gate/depletion control. These results show that p-GaN gate reliability should be assessed through coupled electrical and thermal signatures rather than single electrical or thermal metrics.

1. Introduction

GaN-based High Electron Mobility Transistors (HEMTs) are attractive for power electronics because the AlGaN/GaN heterointerface supports a highly conductive two-dimensional electron gas (2DEG), enabling high current density and low on-state resistance [1,2]. However, conventional AlGaN/GaN HEMTs are inherently depletion-mode devices because the polarization-induced 2DEG exists even at zero gate bias. For power-switching applications, enhancement-mode operation is generally preferred to ensure fail-safe behavior and to simplify gate-driven design [3,4,5,6]. Recent progress in GaN-, AlGaN-, and AlN-based HEMTs has continued to improve device performance through epitaxial and barrier engineering, including hybrid AlN nucleation layers and thick-AlN-barrier AlN/GaN heterostructures [7,8]. Nevertheless, for normally off p-gaN gate HEMTs, the gate stack remains a critical reliability bottleneck under high-temperature and high-field operation.

Among the normally off approaches, p-GaN gate technology has become one of the most practically important solutions. The p-GaN cap lifts the conduction band beneath the gate and depletes the 2DEG at equilibrium. A positive gate bias restores the channel, enabling normally off operation [3,5,6]. The gate-contact scheme, however, plays a decisive role in determining threshold voltage, gate leakage, gate-drive window, and reliability. Depending on the metal/p-GaN barrier profile, p-GaN gate HEMTs can be broadly classified into ohmic-gate and Schottky-gate devices [9,10,11,12].

In ohmic-gate or gate-injection-type (GIT) devices, forward gate bias can induce hole injection from the p-type gate region into the heterostructure. This hole injection increases the electron density in the channel through conductivity modulation, thereby enhancing the drain current while maintaining normally off behavior [11]. In Schottky-gate devices, the metal/p-GaN Schottky barrier suppresses gate injection and reduces gate current. Schottky-gate p-GaN HEMTs typically offer higher threshold voltage, higher gate-breakdown voltage, and larger gate-voltage swing than ohmic-gate p-GaN HEMTs, but the allowable long-term gate bias remains limited by gate/p-GaN interface degradation under high electric fields [9,11,12].

Previous studies have clarified several important aspects of ohmic and Schottky-type p-GaN gate HEMTs, including gate-current magnitude, gate driving requirements, threshold-voltage behavior, Schottky gate leakage mechanisms, gate breakdown, and p-GaN-related current instability under high-temperature operation [11,13,14,15,16]. These studies have established that the gate-contact scheme strongly affects the electrical reliability of p-GaN gate HEMTs. However, most prior comparisons have focused primarily on scalar electrical parameters, whereas the spatial consequence of gate-contact-dependent degradation has been less explored. In particular, it remains insufficiently understood how post-temperature-dependent-test (TDT) changes in transfer and output characteristics are coupled with changes in heat-source topology observed by thermal mapping. This lack of correlation between post-TDT electrical degradation and spatial thermal redistribution limits the physically complete assessment of gate-stack reliability.

In this study, we address this gap by correlating electrical degradation parameters with thermoreflectance thermal maps in Pd ohmic and Ni Schottky p-GaN gate e-mode HEMTs. The central hypothesis is that gate-contact-dependent degradation is reflected not only in scalar electrical parameters, such as gm, Ron, IG/ID, SS, and Ioff, but also in the spatial redistribution framework in which electrical changes and thermoreflectance signatures are interpreted as coupled reliability indicators.

2. Experimental Section

2.1. Device Fabrication

Two p-GaN gate enhancement-mode HEMT structures were fabricated: a Pd-based ohmic-gate device and a Ni-based Schottky-gate device. The devices investigated in this work were fabricated on a GaN HEMT-on-Si epitaxial wafer, as shown in Figure 1a. The epitaxial structure consisted of a Si(111) substrate, a 200 nm nucleation layer, a 3000 nm transition layer, a 2000 nm high-resistivity buffer layer, a 200 nm GaN channel layer, a 0.7 nm AlN spacer, a 15 nm AlGaN barrier with an Al composition of 20%, and an 80 nm p-GaN cap layer. The same epitaxial platform was used for both Pd ohmic and Ni Schottky gate devices, allowing the effect of the gate-contact scheme to be compared without changing the underlying channel and buffer structures.

The fabrication process depicted in Figure 1b was designed to isolate the gate-contact effect while maintaining identical source/drain and passivation processes. First, mesa isolation was performed by inductively coupled plasma reactive-ion etching (ICP-RIE) using Cl₂/BCl₃ chemistry. The source/drain access regions were then recessed by ICP-RIE, using BCl₃ to remove the p-GaN cap in the source/drain contact regions. Source and drain ohmic contacts were formed by electron-beam evaporation of Ti/Al/Ni/Au (20/100/50/50 nm), followed by rapid thermal annealing at 850 °C for 30 s. The gate metal was subsequently defined with two different metallization schemes: Pd for the ohmic-gate device and Ni for the Schottky-gate device. In this work, post-gate annealing was intentionally omitted to evaluate the response of as-deposited Pd/p-GaN and Ni/p-GaN gate contacts under an identical high-temperature TDT sequence. Therefore, the post-TDT changes discussed in this work should not be interpreted as universal characteristics of fully process-optimized commercial p-GaN gate HEMTs. Rather, they reflect the combined effects of temperature-dependent carrier transport and thermally induced gate-contact modification. Because the maximum TDT temperature reached 500 °C, unintended in situ annealing or interfacial modification of the gate contact may have occurred during the measurement sequence. This possibility is explicitly considered in the interpretation of the post-TDT electrical and thermal signatures. Finally, a 100 nm SiO₂ passivation layer was deposited by sputtering.

The fabricated devices had the same lateral geometry for both gate-contact schemes. The source-to-gate spacing, gate length, gate-to-drain spacing, and gate width were 5 μm, 5 μm, 13 μm, and 200 μm, respectively. This identical layout enables direct comparison of the electrical and thermal responses of the Pd ohmic and Ni Schottky p-GaN gate HEMTs.

The gate-contact characteristics were verified using transmission-line-method (TLM) structures fabricated on p-GaN. Figure 2a shows the TLM current–voltage characteristics of the Pd/p-GaN contact with gap spacings of 10–50 μm. The Pd contact exhibited nearly linear and symmetric I-V behavior around zero bias, and the measured current systematically decreased with increasing TLM spacing. From the linear TLM fitting, the sheet resistance and specific contact resistivity were extracted, with values of 3.96 × 10⁴ Ω/square and 4.5 × 10⁻³ Ω∙cm², respectively. These results indicate non-rectifying, injection-capable ohmic-like conduction through the Pd/p-GaN contact. This interpretation is also consistent with previous reports on Pd-based contacts to p-GaN, where Pd-based metallization showed room-temperature ohmic behavior even before annealing [17]. The reported mechanism was associated with epitaxial growth of Pd(111) on GaN(0001), good in-plane epitaxial ordering, and a reduced effective Pd/p-GaN Schottky-barrier height compared with the theoretical Schottky–Mott value [17]. Therefore, the Pd gate in this work is classified as an ohmic-like gate contact, while it is noted that the relatively large ρ_c indicates an injection-capable contact rather than an ideal low-resistance ohmic contact. In contrast, the Ni/p-GaN contact in Figure 2b showed strongly suppressed current within the same bias range, indicating a blocking Schottky-type gate contact. Accordingly, the Pd- and Ni-gated devices are referred to hereafter as ohmic-like and Schottky-type p-GaN gate HEMTs, respectively. This contact verification is important because the observed post-TDT degradation of the Pd-gated device is interpreted in terms of the loss of injection-assisted gate–channel modulation, which requires an injection-capable Pd/p-GaN gate contact rather than a blocking Schottky-type contact.

2.2. Temperature-Dependent Electrical Characterization

Electrical measurements were performed before the TDT, during temperature-dependent characterization and after post-TDT recovery to room temperature. Gate leakage measured at V_DS = 0 V was treated as intrinsic gate-stack leakage, whereas gate current obtained during transfer measurements at finite V_DS was treated as the operating gate-current penalty. This distinction is essential because the gate current under shorted drain–source conditions does not necessarily represent the gate-current burden during transistor operation [14,15,16].

The experimental workflow was designed to correlate the electrical degradation of the two gate-contact schemes with their corresponding thermal signatures. The electrical and thermal datasets were integrated using a common set of degradation and localization metrics. Electrical characterization, including the temperature-dependent test (TDT), and thermoreflectance thermal imaging were therefore treated as complementary measurements rather than independent analyses.

Temperature-dependent electrical characterization was carried out using a Keysight B1505A power device analyzer and a vacuum chamber. The devices were measured sequentially at room temperature, 100 °C, 200 °C, 300 °C, 400 °C, and 500 °C. At each temperature, the devices were allowed to stabilize for more than 30 min before electrical measurements were performed. After the high-temperature sequence, the devices were naturally cooled down inside the vacuum chamber and then measured again at room temperature to distinguish reversible temperature-dependent changes from residual degradation after the TDT.

Three electrical measurement modes were used. First, gate leakage characteristics were measured under shorted drain–source conditions, with V_DS = 0 V and V_GS swept from −8 to 6 V. This measurement was used to evaluate intrinsic gate-stack conduction through the metal/p-GaN/AlGaN gate structure. Second, I_DS-V_GS were measured at VDS = 10 V while sweeping V_GS from −8 to 6 V. From these data, I_DS, I_GS, I_GS/I_DS, threshold voltage (V_TH), transconductance (gm), subthreshold swing (SS), and off-state current were extracted. Third, output characteristics were measured with VDS sweeping from 0 V to 10 V and Vg varying from −4 V to 6 V in 2 V steps. The output curves were used to assess on-state current capability and on-resistance. To minimize the influence of self-heating-induced current collapse during the electrical measurements, the transfer and output characteristics were measured under pulsed-bias conditions.

2.3. Thermoreflectance Thermal Imaging

Thermoreflectance thermal imaging was performed using a TRM250 system from Nanoscopesystems (Daejeon, Republic of Korea). Thermoreflectance is an optical thermometry technique based on the temperature dependence of the optical reflectance of a material. When the temperature changes by delta T, the refractive index and optical constants of the probed surface change slightly, producing a corresponding change in the reflected intensity [18,19,20]. For small temperature excursions, the normalized reflectance change is linearly related to the local temperature rise through the thermoreflectance coefficient, $C_{TR}$:

$${\displaystyle \frac{∆R}{R}}=C_{TR}\times ∆T$$

(1)

Here, $C_{TR}$ represents the temperature sensitivity of the measured surface reflectance at a given wavelength and in a certain material region. Since both the magnitude and sign of $C_{TR}$ depend on the material, surface conditions, and illumination wavelength, the experimentally calibrated $C_{TR}$ value was used directly for temperature conversion [20].

A 365 nm wavelength was used to probe the GaN region, and the thermal maps were acquired using a 20× objective lens. The use of near-ultraviolet illumination is appropriate for GaN because the photon energy at 365 nm is close to the GaN bandgap and can therefore probe the near-surface GaN region rather than being fully transparent to the semiconductor [18].

The thermoreflectance coefficient calibration was performed from 25 °C to 95 °C with a 10 °C interval, yielding a $C_{TR}$ value of −2 × 10⁻³ K⁻¹. Temperature was calculated using an asynchronous thermoreflectance technique. The pre- and post-TDT thermal maps were acquired under the same electrical bias condition, VGS = 6 V and VDS = 10 V. Therefore, the observed changes in the thermal maps reflect the combined influence of electrical degradations, modified current transport, and heat-source redistribution under identical external bias conditions.

3. Results and Discussion

3.1. Gate Leakage Characteristics

The gate leakage characteristics in Figure 1 were first examined under V_DS = 0 V to evaluate the intrinsic gate-stack conduction of each gate-contact scheme. This measurement condition isolates the metal/p-GaN/AlGaN gate stack from drain-induced channel conduction and therefore provides a direct comparison of the leakage behavior of the Pd ohmic and Ni Schottky gates.

In the initial room-temperature state, the Pd ohmic gate exhibited a substantially larger gate leakage than the Ni Schottky gate. At V_GS ≈ 6 V, the gate leakage current was 20.69 mA/mm for the Pd ohmic gate and 6.24 mA/mm for the Ni Schottky gate. At VGS = 4 V, the difference was even more pronounced, with 15.18 mA/mm for the ohmic gate and 1.05 mA/mm for the Schottky gate. This confirms that the Pd gate provides an injection-capable gate contact, whereas the Ni gate suppresses gate conduction through a rectifying Schottky-type barrier.

The temperature dependence of gate leakage showed different trends for the two gate types. For the ohmic gate, the leakage current at V_GS ≈ 6 V decreased from 20.69 mA/mm at room temperature to 2.24 mA/mm at 500 °C. This decrease indicates that the high-temperature behavior of the ohmic gate is not governed simply by thermally enhanced emission. Instead, the effective gate injection may be limited by increased p-GaN resistance, altered voltage partitioning within the gate stack, or weakening of the effective injection path at high temperature. For the Ni Schottky gate, the leakage current was 6.24 mA/mm at room temperature, increased slightly to 7.22 mA/mm at 100 °C, and then decreased to 2.46 mA/mm at 500 °C. After cooling back to room temperature, the leakage current was 6.71 mA/mm, slightly higher than the initial value, suggesting a residual modification of the Schottky gate stack after the TDT.

As described in

Table 1. Gate leakage onset voltage defined at I_GS = 0.5 mA/mm.

Temperature	Pd Ohmic Gate	Ni Schottky Gate
RT	1.78 V	3.42 V
100 °C	1.85 V	2.58 V
200 °C	2.11 V	3.37 V
300 °C	2.27 V	3.81 V
400 °C	2.33 V	3.91 V
500 °C	3.08 V	3.17 V
Post-TDT	1.75 V	2.53 V

, the leakage-onset voltage, defined here as the gate voltage at which IG reaches 0.5 mA/mm, also revealed gate-stack modification after the TDT. Initially, the onset voltage was 1.78 V for the ohmic gate and 3.42 V for the Schottky gate. The higher onset voltage of the Schottky gate confirms its stronger gate-current-blocking capability in the initial state. However, after the TDT, the onset voltage of the Schottky gate decreased from 3.42 V to 2.53 V, indicating that the Schottky barrier or leakage path became easier to activate after high-temperature exposure.

The reduction in the leakage-onset voltage in the Ni Schottky gate after the TDT indicates that the Schottky-gate stack became easier to activate after high-temperature exposure. This behavior may originate from several non-exclusive mechanisms. First, a thermally induced interfacial reaction or interdiffusion at the Ni/p-GaN interface can modify the effective Schottky barrier. Second, high-temperature electrical stress can generate or activate defect-assisted leakage paths in the p-GaN/AlgaN gate stack. Third, residual trapped charge may modify the local band bending and lower the apparent onset voltage for gate conduction.

3.2. Transfer Characteristics

The temperature-dependent transfer (Id-Vg) characteristics were summarized using four key parameters extracted at V_DS = 10 V: V_TH, gm, SS, and the operating gate-current ratio (I_G/I_D). The resulting trends are shown in Figure 3 and Figure 4.

Figure 5a shows that V_TH increases monotonically with temperature for both gate-contact schemes. At room temperature, all devices exhibit similar V_TH values of approximately 1.6–1.7 V, confirming comparable normally off behavior before high-temperature exposure. As the temperature increases, V_TH gradually shifts toward positive values and reaches approximately 3.4–3.8 V at 500 °C. This positive V_TH shift indicates that a larger gate bias is required to restore the 2DEG channel at elevated temperature. The trend is observed in both ohmic and Schottky devices, suggesting that the dominant origin is not solely the metal/p-GaN contact type but also temperature-dependent channel depletion, p-GaN potential modulation, and increased series resistance in the gate/channel access path.

Figure 5b shows a strong reduction in gm with increasing temperature. The gm values are normalized to their room-temperature values in the plot, and all devices decrease rapidly from unity at room temperature to less than approximately 0.1 at 400–500 °C. The reduction in gm is attributed to the combined effect of reduced channel mobility, enhanced phonon scattering, increased source/drain access resistance, and weakened gate-to-channel charge modulation at elevated temperature. Because both gate types show a similar first-order decrease in gm, the dominant temperature-dependent component is likely associated with the AlGaN/GaN channel and access regions rather than only the metal/p-GaN contact. However, the different post-TDT recovery trends indicate that the gate contact still plays an important role in the residual degradation pathway. The similarity of the decreasing trends in the two gate types indicates that high-temperature carrier transport degradation in the AlGaN/GaN channel and access regions dominates the transconductance loss. However, the post-TDT recovery behavior must still be interpreted together with the contact-specific gate-current and off-state degradation signatures.

Figure 5c compares the subthreshold swing normalized to the room-temperature value. In general, SS increases with temperature, indicating degraded subthreshold gate control at elevated temperatures. The increase is modest up to approximately 300 °C for most devices but becomes more pronounced at 400–500 °C. The variation observed in the extracted SS suggests that the subthreshold regime is sensitive to local trap and gate-stack nonuniformity. The Schottky devices show strong SS degradation at intermediate-to-high temperatures, whereas the ohmic devices exhibit a sharp SS increase near 500 °C. This behavior indicates that both gate schemes lose electrostatic control in the extreme-temperature regime, although the detailed degradation path differs between the two contact types.

Figure 5d shows the operating gate-current ratio. It evaluates the gate-current burden under actual transistor operation rather than under gate leakage conditions (V_DS = 0 V). At room temperature, the Schottky devices exhibit much lower I_G/I_D than the ohmic devices, confirming the superior gate-current blocking capability of the Schottky contact. With increasing temperature, the gate-current ratio increases for all devices, reflecting the combined effect of reduced drain current and non-negligible gate current. Near 500 °C, the Schottky devices show a pronounced increase in I_G/I_D, reaching values comparable to or larger than those of the ohmic devices. This indicates that the low-gate-current advantage of the Schottky gate collapses in the extreme-temperature regime.

The reduction in leakage-onset voltage is consistent with the post-TDT transfer and output signatures of the Schottky-gated devices. The simultaneous increase in transconductance and maximum drain current, decrease in on-resistance, and degradation of SS suggest that the Schottky gate stack becomes easier to electrically activate after the TDT, while its ability to maintain off-state electrostatic control is degraded. Therefore, the leakage-onset shift is interpreted as part of the same barrier/depletion-control weakening process rather than as an isolated gate leakage phenomenon.

After the TDT and natural cooling to room temperature, the gate-current ratio decreases markedly in the Schottky devices and returns close to the initial low range, while the ohmic devices remain at several percent. However, this apparent recovery of I_G/I_D should not be interpreted alone as full recovery of gate reliability, because the post-TDT electrical data also show degraded SS and increased I_off in the Schottky devices. Therefore, the transfer-parameter trends indicate that the Schottky gate is advantageous at low-to-moderate temperatures due to its low operating gate-current penalty, whereas both gate types enter a severe degradation regime at 400–500 °C, where gm collapse, SS degradation, and increased IG/ID must be considered simultaneously.

3.3. Output Characteristics

After the transfer analysis established the progressive loss of gate modulation capability with increasing temperature, the output characteristics were examined to evaluate how this degradation is reflected in the on-state conduction path, as shown in Figure 6. The output behavior was summarized using normalized on-resistance and normalized maximum drain current, as shown in Figure 4. Normalization to the room-temperature value allows the relative thermal stability of each gate-contact scheme to be compared independently of the initial absolute current difference between the ohmic and Schottky devices.

Figure 7a shows the normalized on-resistance, R_ON,norm, as a function of temperature. For all devices, R_ON,norm increases monotonically with temperature, indicating progressive degradation of the on-state conduction path. This increase is consistent with reduced carrier mobility, enhanced phonon scattering, and increased channel/access resistance at elevated temperature. However, the slope of degradation differs between the two gate-contact schemes. The ohmic devices show a steeper increase in R_ON,norm, particularly above 300 °C, reaching approximately 7.4–7.9 times their room-temperature values at 500 °C. By contrast, the Schottky devices show a more moderate increase, reaching approximately 4.3–5.0 times their room-temperature values at 500 °C. This result indicates that, although the Pd ohmic devices provide a strong initial current drive, their on-state resistance is more strongly affected by high-temperature operation.

Figure 7b presents the normalized maximum drain current, I_D,max,norm. The drain current decreases systematically with temperature for both gate-contact schemes, reflecting the loss of current-driving capability under high-temperature operation. The decrease is most rapid from room temperature to 200 °C and continues more gradually at higher temperatures. Consistent with R_ON,norm, the Schottky devices retain a larger fraction of their initial drain current over most of the measured temperature range. In the 200–500 °C range, the normalized I_D,max of the Schottky devices remains higher than that of the ohmic devices, indicating superior relative current retention under thermal stress.

The transfer data showed that gm collapses and I_G/I_D increases as temperature rises, especially in the extreme-temperature regime. The normalized output data further show that the degradation is not limited to gate modulation but also extends to the lateral conduction path. The ohmic-gate devices exhibit stronger relative degradation in R_ON and I_D,max, suggesting that the injection-assisted current advantage observed at lower temperature becomes increasingly ineffective as the channel/access resistance increases. Conversely, the Schottky devices show better relative preservation of on-state conduction, even though their gate-current advantage also weakens at high temperature.

3.4. Post-TDT Electrical Signatures

The residual electrical changes after TDT were evaluated by comparing the initial room-temperature parameters with those measured after natural cooling to room temperature, as summarized in Figure 8. The ohmic devices show a clear reduction in current-modulation capability after the TDT: the transconductance decreases from 83.3 to 52.2 mS/mm and from 107.2 to 89.95 mS/mm for ohmic devices, while I_D,max decreases from 201.8 to 163.3 mA/mm and from 200.65 to 195.75 mA/mm, respectively. Although R_ON decreases after the TDT in both ohmic devices, from 17.65 to 14.16 Ω·mm and from 18.93 to 14.13 Ω·mm, this reduction does not indicate full recovery or improved gate control because it occurs simultaneously with a decrease in gm and I_D,max. Therefore, the dominant post-TDT signature of the ohmic gate is not on-state activation but degradation of gate–channel modulation efficiency. In other words, the ability of the Pd gate to translate forward gate bias or gate injection into effective 2DEG modulation becomes weaker after high-temperature exposure. In contrast, the Schottky devices exhibit apparent on-state activation after the TDT. The transconductance increases from 87.45 to 109.4 mS/mm and from 84.25 to 112.45 mS/mm for Schottky devices, while I_D,max increases from 175.55 to 205.7 mA/mm and from 165.1 to 211.25 mA/mm, respectively. R_ON also decreases markedly, from 27.21 to 15.53 Ω·mm and from 27.97 to 15.04 Ω·mm. However, this apparent improvement is accompanied by a pronounced degradation in subthreshold swing, which increases from 129.9 to 189.7 mV/dec and from 146 to 239.6 mV/dec. Thus, the post-TDT Schottky behavior should not be interpreted as beneficial annealing. Instead, the simultaneous increase in gm and I_D,max, decrease in R_ON, and degradation of SS indicate weakened Schottky-barrier or p-GaN depletion control, which makes the channel easier to turn on but degrades off-state electrostatic control. Here, R_ON was extracted from the low-V_DS linear region, whereas I_D,max was evaluated at high V_DS. Therefore, the decrease in R_ON after TDT does not necessarily imply improved high-field current capability. Instead, the simultaneous reduction in gm and I_D,max indicates that the gate-to-channel modulation efficiency and high-field current-driving capability are degraded, despite the apparent reduction in low-field resistance. This distinction motivates the thermal-map analysis in the following sections, where the electrical signatures are correlated with heat-source redistribution under identical bias conditions.

3.5. Temperature-Dependent Trade-Off Between Ohmic and Schottky Gates

The electrical characteristics show that the preferred gate-contact scheme depends on both temperature and reliability metrics. At low temperatures, the ohmic devices provide higher absolute current drive through injection-assisted channel modulation, but this benefit is accompanied by a larger operating I_G/I_D ratio. In contrast, the Schottky devices show lower initial current but substantially reduced gate-current burden. Therefore, from RT to approximately 100 °C, the Schottky gate is more favorable when gate-drive efficiency and leakage suppression are prioritized, whereas the ohmic gate is advantageous only when maximum on-state current is the primary criterion.

In the 100–300 °C range, the Schottky devices provide a more balanced response. They maintain a lower I_G/I_D ratio and better normalized retention of I_D,max and R_ON, indicating that the Schottky barrier remains effective while the dominant degradation is still associated with a thermally induced mobility reduction and access-resistance increase. Above approximately 300 °C, however, both gate schemes show severe gm degradation, increasing SS, and a rising I_G/I_D ratio. In this regime, Schottky devices may still retain favorable normalized output behavior, but the post-TDT SS degradation indicates that apparent on-state improvement can coincide with weakened gate or depletion control.

At 400–500 °C, both gate-contact schemes enter an extreme degradation regime, characterized by a strong current reduction, a sharp R_ON increase, and a large I_G/I_D. The low-gate-current advantage of the Schottky gate is no longer decisive because the degraded drain current amplifies the relative gate-current penalty. Thus, operation near 500 °C should be regarded as a failure-precursor regime rather than a stable operating window for either contact scheme. Overall, Schottky gates are preferable up to approximately 300 °C for leakage suppression and gate-drive efficiency, whereas ohmic gates provide a stronger initial current drive but are more vulnerable to thermally induced loss of gate–channel modulation efficiency.

To place these results in the context of previous reliability studies, the observed trends can be related to three major issues reported for GaN HEMTs: Schottky-gate reliability, self-heating in GaN-on-Si devices, and high-temperature degradation of channel transport. Previous studies on Schottky-type p-GaN gates have shown that a gate leakage increase, barrier modification, and degradation at the metal/p-GaN or p-GaN/AlGaN interface can occur under high-field or high-temperature stress. In the present work, the post-TDT reduction in leakage-onset voltage of the Ni Schottky gate, together with the increased gm and I_D,max, decreased R_ON, degraded SS, and persistent localized heating, suggests weakened Schottky-barrier or p-GaN depletion control rather than isolated gate leakage variation. In addition, the thermoreflectance maps are consistent with previous reports emphasizing localized self-heating near the gate-edge/channel region in GaN-on-Si HEMTs. Therefore, the thermal maps are interpreted as spatial signatures of post-TDT heat-source redistribution. Finally, the common high-temperature trends observed in both gate types, including gm reduction, R_ON increase, and I_D,max degradation, are attributed to reduced channel mobility, enhanced phonon scattering, increased access resistance, and weakened gate-to-channel charge modulation. The different post-TDT recovery signatures of the Pd ohmic-like and Ni Schottky-type gates indicate that the gate-contact scheme introduces an additional degradation pathway beyond the common channel/access-region temperature dependence.

3.6. Thermoreflectance Thermal Maps Before and After TDT

Figure 9 shows the thermoreflectance thermal maps measured under the identical bias condition of V_GS = 6 V and V_DS = 10 V. The grayscale image indicates the device metallization layout, while the overlaid color map represents the temperature distribution in the GaN active region. The source and drain electrodes are located on the left and right sides of the central channel region, respectively, and the thermal response is therefore interpreted mainly along the narrow vertical active region between the source and drain metallization. Since the maps were acquired under identical external bias rather than identical dissipated power, the observed change in temperature distribution reflects the combined effects of post-TDT electrical degradation, modified channel current, and heat-source redistribution.

The ohmic device exhibits a clear reduction in active-channel heating after the TDT. Figure 9a shows a continuous hot stripe along the central channel before the TDT, with the highest temperature contrast concentrated near the gate-edge/channel region. This behavior is consistent with injection-assisted channel conduction in the ohmic-gate device, where forward gate bias enhances the channel charge and produces an extended Joule heating profile. After the TDT, as shown in Figure 9b, the hot stripe becomes weaker, and the high-temperature region is less pronounced. This reduction should not be interpreted as improved thermal stability. Rather, it is consistent with the post-TDT decrease in gm and I_D,max. Under the same V_GS and V_DS, the reduced thermal contrast indicates that a smaller fraction of the applied gate bias is effectively converted into channel modulation and drain current. Therefore, the post-TDT cooling of the Pd ohmic device is a thermal signature of degraded gate–channel modulation efficiency.

In contrast, the Schottky device maintains a stronger and more localized hot stripe after the TDT. Figure 9c shows a sharp high-temperature stripe along the central gate-edge/channel region before the TDT, indicating localized heat generation under Schottky-gate operation. Figure 9d shows that a pronounced localized heating profile remains after the TDT, although the spatial contrast becomes slightly redistributed along the channel. This behavior is consistent with the post-TDT electrical signature of the Schottky devices: gm and I_D,max increase, while SS markedly degrades. Therefore, the persistent hot stripe should not be regarded as evidence of beneficial recovery. Instead, it suggests that high-temperature exposure weakens the Schottky-barrier or p-GaN depletion control, allowing the channel to turn on more easily under the same external bias while degrading off-state electrostatic control.

Overall, the thermoreflectance maps reveal that the two gate-contact schemes undergo different heat-source transformations after the TDT. The ohmic gate shows degradation-type cooling associated with reduced modulation efficiency, whereas the Schottky gate shows persistent localized heating associated with apparent on-state activation and degraded subthreshold control. Thus, the thermal maps provide spatial evidence that complements the electrical analysis: post-TDT reliability cannot be judged from the absolute temperature rise alone but must be interpreted together with the direction of change in gm, I_D,max, R_ON, and SS.

4. Conclusions

This study compared Pd ohmic and Ni Schottky p-GaN gate HEMTs fabricated on the same GaN-on-Si epitaxial platform by combining temperature-dependent electrical characterization, post-TDT room-temperature recovery analysis, and thermoreflectance thermal imaging. Under the present as-deposited gate-contact conditions, the results suggest that Pd ohmic-like and Ni Schottky p-GaN gates follow different electro-thermal degradation pathways. The results show that the relative advantage of each gate-contact scheme depends strongly on the temperature regime and on the metric used for evaluation. The Pd ohmic devices provide higher initial current drive through injection-assisted channel modulation, but this benefit is accompanied by a larger operating gate-current penalty. In contrast, the Ni Schottky devices suppress the gate-current burden and retain normalized output characteristics more effectively up to approximately 300 °C. At higher temperatures, however, both gate types show severe degradation in gate modulation and on-state conduction, indicating that operation near 500 °C should be regarded as an extreme-stress or failure-precursor regime rather than a stable operating window.

The post-TDT results reveal that apparent improvements in individual electrical parameters can be misleading unless on-state, off-state, and thermal signatures are interpreted together. In the Pd ohmic devices, the post-TDT reduction in gm and I_D,max, together with the weakened active-channel thermal contrast, indicates a loss of gate–channel modulation efficiency. The resulting decrease in thermal signal is therefore interpreted as degradation-type cooling rather than improved thermal stability. In the Ni Schottky devices, the post-TDT increase in gm and I_D,max and the reduction in R_ON occur simultaneously with pronounced SS degradation and persistent localized heating. This behavior indicates apparent on-state activation associated with weakened Schottky-barrier or p-GaN depletion control, rather than beneficial recovery.

Overall, this work demonstrates that high-temperature reliability in p-GaN gate HEMTs cannot be assessed using a single scalar parameter such as I_D,max, R_ON, gate leakage, or peak temperature. A physically meaningful assessment requires separating intrinsic gate-stack leakage from transfer-condition gate-current penalty and correlating electrical degradation with spatial heat-source redistribution. By linking post-TDT electrical shifts with spatial changes in thermoreflectance maps, this study provides a gate-contact-resolved view of reliability degradation in p-GaN HEMTs. The results suggest that ohmic and Schottky gates do not merely differ in leakage magnitude or initial current capability but follow different electro-thermal degradation pathways: reduced modulation efficiency in the former and easier channel activation with compromised off-state control in the latter. This interpretation offers a practical basis for temperature-regime-dependent gate-contact selection and highlights the broader need to treat gate-stack stability, heat-source topology, and high-temperature reliability as coupled design parameters in GaN and ultrawide-bandgap power devices.

Although the present study focuses on representative devices measured under the same high-temperature TDT protocol, future work with a larger device population will be required to quantify statistical variations, confidence intervals, and lifetime distributions under high-temperature operation. Also, future work combining post-stress TEM/EDS, XPS, or SIMS with electrical and thermoreflectance measurements will be necessary to directly verify whether the observed post-TDT changes originate from gate-metal interdiffusion, interface-state generation, or residual charge trapping.