Search Results (141)

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of ion-induced Single-Event Burnout (SEB) in similarly rated silicon (Si) UMOS and DMOS devices remains lacking. This study presents a comprehensive experimental comparison of ion-induced charge collection mechanisms and SEB susceptibility in similarly rated Si UMOS and DMOS devices. Charge collection mechanisms due to alpha particles from ²⁴¹Am radiation source are analyzed, and SEB cross sections induced by heavy ions from particle accelerators are directly compared. The implications of the unique gate structure of Si UMOSFETs on their reliability in harsh radiation environments are discussed based on technology computer-aided design (TCAD) simulations. Full article

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives, such as gallium arsenide (GaAs), provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions include a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics for performance evaluation. A comprehensive analytical modeling approach is employed, solving Poisson’s equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs while minimizing some disadvantages. The results of the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

Biologically sensitive field-effect transistors (BioFETs) have advanced the biosensing capabilities in various fields such as healthcare, security and environmental monitoring. Here, we propose a junctionless BioFET (JL-BioFET) for the high-sensitivity and low-cost detection of biomolecules and analyze it using detailed device simulations. In contrast to the conventional FET with junctions, the JL-BioFET simplifies fabrication by doping the source, channel and drain simultaneously with the same types of impurities, thereby reducing the fabrication effort and cost. Additionally, if the device is designed with optimal bias, it can operate with only the source and drain terminals, which reduces power consumption. Thus, cost reduction and reduced power consumption are strong motivations to pursue a new design. Therefore, we simulated two JL-BioFET structures (SOI JL, bulk JL) that operate without a gate electrode and compared their biosensing performances. The bulk JL-BioFET showed an average sensitivity three times higher than that of the SOI JL-BioFET across varying charge levels. Then, we optimized the sensing performance of the bulk JL-BioFET by adjusting three key parameters: the active layer thickness and the doping concentrations of the active layer and substrate. These encouraging results are expected to lead to future fabrication efforts to realize bulk JL-BioFETs for high-performance biosensing. Full article

With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits. Full article

GaN HEMTs based on polarization super junction (PSJ) technology offer significant improvements in efficiency and power density over conventional silicon (Si) devices due to their excellent material characteristics, which enable fast switching edges and lower specific on-resistance. However, due to the presence of an uninterrupted channel between drain and source at zero gate bias, these devices have normally-on characteristics. In this paper, the performance of a 1200 V GaN FET utilizing PSJ technology in cascode configuration is reported. The device working principle, characteristics, and switching behavior are experimentally demonstrated. The results show that cascoded GaN FETs utilizing the PSJ concept are highly promising for power device applications. Full article

Impedance-based biosensing has emerged as a critical technology for high-sensitivity biomolecular detection, yet traditional approaches often rely on bulky, costly impedance analyzers, limiting their portability and usability in point-of-care applications. Addressing these limitations, this paper proposes an advanced biosensing system integrating a Silicon Nanowire Field-Effect Transistor (SiNW-FET) biosensor with a high-gain amplification circuit and a 1D Convolutional Neural Network (CNN) implemented on FPGA hardware. This attempt combines SiNW-FET biosensing technology with FPGA-implemented deep learning noise reduction, creating a compact system capable of real-time viral detection with minimal computational latency. The integration of a 1D CNN model on FPGA hardware for adaptive, non-linear noise filtering sets this design apart from conventional filtering approaches by achieving high accuracy and low power consumption in a portable format. This integration of SiNW-FET with FPGA-based CNN noise reduction offers a unique approach, as prior noise reduction techniques for biosensors typically rely on linear filtering or digital smoothing, which lack adaptive capabilities for complex, non-linear noise patterns. By introducing the 1D CNN on FPGA, this architecture enables real-time, high-fidelity noise reduction, preserving critical signal characteristics without compromising processing speed. Notably, the findings presented in this work are based exclusively on comprehensive simulations using COMSOL and MATLAB, as no physical prototypes or biomarker detection experiments were conducted. The SiNW-FET biosensor, functionalized with antibodies specific to viral antigens, detects impedance shifts caused by antibody–antigen interactions, providing a highly sensitive platform for viral detection. A high-gain folded-cascade amplifier enhances the Signal-to-Noise Ratio (SNR) to approximately 70 dB, verified through COMSOL and MATLAB simulations. Additionally, a 1D CNN model is employed for adaptive noise reduction, filtering out non-linear noise patterns and achieving an approximate 75% noise reduction across a broad frequency range. The CNN model, implemented on an Altera DE2 FPGA, enables high-throughput, low-latency signal processing, making the system viable for real-time applications. Performance evaluations confirmed the proposed system’s capability to enhance the SNR significantly while maintaining a compact and energy-efficient design suitable for portable diagnostics. This integrated architecture thus provides a powerful solution for high-precision, real-time viral detection, and continuous health monitoring, advancing the role of biosensors in accessible point-of-care diagnostics. Full article

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron. Full article

The continuous scaling down of MOSFETs is one of the present trends in semiconductor devices to increase device performance. Nevertheless, with scaling down beyond 22 nm technology, the performance of even the newer nanodevices with multi-gate architecture declines with an increase in short channel effects (SCEs). Consequently, to facilitate further increases in the drain current, the use of strained silicon technology provides a better solution. Thus, the development of a novel Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel with a 10 nm gate length is initiated and discussed. In this device, strain is incorporated in the channel, where a strained silicon germanium layer is wedged between two strained silicon layers. The GAAFET device has four gates that surround the channel to provide improved control of the gate over the strained channel region and also reduce the short channel effects in the devices. The electrical properties, such as the on current, off current, threshold voltage (V_TH), subthreshold slope, drain-induced barrier lowering (DIBL), and I_on/I_off current ratio, of the 10 nm channel length GAAFET are compared with the 22 nm strained silicon channel GAAFET, the existing SOI FinFET device on 10 nm gate length, and IRDS 2022 specifications device. The developed 10 nm channel length GAAFET, having an ultrathin strained silicon channel, delivers enriched device performance, being augmented in contrast to the IRDS 2022 specifications device, showing improved characteristics along with amended SCEs. Full article

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general. Full article

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. Full article

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (tr_pbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (T_SD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (C_gg) as the T_SD increases. A higher TIS height prevents the C_gg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (C_L) increases. As C_L increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling tr_pbt and improving electro-thermal performance in sub-3 nm node NSFETs. Full article

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs. Full article