Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.


Introduction
Silicon fin field-effect transistors (FinFETs) have been successfully scaled down to 3 nm nodes and have gained acceptance in the logic foundry industry [1].The downscaling made the fin channels thinner and taller to maintain electrostatics and performance.Nevertheless, the significantly heightened fin aspect ratio resulted in a structural instability of the fins, leading to their bending and breaking [2,3].Furthermore, the number of fins per device was depopulated from 3 to 1 fin to reduce the cell height.Performance modulation of FinFETs mainly depends on adjusting the number of fins; therefore, fin depopulation is a challenge for circuit design with FinFETs.To overcome the limitations of FinFETs, vertically stacked silicon gate-all-around nanosheet (NS) FETs have emerged as a replacement for FinFETs [4,5].In contrast to FinFETs, NS channels are laterally wide, resulting in a low aspect ratio and stable structure [5].In addition, continuous performance modulation is possible by adjusting the NS width, which enables flexible circuit design.
Regrettably, the distinctive structure of NSFETs leads to a parasitic bottom transistor (tr pbt ) that forms beneath the bottommost NS channel [6][7][8].The tr pbt is a critical failure factor that causes significant punch-through leakage because gate controllability is not achieved in the tr pbt .Conventionally, a counter-doped punch-through stopper (PTS) layer has been used to control the leakage in tr pbt [9].However, the PTS loses its ability to control the leakage if the source/drain (S/D) recess is unintentionally over-etched [6,10].
The insertion of dielectric layers between the S/D and the substrate, known as the bottom oxide (BOX) scheme, is one of the commonly known methods to control the tr pbt [10,11].BOX acts as an etch-stop layer that regulates the S/D recess depth variations.In addition, BOX allows for the thorough blocking of the leakage path.Alternatively, the trench inner-spacer (TIS) scheme was proposed in our previous study to control tr pbt , even under over-etched S/D recess conditions [12].In the TIS scheme, the bottom inner-spacer is extended toward the PTS layer, preventing S/D dopants from diffusing into the channel of the tr pbt (see Figure 1 for details).The TIS scheme is immune to variation in the over-etched S/D recess depth (T SD ) because the TIS height is always higher than the T SD .
Nanomaterials 2024, 14, x FOR PEER REVIEW 2 of 14 achieved in the trpbt.Conventionally, a counter-doped punch-through stopper (PTS) layer has been used to control the leakage in trpbt [9].However, the PTS loses its ability to control the leakage if the source/drain (S/D) recess is unintentionally over-etched [6,10].
The insertion of dielectric layers between the S/D and the substrate, known as the bottom oxide (BOX) scheme, is one of the commonly known methods to control the trpbt [10,11].BOX acts as an etch-stop layer that regulates the S/D recess depth variations.In addition, BOX allows for the thorough blocking of the leakage path.Alternatively, the trench inner-spacer (TIS) scheme was proposed in our previous study to control trpbt, even under over-etched S/D recess conditions [12].In the TIS scheme, the bottom inner-spacer is extended toward the PTS layer, preventing S/D dopants from diffusing into the channel of the trpbt (see Figure 1 for details).The TIS scheme is immune to variation in the overetched S/D recess depth (TSD) because the TIS height is always higher than the TSD.The main difference between the BOX and TIS schemes is the presence of an oxide layer between the S/D and the substrate.As the heat generated in the channels is primarily dissipated from the drain toward the substrate, BOX with a lower thermal conductivity (κ) than silicon hinders the heat dissipation [12,13].This implies that the temperature of the device differs depending on the scheme used.Consequently, the electro-thermal performance may also vary, taking into account the self-heating effect (SHE).
Previous studies have compared the electro-thermal characteristics considering the schemes used to control the trpbt, but they have some limitations.First, some studies compared the electro-thermal performance between conventional (Conv) and BOX schemes The main difference between the BOX and TIS schemes is the presence of an oxide layer between the S/D and the substrate.As the heat generated in the channels is primarily dissipated from the drain toward the substrate, BOX with a lower thermal conductivity (κ) than silicon hinders the heat dissipation [12,13].This implies that the temperature of the device differs depending on the scheme used.Consequently, the electro-thermal performance may also vary, taking into account the self-heating effect (SHE).
Previous studies have compared the electro-thermal characteristics considering the schemes used to control the tr pbt , but they have some limitations.First, some studies compared the electro-thermal performance between conventional (Conv) and BOX schemes [14,15].However, one of them focused solely on the evaluation of the heat dissipa-tion capability without considering the effects of heat on electrical performance.The other study primarily examined the operation of a single device in steady-state DC and neglected the heating and cooling cycles of the devices.As a result, the effects of heat on electrical performance may be overestimated.In contrast, a comparison between TIS and BOX schemes by considering the heating and cooling cycles was investigated in our previous work [12].However, only the ability to dissipate heat during single-device operations was evaluated without quantitatively investigating the effects of heat on electrical performance.In addition, no circuit-level evaluation was conducted to reflect the actual behavior of the system-on-chip (SoC) product.
Therefore, an accurate and comprehensive evaluation of the electro-thermal performance in sub-3 nm node NSFETs with the Conv, TIS, and BOX schemes for the singledevice-to-circuit level is conducted in this study.First, the device structures and simulation methods are presented in Section 2. Secondly, Section 3.1 examines the electro-thermal performance at the single-device level in steady state.Finally, in Section 3.2, the electro-thermal performance of a ring oscillator (RO) is compared based on the transient characteristics using a 3D mixed-mode simulation.All characteristics are based on fully calibrated Synopsys Sentaurus Technology Computer-Aided Design (TCAD) simulations [16,17].

Simulation Structure and Methodology
The TCAD simulation framework for 3-stacked silicon NSFETs was defined as follows.Both process and device simulations were performed using the Sentaurus process and device simulator [16,17].First, we benchmarked the NSFET structures in [4] and calibrated the simulated data and parameters to match the measured transfer curves, as described in our previous work [12].Subsequently, the NSFETs were scaled down to specifications suitable for sub-3 nm node, and then schemes were applied to control the tr pbt .The PTS layer was doped with 2 × 10 18 cm −3 in the Conv and TIS schemes, but undoped in the BOX scheme [11].
Figure 1 presents detailed NSFET structures with the Conv, TIS, and BOX schemes, where the regions with tr pbt are highlighted.Geometric and device parameters are listed in Table 1.The TIS and BOX schemes each include an additional process step compared to the Conv scheme: trench patterning prior to the Si and sacrificial layer (SiGe 0.3 ) epi stacking for the TIS scheme [12], and oxide deposition before the S/D epi growth for the BOX scheme.Here, The TIS scheme leaves SiGe 0.3 residues under the TIS, and the BOX thickness (T BOX ) was determined as 10 nm.Various T SD values were considered in the Conv and TIS schemes to thoroughly verify the effects of tr pbt .For the device and circuit simulations, a comprehensive set of physical models was integrated to simulate various aspects of semiconductor behavior.A self-consistent hydrodynamic model was used to ensure accurate carrier and energy transport.This also facilitated the calculation of device temperatures, which reflect the thermal effects on device performance [18].The inversion and accumulation layer model was included to account for Coulomb, phonon, and scattering from rough surfaces for carrier mobility.In addition, low-field ballistic mobility was included to account for an additional contribution to low-field mobility for devices with very short channels.The low-field mobility model was adjusted so that the simulated data matched the measured data.The Shockley-Read-Hall and Auger models considered recombination and generation, while the Hurkx model was implemented for band-to-band tunneling.To account for quantum mechanical effects, the density gradient model was used.Furthermore, the deformation potential model was included to consider strain-induced changes in the band structure, and the Slotboom model was incorporated to analyze the effects of doping on bandgap narrowing.κ of semiconductor regions was calculated based on the Boltzmann transport equations for phonons with relaxation time approximation.In this context, dependencies of κ on physical size, doping types and concentration, alloy composition, and lattice temperature were considered [19][20][21][22][23].The Sentaurus device simulator provides built-in functions for a self-consistent calculation of κ, and the κ values at 300 K are summarized in Table 2.For the thermal boundary condition, the adiabatic sidewalls along with the contact thermal resistivities of the substrate (r th,sub ) and the BEOL (r th,BEOL ) to be connected to the heat sink at 300 K were assumed.The r th,sub and r th,BEOL were calculated on a Si substrate with dimensions of 5 × 5 µm 2 (area), a thickness of 50 µm, and a BEOL height of 1 µm (contact-M10).
Table 2. Thermal conductivities of the individual regions at 300 K.The transfer curves of Conv-NSFETs as a function of different T SD are presented in Figure 2a.Here, the off-state current (I off ) at T SD = 0 nm was fixed to 1 nA to allow for a fair comparison.The I off was defined as the drain current (I ds ) at V GS = 0 V and |V DS | = 0.7 V.The Conv scheme shows a pronounced increase in I off as the T SD increases.In particular, for nFETs with T SD ≥ 4 nm, and for pFETs with T SD ≥ 6 nm, I off becomes 10 times larger than that of T SD = 0, resulting in critical failures in the SoC products [6,24].On-state current (I on ) also increases with increasing T SD as the leakage current in the tr pbt contributes to I on (I on was defined as I ds at |V GS | = |V DS | = 0.7 V).In contrast, the TIS scheme completely controls the tr pbt , even in deep T SD , by preventing S/D dopants from diffusing into the channel of the tr pbt (Figure 2b) [12].Thus, the I on in the TIS scheme is not affected by the T SD variations.The T SD variations do not occur in the BOX scheme, and the tr pbt has no effect on the I on .

Region
Furthermore, Figure 2 shows the effects of the SHE on the I ds .In all three schemes, the I off is rarely affected by SHE, but the I on is affected.This is attributed to the negligible heat generation in the off-state, which is due to the low current level.In contrast, I on is large enough to cause joule-heating.There are two points of analysis regarding the SHE in Figure 2: (1) the opposite I on change trend caused by the SHE in the n/pFET, and (2) the comparison of I on in the Con, TIS, and BOX schemes under the SHE.Furthermore, Figure 2 shows the effects of the SHE on the Ids.In all three schemes, the Ioff is rarely affected by SHE, but the Ion is affected.This is attributed to the negligible heat generation in the off-state, which is due to the low current level.In contrast, Ion is large enough to cause joule-heating.There are two points of analysis regarding the SHE in Figure 2: (1) the opposite Ion change trend caused by the SHE in the n/pFET, and (2) the comparison of Ion in the Con, TIS, and BOX schemes under the SHE.
First, in all schemes, the Ion under the SHE (Ion_SHE) is larger than that without SHE (Ion_noSHE) in nFETs, whereas it is smaller in pFETs (Figure 3a).This is because the maximum lattice temperature (Tmax) in pFETs is higher than that in nFETs due to the smaller κ of SiGe0.5 S/D than that of SiC0.02S/D (Figure 3b).An increase in the lattice temperature leads to two opposing phenomena in Ion: (1) an increase in carrier density (ne, nh) and (2) a reduction in carrier mobility (μe, μh) (Figure 3c,d).The increase in carrier density is because the elevated Tmax results in an increased intrinsic carrier density.The reduction in carrier mobility is caused by increased phonon scattering.The increase in carrier density is dominant at a low VGS and the reduction in carrier mobility is dominant at a high VGS.A crossover point (Vco) then occurs, at which the magnitudes of Ids_SHE and Ids_noSHE are reversed.Vco is defined as the VGS at which Ids_SHE = Ids_noSHE.First, in all schemes, the I on under the SHE (I on_SHE ) is larger than that without SHE (I on_noSHE ) in nFETs, whereas it is smaller in pFETs (Figure 3a).This is because the maximum lattice temperature (T max ) in pFETs is higher than that in nFETs due to the smaller κ of SiGe 0.5 S/D than that of SiC 0.02 S/D (Figure 3b).An increase in the lattice temperature leads to two opposing phenomena in I on : (1) an increase in carrier density (n e , n h ) and (2) a reduction in carrier mobility (µ e , µ h ) (Figure 3c,d).The increase in carrier density is because the elevated T max results in an increased intrinsic carrier density.The reduction in carrier mobility is caused by increased phonon scattering.The increase in carrier density is dominant at a low V GS and the reduction in carrier mobility is dominant at a high V GS .A crossover point (V co ) then occurs, at which the magnitudes of I ds_SHE and I ds_noSHE are reversed.V co is defined as the V GS at which I ds_SHE = I ds_noSHE .
In Figure 3a, I ds_SHE is larger than I ds_noSHE when the V GS is smaller than the V co .This is because the increased carrier density due to the elevated T max dominates over the reduction in carrier mobility for V GS ≤ V co .For the V GS ≥ V co , however, the I ds_SHE becomes smaller as the contributions of these two factors are reversed.Here, both µ e and µ h.have almost the same temperature dependence [25], and the T max of pFET is larger than that of nFETs.Thus, the reduction in µ h in pFET is significantly larger than µ e in nFET.As a result, V co was determined at a lower V GS in pFETs than in nFETs (0.8 V for nFETs and −0.65 V for pFETs).Therefore, the I on_SHE is larger than the I on_noSHE nFETs, whereas it is smaller in pFETs.In Figure 3a, Ids_SHE is larger than Ids_noSHE when the VGS is smaller than the Vco.This is because the increased carrier density due to the elevated Tmax dominates over the reduction in carrier mobility for VGS ≤ Vco.For the VGS ≥ Vco, however, the Ids_SHE becomes smaller as the contributions of these two factors are reversed.Here, both μe and μh.have almost the same temperature dependence [25], and the Tmax of pFET is larger than that of nFETs.Thus, the reduction in μh in pFET is significantly larger than μe in nFET.As a result, Vco was determined at a lower VGS in pFETs than in nFETs (0.8 V for nFETs and −0.65 V for pFETs).Therefore, the Ion_SHE is larger than the Ion_noSHE nFETs, whereas it is smaller in pFETs.
Secondly, the three schemes show different trends of Ion with respect to the TSD (Figure 2).The Ion in the Conv scheme increases linearly with deeper TSD as the leakage current through the trpbt contributes to Ion.However, the Ion in the TIS scheme hardly varies with the TSD due to the suppression of the leakage in trpbt.Moreover, for nFETs, the TIS scheme has a 3.1% higher Ion_SHE value compared to the BOX scheme, although both schemes have almost the same Ion_noSHE value.Similarly, for pFETs, the TIS scheme has a 2.2% higher Ion_SHE value than the BOX scheme.
The reason for the TIS and BOX schemes showing different changes in Ion_SHE is attributed to the different Tmax values.Conv and TIS schemes with TSD = 0 nm have similar Tmax because the heat can dissipate unhindered through the substrate (Figure 4).The similarity in Tmax between the TIS and Conv schemes is an advantage of the TIS scheme, as it means that the TIS scheme can control the impact of trpbt without affecting thermal performance.However, the lower κ of BOX compared to the S/D epitaxy hinders heat dissipation, causing the BOX scheme to have a significantly higher Tmax than the others.Furthermore, Tmax in the on-state (Tmax_on) increases linearly with the larger TSD, as the S/D epitaxies with the lower κ than PTS intrudes the PTS (Figure 5a).Nevertheless, the BOX scheme in n/pFETs still exhibits 59.6 and 50.4K higher Tmax_on compared with those of the TIS scheme with TSD = 6 nm, respectively.As a result, the reduction in carrier mobility due to the SHE Secondly, the three schemes show different trends of I on with respect to the T SD (Figure 2).The I on in the Conv scheme increases linearly with deeper T SD as the leakage current through the tr pbt contributes to I on .However, the I on in the TIS scheme hardly varies with the T SD due to the suppression of the leakage in tr pbt .Moreover, for nFETs, the TIS scheme has a 3.1% higher I on_SHE value compared to the BOX scheme, although both schemes have almost the same I on_noSHE value.Similarly, for pFETs, the TIS scheme has a 2.2% higher I on_SHE value than the BOX scheme.
The reason for the TIS and BOX schemes showing different changes in I on_SHE is attributed to the different T max values.Conv and TIS schemes with T SD = 0 nm have similar T max because the heat can dissipate unhindered through the substrate (Figure 4).The similarity in T max between the TIS and Conv schemes is an advantage of the TIS scheme, as it means that the TIS scheme can control the impact of tr pbt without affecting thermal performance.However, the lower κ of BOX compared to the S/D epitaxy hinders heat dissipation, causing the BOX scheme to have a significantly higher T max than the others.Furthermore, T max in the on-state (T max_on ) increases linearly with the larger T SD , as the S/D epitaxies with the lower κ than PTS intrudes the PTS (Figure 5a).Nevertheless, the BOX scheme in n/pFETs still exhibits 59.6 and 50.4K higher T max_on compared with those of the TIS scheme with T SD = 6 nm, respectively.As a result, the reduction in carrier mobility due to the SHE is greater in the BOX scheme than in the TIS scheme.Especially in nFETs, the V co in the BOX scheme is significantly lower than that in the TIS scheme due to the T max difference (Figure 5b,c).Therefore, the increase in I on due to the SHE is more pronounced in the TIS scheme than in the BOX scheme, resulting in a higher I on_SHE of the TIS scheme for nFETs.
is greater in the BOX scheme than in the TIS scheme.Especially in nFETs, the Vco in the BOX scheme is significantly lower than that in the TIS scheme due to the Tmax difference (Figure 5b,c).Therefore, the increase in Ion due to the SHE is more pronounced in the TIS scheme than in the BOX scheme, resulting in a higher Ion_SHE of the TIS scheme for nFETs.Figure 6 shows the gate capacitance (Cgg) as a function of VGS in Conv, TIS, and BOX schemes.As increased intrinsic carriers respond to the small signal of the gate due to elevated Tmax, the SHE increases the Cgg in all schemes.In the Conv scheme, the Cgg increase with a large TSD is also due to the increased inversion capacitance of the trpbt (Figure 6a) [6].In contrast, in the TIS scheme, Cgg is not dependent on the TSD at low VGS.However, at high VGS, Cgg increases with a large TSD because carriers in the source are pulled toward the PTS and respond to the small signal of the gate (inset of Figure 6b) [12].For this reason, the formation of a deeper TIS allows for a reduction in Cgg.The TIS scheme inevitably leaves residues of the SiGe0.3sacrificial layer beneath the TIS during the isotropic selective etch of the sacrificial layer for inner-space formation because the depth of the trench is larger than the height of the TIS [12].By performing an additional cleaning step to remove the SiGe0.3residues within the trench, the TIS can be formed to a depth equal to that of the trench.This configuration is referred to as the TIS-full scheme (Figure 7a).In the TIS-full is greater in the BOX scheme than in the TIS scheme.Especially in nFETs, the Vco in the BOX scheme is significantly lower than that in the TIS scheme due to the Tmax difference (Figure 5b,c).Therefore, the increase in Ion due to the SHE is more pronounced in the TIS scheme than in the BOX scheme, resulting in a higher Ion_SHE of the TIS scheme for nFETs.Figure 6 shows the gate capacitance (Cgg) as a function of VGS in Conv, TIS, and BOX schemes.As increased intrinsic carriers respond to the small signal of the gate due to elevated Tmax, the SHE increases the Cgg in all schemes.In the Conv scheme, the Cgg increase with a large TSD is also due to the increased inversion capacitance of the trpbt (Figure 6a) [6].In contrast, in the TIS scheme, Cgg is not dependent on the TSD at low VGS.However, at high VGS, Cgg increases with a large TSD because carriers in the source are pulled toward the PTS and respond to the small signal of the gate (inset of Figure 6b) [12].For this reason, the formation of a deeper TIS allows for a reduction in Cgg.The TIS scheme inevitably leaves residues of the SiGe0.3sacrificial layer beneath the TIS during the isotropic selective etch of the sacrificial layer for inner-space formation because the depth of the trench is larger than the height of the TIS [12].By performing an additional cleaning step to remove the SiGe0.3residues within the trench, the TIS can be formed to a depth equal to that of the trench.This configuration is referred to as the TIS-full scheme (Figure 7a).In the TIS-full Figure 6 shows the gate capacitance (C gg ) as a function of V GS in Conv, TIS, and BOX schemes.As increased intrinsic carriers respond to the small signal of the gate due to elevated T max , the SHE increases the C gg in all schemes.In the Conv scheme, the C gg increase with a large T SD is also due to the increased inversion capacitance of the tr pbt (Figure 6a) [6].In contrast, in the TIS scheme, C gg is not dependent on the T SD at low V GS .However, at high V GS , C gg increases with a large T SD because carriers in the source are pulled toward the PTS and respond to the small signal of the gate (inset of Figure 6b) [12].For this reason, the formation of a deeper TIS allows for a reduction in C gg .The TIS scheme inevitably leaves residues of the SiGe 0.3 sacrificial layer beneath the TIS during the isotropic selective etch of the sacrificial layer for inner-space formation because the depth of the trench is larger than the height of the TIS [12].By performing an additional cleaning step to remove the SiGe 0.3 residues within the trench, the TIS can be formed to a depth equal to that of the trench.This configuration is referred to as the TIS-full scheme (Figure 7a).In the TIS-full scheme, the C gg does not rely on the T SD , as shown in Figure 7b.Therefore, the TIS-full scheme is also used only for a comparison.The I on and C gg in the on-state (C gg_on ) in the four schemes are summarized in Figure 8.The TIS-full scheme has almost the same I on as the TIS scheme.However, C gg_on is reduced by up to 1.6% and 7.1% in the TIS-full scheme compared with the TIS scheme for n/pFETs.scheme, the Cgg does not rely on the TSD, as shown in Figure 7b.Therefore, the TIS-full scheme is also used only for a comparison.The Ion and Cgg in the on-state (Cgg_on) in the four schemes are summarized in Figure 8.The TIS-full scheme has almost the same Ion as the TIS scheme.However, Cgg_on is reduced by up to 1.6% and 7.1% in the TIS-full scheme compared with the TIS scheme for n/pFETs.For a fair performance comparison, it is necessary to account for static power consumption.Figure-of-merit (FoM) is defined as RC delay/|log10(Ioff × VDD)|, where RC delay = Cgg_on × VDD/Ion.The reason that log10 is taken for the static power term is that the contribution of static power should not be overestimated.The smaller the FoM, the better the electrical performance.Figure 9 illustrates the FoM as a function of the TSD and SHE in the four schemes.First, in the Conv scheme, the FoM increases significantly with a large TSD due to the leakage current, which spikes sharply with increasing TSD.As a result, the Conv scheme exhibits the worst device performance with TSD = 6 nm.Second, the FoM in the TIS scheme does not vary much with larger TSD, except for the pFETs under the SHE.The pFETs with TSD = 0 nm show a smaller FoM than the BOX scheme, but it increases significantly as the TSD becomes larger due to increased Cgg (Figure 6b).Third, the FoM in the TIS-full scheme is not varied by the TSD, and is consistently smaller than that of the BOX scheme regardless of the TSD.Consequently, the TIS-full scheme with the smallest FoM scheme, the Cgg does not rely on the TSD, as shown in Figure 7b.Therefore, the TIS-full scheme is also used only for a comparison.The Ion and Cgg in the on-state (Cgg_on) in the four schemes are summarized in Figure 8.The TIS-full scheme has almost the same Ion as the TIS scheme.However, Cgg_on is reduced by up to 1.6% and 7.1% in the TIS-full scheme compared with the TIS scheme for n/pFETs.For a fair performance comparison, it is necessary to account for static power consumption.Figure-of-merit (FoM) is defined as RC delay/|log10(Ioff × VDD)|, where RC delay = Cgg_on × VDD/Ion.The reason that log10 is taken for the static power term is that the contribution of static power should not be overestimated.The smaller the FoM, the better the electrical performance.Figure 9 illustrates the FoM as a function of the TSD and SHE in the four schemes.First, in the Conv scheme, the FoM increases significantly with a large TSD due to the leakage current, which spikes sharply with increasing TSD.As a result, the Conv scheme exhibits the worst device performance with TSD = 6 nm.Second, the FoM in the TIS scheme does not vary much with larger TSD, except for the pFETs under the SHE.The pFETs with TSD = 0 nm show a smaller FoM than the BOX scheme, but it increases significantly as the TSD becomes larger due to increased Cgg (Figure 6b).Third, the FoM in the TIS-full scheme is not varied by the TSD, and is consistently smaller than that of the BOX scheme regardless of the TSD.Consequently, the TIS-full scheme with the smallest FoM   For a fair performance comparison, it is necessary to account for static power consumption.Figure-of-merit (FoM) is defined as RC delay/|log 10 (I off × V DD )|, where RC delay = C gg_on × V DD /I on .The reason that log 10 is taken for the static power term is that the contribution of static power should not be overestimated.The smaller the FoM, the better the electrical performance.Figure 9 illustrates the FoM as a function of the T SD and SHE in the four schemes.First, in the Conv scheme, the FoM increases significantly with a large T SD due to the leakage current, which spikes sharply with increasing T SD .As a result, the Conv scheme exhibits the worst device performance with T SD = 6 nm.Second, the FoM in the TIS scheme does not vary much with larger T SD , except for the pFETs under the SHE.The pFETs with T SD = 0 nm show a smaller FoM than the BOX scheme, but it increases significantly as the T SD becomes larger due to increased C gg (Figure 6b).Third, the FoM in the TIS-full scheme is not varied by the T SD , and is consistently smaller than that of the BOX scheme regardless of the T SD .Consequently, the TIS-full scheme with the smallest FoM shows the best electro-thermal performance in single-device operation under steady-state conditions.
shows the best electro-thermal performance in single-device operation under steady-state conditions.

Electro-Thermal Performance of the Three-Stage Ring Oscillator in the 3D Mixed-Mode Simulation
Although a steady-state operation of devices offers insights into their characteristics, it can lead to an overestimation of the device temperature.In contrast to steady-state operation, where the cooling of the device is not considered, a circuit operate under transient conditions cycles through heating and cooling periodically.Therefore, circuit-level performance evaluation is essential to compare the electro-thermal performance of the four schemes.In Section B, the NSFET-based three-stage ring oscillator (RO) is simulated using 3D mixed-mode simulation (Figure 10) [15].In mixed-mode simulation, the process-simulated devices are first integrated directly into the netlist of the circuit, and then the equations for the devices and the circuit are solved numerically at the same time.Despite the high CPU time required for this, the 3D mixed-mode simulation delivers much more accurate results than the compact model-based SPICE circuit simulation.In particular, the SHE-related physical effects on the transistor, such as the increased carrier density and 3.2.Electro-Thermal Performance of the Three-Stage Ring Oscillator in the 3D Mixed-Mode Simulation Although a steady-state operation of devices offers insights into their characteristics, it can lead to an overestimation of the device temperature.In contrast to steady-state operation, where the cooling of the device is not considered, a circuit operate under transient conditions cycles through heating and cooling periodically.Therefore, circuitlevel performance evaluation is essential to compare the electro-thermal performance of the four schemes.In Section B, the NSFET-based three-stage ring oscillator (RO) is simulated using 3D mixed-mode simulation (Figure 10) [15].In mixed-mode simulation, the processsimulated devices are first integrated directly into the netlist of the circuit, and then the equations for the devices and the circuit are solved numerically at the same time.Despite the high CPU time required for this, the 3D mixed-mode simulation delivers much more accurate results than the compact model-based SPICE circuit simulation.In particular, the SHE-related physical effects on the transistor, such as the increased carrier density and reduced κ at an elevated temperature, are still not accurately captured in compact SPICE models.reduced κ at an elevated temperature, are still not accurately captured in compact SPICE models.Figure 11 illustrates the transient voltage waveforms in the three-stage RO.After VDD reaches its nominal value and a warm-up time of several hundred picoseconds has elapsed, the RO circuit begins to produce stable oscillation waveforms.The device temperature also oscillates with repeated heating and cooling in response to the transient voltage waveforms (Figure 12).In contrast to the Tmax under a steady-state condition where |VGS| and |VDS| are fixed at the VDD of 0.7 V and the cooling period is not considered, Tmax under the RO operation is much lower.This is because VGS and VDS oscillate rapidly within the range of 0 to VDD, and therefore, heat does not accumulate as much as in the steady state.Conv, TIS, and TIS-full schemes exhibit similar Tmax in 1 ns after RO operation (nFET: 314.0 K, pFET: 310.0 K).However, the BOX scheme still shows an approximately 2.6 and 2.1 K higher Tmax than the other schemes in n/pFET, respectively.Figure 11 illustrates the transient voltage waveforms in the three-stage RO.After V DD reaches its nominal value and a warm-up time of several hundred picoseconds has elapsed, the RO circuit begins to produce stable oscillation waveforms.The device temperature also oscillates with repeated heating and cooling in response to the transient voltage waveforms (Figure 12).In contrast to the T max under a steady-state condition where |V GS | and |V DS | are fixed at the V DD of 0.7 V and the cooling period is not considered, T max under the RO operation is much lower.This is because V GS and V DS oscillate rapidly within the range of 0 to V DD , and therefore, heat does not accumulate as much as in the steady state.Conv, TIS, and TIS-full schemes exhibit similar T max in 1 ns after RO operation (nFET: 314.0 K, pFET: 310.0 K).However, the BOX scheme still shows an approximately 2.6 and 2.1 K higher T max than the other schemes in n/pFET, respectively.
For a more accurate comparison of electro-thermal performance between the four schemes, f osc and T max after 10 cycles (T max_10cy ) after the end of the warm-up period are examined under an iso-leakage condition (I off_n = I off_p = 1 nA) (Figure 13).In the Conv scheme, f osc decreases drastically when T SD exceeds 2 nm, and T max_10cy also drops accordingly.Moreover, the RO with a T SD ≥ 6 nm does not oscillate due to the very low drive current.In contrast, in TIS and TIS-full schemes, the f osc and T max_10cy are almost retained regardless of the T SD .Comparing the TIS, TIS-full, and BOX schemes, they exhibit almost the same f osc .However, it is observed that T max_10cy is 1.5 K and 1.7 K higher in the BOX scheme for n/pFET, respectively.Figure 11 illustrates the transient voltage waveforms in the three-stage RO.After VDD reaches its nominal value and a warm-up time of several hundred picoseconds has elapsed, the RO circuit begins to produce stable oscillation waveforms.The device temperature also oscillates with repeated heating and cooling in response to the transient voltage waveforms (Figure 12).In contrast to the Tmax under a steady-state condition where |VGS| and |VDS| are fixed at the VDD of 0.7 V and the cooling period is not considered, Tmax under the RO operation is much lower.This is because VGS and VDS oscillate rapidly within the range of 0 to VDD, and therefore, heat does not accumulate as much as in the steady state.Conv, TIS, and TIS-full schemes exhibit similar Tmax in 1 ns after RO operation (nFET: 314.0 K, pFET: 310.0 K).However, the BOX scheme still shows an approximately 2.6 and 2.1 K higher Tmax than the other schemes in n/pFET, respectively.For a more accurate comparison of electro-thermal performance between the four schemes, fosc and Tmax after 10 cycles (Tmax_10cy) after the end of the warm-up period are examined under an iso-leakage condition (Ioff_n = Ioff_p = 1 nA) (Figure 13).In the Conv scheme, fosc decreases drastically when TSD exceeds 2 nm, and Tmax_10cy also drops accordingly.Moreover, the RO with a TSD ≥ 6 nm does not oscillate due to the very low drive current.In contrast, in TIS and TIS-full schemes, the fosc and Tmax_10cy are almost retained regardless of the TSD.Comparing the TIS, TIS-full, and BOX schemes, they exhibit almost the same fosc.However, it is observed that Tmax_10cy is 1.5 K and 1.7 K higher in the BOX scheme for n/pFET, respectively.
On the other hand, in large-scale integration, many circuits are interconnected, so the load capacitance (CL) affecting the circuit operation is quite large.Therefore, the electrothermal performance of RO under the larger CL should also be investigated (Figure 14).The fosc value is almost the same for each scheme and inversely proportional to CL.This is because the larger CL is, the larger the capacitance of the capacitor whose transistor must generate the potential change for the RO to oscillate.Alternatively, Tmax_10cy increases with increasing CL in all schemes.This is because a lower fosc increases the heating time, and the time required to cool the transistor to 300 K increases more than the increased heating time [26].Consequently, more residual heat remains in the transistor when the fosc decreases.The TIS and TIS-full schemes exhibit almost the same Tmax_10cy, but the BOX schemes exhibit a higher Tmax_10cy than the others.Moreover, the Tmax_10cy differences become larger as the CL increases.The Tmax_10cy differences increase from 1.5 K (1.7 K) with CL = 1 fF to 4.8 K (3.0 K) with CL = 10 fF for n(p)FET.This implies that the electro-thermal performance superiority of the TIS scheme may become more evident in SoC applications where the scale and complexity of integrated circuits continue to increase.Therefore, an RO consisting of NSFETs with TIS and TIS-full schemes can achieve the same electrical performance at lower device temperatures compared to the BOX scheme.Moreover, this superiority of TIS and TIS-full schemes becomes even more evident in circuits with a larger CL.On the other hand, in large-scale integration, many circuits are interconnected, so the load capacitance (C L ) affecting the circuit operation is quite large.Therefore, the electrothermal performance of RO under the larger C L should also be investigated (Figure 14).The f osc value is almost the same for each scheme and inversely proportional to C L .This is because the larger C L is, the larger the capacitance of the capacitor whose transistor must generate the potential change for the RO to oscillate.Alternatively, T max_10cy increases with increasing C L in all schemes.This is because a lower f osc increases the heating time, and the time required to cool the transistor to 300 K increases more than the increased heating time [26].Consequently, more residual heat remains in the transistor when the f osc decreases.The TIS and TIS-full schemes exhibit almost the same T max_10cy , but the BOX schemes exhibit a higher T max_10cy than the others.Moreover, the T max_10cy differences become larger as the C L increases.The T max_10cy differences increase from 1.5 K (1.7 K) with C L = 1 fF to 4.8 K (3.0 K) with C L = 10 fF for n(p)FET.This implies that the electro-thermal performance superiority of the TIS scheme may become more evident in SoC applications where the scale and complexity of integrated circuits continue to increase.Therefore, an RO consisting of NSFETs with TIS and TIS-full schemes can achieve the same electrical performance at lower device temperatures compared to the BOX scheme.Moreover, this superiority of TIS and TIS-full schemes becomes even more evident in circuits with a larger C L .

Conclusions
In this study, an accurate and comprehensive evaluation of the electro-thermal performance of NSFETs with different trpbt-controlling schemes ranging from single-device to three-stage RO circuits was performed.When evaluated for a single-device operation, the TIS scheme not only controlled the trpbt effectively, but also had a lower Tmax than the BOX scheme because heat dissipation was not hindered in the TIS scheme.The Tmax of TIS-NSFETs was 59.6 K and 50.4K lower than that of BOX-NSFETs in n/pFETs, respectively.However, the TIS scheme has the disadvantage that Cgg_on increases with increasing TSD, resulting in a larger RC delay.This issue is particularly pronounced in pFETs, where the electro-thermal performance is worse than that of the BOX scheme when TSD exceeds 2 nm.Meanwhile, the TIS-full scheme, which increases the height of the TIS by removing SiGe0.3 residues below the TIS, enabled a reduction in Cgg_on and exhibited the best electrothermal performance among the various schemes under iso-leakage condition.Moreover, at the RO circuit level, the TIS and TIS-full schemes exhibited slightly lower Tmax_10cy while providing comparable fosc with the BOX scheme.However, the thermal superiority was more pronounced as the CL added to the RO becomes larger.When CL was 1 fF, the difference in Tmax_10cy of the TIS scheme was 1.5 and 1.7 K lower than that of the BOX scheme for

Conclusions
In this study, an accurate and comprehensive evaluation of the electro-thermal performance of NSFETs with different tr pbt -controlling schemes ranging from single-device to three-stage RO circuits was performed.When evaluated for a single-device operation, the TIS scheme not only controlled the tr pbt effectively, but also had a lower T max than the BOX scheme because heat dissipation was not hindered in the TIS scheme.The T max of TIS-NSFETs was 59.6 K and 50.4K lower than that of BOX-NSFETs in n/pFETs, respectively.However, the TIS scheme has the disadvantage that C gg_on increases with increasing T SD , resulting in a larger RC delay.This issue is particularly pronounced in pFETs, where the electro-thermal performance is worse than that of the BOX scheme when T SD exceeds 2 nm.Meanwhile, the TIS-full scheme, which increases the height of the TIS by removing SiGe 0.3 residues below the TIS, enabled a reduction in C gg_on and exhibited the best electro-thermal performance among the various schemes under iso-leakage condition.Moreover, at the RO circuit level, the TIS and TIS-full schemes exhibited slightly lower T max_10cy while providing comparable f osc with the BOX scheme.However, the thermal superiority was more pronounced as the C L added to the RO becomes larger.When C L was 1 fF, the difference in T max_10cy of the TIS scheme was 1.5 and 1.7 K lower than that of the BOX scheme for n/pFETs, respectively.However, when C L increased to 10 fF, the difference grew to 4.8 and 3.0 K for n/pFETs, respectively.In conclusion, it is highly recommended to use the TIS or TIS-full scheme to simultaneously control tr pbt and improve electro-thermal performance in SoC products adapting sub-3 nm node NSFETs.

Figure 1 .
Figure 1.(a) Three-dimensional structure and cross-sections of Conv-NSFETs, and (b) structural comparison of the Conv, TIS, and BOX schemes.

Figure 1 .
Schemes to control the tr pbt

Figure 2 .
Figure 2. Transfer characteristics and Ion for various TSD with and without SHE in (a) Conv, (b) TIS, and BOX schemes (the transfer curves with and without SHE almost overlaps).

Figure 2 .
Figure 2. Transfer characteristics and I on for various T SD with and without SHE in (a) Conv, (b) TIS, and BOX schemes (the transfer curves with and without SHE almost overlaps).

Figure 3 .
Figure 3. (a) Transfer characteristics of NSFETs with and without SHE, and (b) Tmax in the Conv scheme.(c) Carrier density and (d) mobility with or without SHE in the Conv scheme.

Figure 3 .
Figure 3. (a) Transfer characteristics of NSFETs with and without SHE, and (b) T max in the Conv scheme.(c) Carrier density and (d) mobility with or without SHE in the Conv scheme.

Figure 4 .
Figure 4. Lattice temperature profiles at on-state in the Conv, TIS, and BOX schemes.The marked points indicate Tmax.

Figure 5 .
Figure 5. (a) Tmax_on compared to different TSD in Conv, TIS, and BOX schemes.(b,c) Vco comparison in TIS and BOX schemes for n/pFETs.

Figure 4 .
Figure 4. Lattice temperature profiles at on-state in the Conv, TIS, and BOX schemes.The marked points indicate T max .

Figure 4 .
Figure 4. Lattice temperature profiles at on-state in the Conv, TIS, and BOX schemes.The marked points indicate Tmax.

Figure 5 .
Figure 5. (a) Tmax_on compared to different TSD in Conv, TIS, and BOX schemes.(b,c) Vco comparison in TIS and BOX schemes for n/pFETs.

Figure 5 .
Figure 5. (a) T max_on compared to different T SD in Conv, TIS, and BOX schemes.(b,c) V co comparison in TIS and BOX schemes for n/pFETs.

Figure 6 .
Figure 6.Cgg-VGS curves for different TSD with and without SHE in (a) Conv, (b) TIS, and BOX schemes (inset: Cgg at high and VGS in the TIS scheme).

Figure 7 .
Figure 7. (a) Structural comparison of the TIS-full scheme and the TIS scheme; (b) Cgg-VGS curves for different TSD with and without SHE in the TIS-full scheme.

Figure 6 .
Figure 6.C gg -V GS curves for different T SD with and without SHE in (a) Conv, (b) TIS, and BOX schemes (inset: C gg at high and V GS in the TIS scheme).

Figure 6 .
Figure 6.Cgg-VGS curves for different TSD with and without SHE in (a) Conv, (b) TIS, and BOX schemes (inset: Cgg at high and VGS in the TIS scheme).

Figure 7 .
Figure 7. (a) Structural comparison of the TIS-full scheme and the TIS scheme; (b) Cgg-VGS curves for different TSD with and without SHE in the TIS-full scheme.

Figure 7 .
Figure 7. (a) Structural comparison of the TIS-full scheme and the TIS scheme; (b) C gg -V GS curves for different T SD with and without SHE in the TIS-full scheme.

Figure 8 .
Figure 8.Comparison of Ion and Cgg_on in the Conv, TIS, TIS-full, and BOX schemes.

Figure 8 .
Figure 8.Comparison of I on and C gg_on in the Conv, TIS, TIS-full, and BOX schemes.

Figure 8 .
Figure 8.Comparison of Ion and Cgg_on in the Conv, TIS, TIS-full, and BOX schemes.

Figure 10 .
Figure 10.Schematic representation of the 3D mixed-mode simulation for a three-stage ring oscillator.

Nanomaterials 2024 ,
14,  x FOR PEER REVIEW 10 of 14 reduced κ at an elevated temperature, are still not accurately captured in compact SPICE models.

Figure 10 .
Figure 10.Schematic representation of the 3D mixed-mode simulation for a three-stage ring oscillator.

Figure 12 .
Figure 12.Transient Tmax response of the devices in each stage of the 3-stage RO.

Figure 12 .
Figure 12.Transient T max response of the devices in each stage of the 3-stage RO.Nanomaterials 2024, 14, x FOR PEER REVIEW 12 of 14

Figure 13 .Figure 13 .
Figure 13.fosc and Tmax_10cy of the 3-stage RO in the Conv, TIS, TIS-full, and BOX schemes under the condition of iso-leakage.

Figure 13 .
Figure 13.fosc and Tmax_10cy of the 3-stage RO in the Conv, TIS, TIS-full, and BOX schemes under the condition of iso-leakage.

Figure 14 .
Figure 14.(a) fosc and (b) Tmax_10cy as a function of CL of the 3-stage RO in TIS, TIS-full, and BOX schemes (fosc is almost the same for all schemes, and they almost overlap).

Figure 14 .
Figure 14.(a) f osc and (b) T max_10cy as a function of C L of the 3-stage RO in TIS, TIS-full, and BOX schemes (f osc is almost the same for all schemes, and they almost overlap).

Table 1 .
Geometrical and device parameters for sub-3 nm node NSFETs.