Search Results (872)

Nanotechnology has emerged as a key driver in radioisotope batteries, which offer unique advantages for long-term, maintenance-free energy supply in deep space exploration, medical implants, and nuclear waste utilization. This review summarizes recent progress in applying nanomaterials and nanostructures to overcome the limitations of nuclear batteries, including low energy conversion efficiency and poor stability. The main content focuses on the three primary conversion mechanisms of thermoelectric, radio-voltaic, and radio-photovoltaic batteries, discussing high-performance thermoelectric nanomaterials such as SiGe alloys, wide-bandgap semiconductors including diamond and SiC for enhanced carrier collection, and nanoscale radionuclide ources to mitigate self-absorption losses. This review further elaborates on how nanostructure regulation and interface engineering have significantly improved carrier collection efficiency and device stability. These advances have enabled notable civilian applications, such as the BV100 and “Zhulong No.1” nuclear batteries. Despite this progress, challenges remain in ensuring long-term material stability under extreme environments, maintaining performance consistency during macroscopic device integration, and addressing the high fabrication costs. The review concludes by outlining future research directions, including the development of novel nanomaterial systems, innovative nanostructure designs, scalable manufacturing processes, and enhanced device stability and safety, to further advance next-generation radioisotope batteries. Full article

The semiconductor industry has long relied on Statistical Process Control (SPC) for yield and reliability management. In early technology nodes, classic univariate tools such as Shewhart charts, cumulative sums (CUSUM), exponentially weighted moving averages (EWMA), and the Cp/Cpk exponent could effectively monitor a finite set of key variables. However, sub-5nm and emerging 3 nm technologies have fundamentally changed the statistical environment. Advanced patterning, high-aspect-ratio etching, atomic layer deposition (ALD), chemical-mechanical polishing (CMP), and novel materials have drastically narrowed the process window. At these scales, nanometer-level deviations in critical dimensions (CD), overlay, or surface roughness can significantly impact yield. Simultaneously, modern wafer fabs generate massive amounts of high-frequency sensor data and high-dimensional metrology data. Traditional SPC assumptions—such as independence, normality, low dimensionality, and stationarity—often do not hold. Semiconductor data exhibits: (i) extremely high-dimensionality and strong intervariate correlations; (ii) a hierarchical structure encompassing fab → tooling → chamber → recipe → batch → wafer → field; and (iii) metrological delays and sampling limitations leading to incomplete and asynchronous observations. To address these challenges, this paper reviews advanced statistical methods applicable to wafer fabrication. These methods include multivariate statistical process control (MSPC) approaches such as Hotelling T² statistics, PCA/PLS combining T² and Q statistics, contribution diagnostics, time-series drift and change point detection, and Bayesian hierarchical modeling for uncertainty-aware monitoring in data-limited scenarios. Furthermore, we discuss how to integrate these methods with fault detection and classification (FDC), line-to-line monitoring (R2R), advanced process control (APC), and manufacturing execution systems (MES). This paper focuses on scalable, interpretable, and maintainable implementations that transform statistical analysis from a passive monitoring tool into an active component of data-driven fab control. Full article

Three-dimensional integrated circuit (3D IC) packaging and heterogeneous integration have emerged as central pillars of contemporary semiconductor scaling. Yet, the multi-physics coupling inherent to stacked architectures manifesting as thermal hot spots, warpage-induced stresses, and interconnect aging demands monitoring and control capabilities that surpass traditional offline metrology. Although Digital Twin (DT) technology provides a principled route to real-time reliability management, the existing literature remains fragmented and frequently blurs the distinction between static multi-physics simulation workflows and truly dynamic, closed-loop twins. This critical review addresses these deficiencies through three main contributions. First, we clarify the Digital Twin hierarchy to resolve terminological ambiguity between digital models, shadows, and twins. Second, we synthesize three foundational enabling technologies. We examine physics-based modeling, emphasizing the shift from finite-element analysis (FEA) to real-time surrogates. We analyze data-driven paradigms, highlighting virtual metrology (VM) for inferring latent metrics. Finally, we explore in situ sensing, which serves as the “nervous system” coupling the physical stack to its virtual counterpart. Third, beyond a descriptive survey, we outline a possible hybrid DT architecture that leverages physics-informed machine learning (e.g., PINNs) to help reconcile data scarcity with latency constraints. Finally, we outline a standards-aligned roadmap incorporating IEEE 1451 and UCIe protocols to support the transition from passive digital shadows toward more adaptive and fully coupled Digital Twin frameworks for 3D IC manufacturing and field operation. Full article

X-ray techniques provide powerful, non-destructive tools for structural characterization in semiconductor manufacturing and advanced packaging. Their strong penetration capability and sensitivity to multiple contrast mechanisms enable the investigation of lattice structure, strain, defects, interfaces, and elemental distribution across a wide range of length scales. As semiconductor devices evolve toward three-dimensional architectures and heterogeneous integration, there is an increasing demand for characterization approaches capable of probing complex, buried, and multi-scale structures in a consistent manner. In this review, we present a systematic overview of X-ray characterization techniques for advanced semiconductor systems, including diffraction-based methods, small-angle scattering, computed tomography, X-ray fluorescence, and spectroscopic approaches. These techniques are discussed in terms of the type of structural, morphological, and compositional information they provide, their applicable length scales, and their strengths and limitations in addressing key challenges such as thin films, high-aspect-ratio structures, buried interfaces, and full wafers. Particular attention is given to the complementary nature of different X-ray modalities and their roles in addressing practical metrology problems. The limitations associated with resolution, model dependence, and data interpretation are also outlined. Finally, emerging opportunities in laboratory X-ray sources, synchrotron-based methods, and integrated characterization strategies are briefly discussed. This review aims to provide a unified perspective for understanding and integrating X-ray techniques, offering insights into their roles in addressing the growing complexity of next-generation semiconductor devices. Full article

The relentless miniaturization of semiconductor components and Printed Circuit Boards (PCBs) has rendered Automated Optical Inspection (AOI) of micro-defects a critical bottleneck in modern manufacturing and metrology. While in-line inspection systems offer economically viable and scalable quality control solutions, they impose stringent constraints on both inference latency and detection robustness—particularly for diminutive, sparsely distributed defects (e.g., mouse bites, pinholes) amidst complex, repetitive circuit topologies. To bridge this gap, we present a semantic-enhanced FCOS framework specifically engineered for micro-defect inspection. Our approach introduces two synergistic innovations: (1) a Semantic-Guided Upsampling Unit (SGU) that adaptively reweights channel–spatial features to reconcile the semantic disparity between shallow textural details and deep contextual representations; and (2) a Sparse Center-ness Calibration (SCC) module that enforces high-confidence, spatially sparse supervision to sharpen localization precision and suppress false positives. The SGU is integrated within a Progressive Semantic-Enhanced Feature Pyramid Network (PSE-FPN) that extends multi-scale representations to stride-4 (P2) resolution, while the SCC module is embedded directly into the detection head. Comprehensive evaluations on MS COCO and the real-world DeepPCB dataset validate the efficacy of our design. On COCO, our model achieves 41.8% AP with real-time throughput of 28 FPS on a single NVIDIA 1080Ti GPU. A lightweight variant further attains 41.6% AP at 42 FPS, accommodating high-throughput production environments. For PCB defect detection, the framework delivers 98.7% mAP@0.5, substantially outperforming contemporary detectors. These results demonstrate that semantics-aware, lightweight architectures enable scalable, real-time quality assurance in semiconductor manufacturing. Full article

This study proposes EvoDeep-Quality, a closed-loop hybrid framework integrating deep learning-based perception with multi-objective evolutionary optimization for adaptive quality control in smart manufacturing. The architecture combines a CNN-LSTM network for real-time spatiotemporal quality prediction with an NSGA-III-based optimization unit to balance conflicting objectives of quality, cost, and energy efficiency. A continuous adaptive learning loop addresses concept drift and process variability. Evaluated on an industrial-inspired synthetic dataset of textile blends (N = 5000) and validated on the real-world SECOM semiconductor manufacturing dataset, the framework demonstrates strong predictive capability (R² = 0.947 ± 0.012, MAE = 0.035 ± 0.003) and significant manufacturing performance improvements, including a 23.5% quality enhancement and an 8.7–12.3% operational cost reduction compared to traditional and standalone AI models. Statistical significance testing (paired t-test, p < 0.01) confirms the superiority of the proposed approach. This deep-evolutionary framework advances proactive quality assurance and adaptive process control, offering a scalable solution aligned with Industry 4.0 and 5.0 paradigms. Full article

Wafer map defect pattern classification supports quality monitoring in semiconductor manufacturing, but public benchmark datasets such as WM-811K exhibit extreme class imbalance, where majority classes can dominate standard metrics. This study aims to improve minority class performance while maintaining inference efficiency. Building on an iFormer-based hybrid backbone, we propose the Pattern-Selective Sequential Hybrid Network (PSS-HNet), which redesigns attention blocks to sequentially integrate local interaction (Modulated Convolution) and global interaction (Modulated Axial Attention) and applies sigmoid-based gating to control contextual information injection. Experiments on WM-811K (9 classes) compare iFormer (baseline), Axial-only, Axial+Modulation, and PSS-HNet using macro-averaged metrics as primary indicators, along with class-wise analysis and efficiency evaluation. PSS-HNet improves Macro-Recall by 1.02 percentage points (from 0.8852 to 0.8954) and Macro-F1 by 0.54 percentage points (from 0.9044 to 0.9098) over the baseline while maintaining similar accuracy. It also reduces computational cost and inference latency to 0.754 G FLOPs, 4.381 M parameters, and 7.682 ms, compared with 1.103 G FLOPs, 6.245 M parameters, and 8.666 ms for the baseline. Overall, selective sequential local–global integration provides a favorable balance between minority class performance and efficiency. Full article

With the advancement of semiconductor technology, the Network-on-Chip (NoC) has become a critical architecture for communication between multiple cores. However, failures caused by factors such as manufacturing processes can degrade its performance and stability, making efficient topology reconstruction algorithms particularly important. Conventional 2D mesh reconstruction yields irregular topologies, increasing network latency and complicating system scheduling and deployment. While REmesh structures maintain topological regularity, they struggle to balance algorithmic complexity, success rates, and reconstruction costs. This paper proposes a monotonic path shift (MPS) topological reconstruction algorithm for REmesh NoCs with core-level redundancy, based on local rapid recovery. This algorithm localizes reconstruction decisions by establishing monotonic paths between failed cores and redundant cores for recovery. It incorporates region retention and local fallback mechanisms to suppress path conflicts among multiple failed cores. Theoretical analysis shows that MPS provides an upper bound on the runtime of the algorithm, significantly reducing its time complexity. Experimental results indicate that its reconstruction success rate is comparable to that of the ACTR algorithm, with both maintaining a high repair rate even under high fault density. In terms of core reuse rate, MPS achieves significant improvements over BTTR, BSTR, and ACTR, with an average increase of approximately 10% under low-fault conditions, effectively utilizing remaining computational resources. Concurrently, the algorithm substantially reduces average migration time, accelerating recovery by several orders of magnitude in large-scale low-fault scenarios and markedly lowering online recovery overhead. Full article

Wafer defect analysis is important for semiconductor manufacturing, but labeled data are limited, and class distributions are highly imbalanced. We present a semi-supervised framework with two lightweight hybrid CNN–Transformer models for wafer defect classification and segmentation. For classification, HybridCNN-ViT combines CNN-based local feature extraction with Transformer-based global context modeling, and adopts a three-stage progressive pseudo-labeling strategy to leverage unlabeled samples. The pseudo-label selection mechanism is systematically calibrated to improve pseudo-label reliability under limited labeled data. For segmentation, ConvoFormer-UNet integrates convolution-enhanced embeddings with Transformer blocks to balance boundary detail and global context. On the public WM-811K dataset, HybridCNN-ViT achieves 98.72% accuracy and 0.9985 macro-AUC under the semi-supervised setting for classification, while ConvoFormer-UNet reaches 99.19% IoU for segmentation with fewer parameters than several baselines. We also report efficiency on a single GPU to illustrate practical inference speed. Full article

Jet machining is widely utilized in innovative technology industries, such as aerospace and semiconductors, due to its minimal thermal damage. However, with the increasingly stringent surface quality requirements of modern manufacturing, conventional jet technologies face limitations in achieving ultra-precision surface finishing and high material removal rates. To address these challenges and adapt to this new situation, multi-energy field-assisted jet machining has emerged as a novel concept, integrating laser, ultrasonic, and magnetic fields. This paper reviews the scientific development and recent advancements of these hybrid technologies within the field of ultra-precision machining. The physical interaction mechanisms between the auxiliary energy fields and the waterjet are elucidated. Specifically, the effects of laser thermal softening, ultrasonic cavitation, and magnetic focusing on new mechanisms of material removal and surface topography are systematically analyzed. The process capabilities and applications of each method are evaluated. Finally, current technical challenges are identified, and the future trends in ultra-precision jet machining are discussed. Full article

In semiconductor fabrication, abnormal behavior may first appear in a small subset of serial numbers before it is reflected in lot-level yield metrics. We present a monitoring framework that detects measurement item outliers using Z-scores, aggregates them into a serial-level cumulative-risk score, provides exploratory views of lot- and site-level trends, and ranks high-risk serials for follow-up. The approach is evaluated on an industrial semiconductor manufacturing dataset comprising 14,142 unique serials (${\mathrm{N}}_{\mathrm{s}\mathrm{e}\mathrm{r}\mathrm{i}\mathrm{a}\mathrm{l}}$ = 14,142). Because most TestResult labels are PASS, label-based yield shows little variation. In this setting, label-based yield alone is not informative enough for early monitoring, so we use outlier-based yield as the primary metric, defined as the proportion of serials with cumulative risk below the threshold ($\mathrm{R}\left(\mathrm{s}\right)<\mathrm{\tau }$, where $\mathrm{\tau }=10$). A sensitivity study of the outlier threshold $\mathrm{\kappa }$ ($\mathrm{\sigma }$-multiplier) shows that yield varies widely, from 61.66% at $\mathrm{\kappa }=3$ to above 99% at $\mathrm{\kappa }\ge 7$. This result shows the trade-off between detection sensitivity and inspection workload. Case studies of top-ranked serials show two recurring patterns: cumulative risk is driven either by isolated extreme deviations or by the accumulation of moderate deviations across multiple items. These results support the use of the proposed score for inspection prioritization. Full article

In this paper, we propose a novel method which utilizes samples of measured product quality characteristics to efficiently estimate the probabilities of those quality characteristics being within the desired specifications and, consequently, the process yield. Specifically, when dealing with 1D Gaussian distributions, we formally prove that the proposed yield estimator asymptotically gives a lower Mean Squared Error compared to the best unbiased estimator. In order to enable maximization of yield, this novel estimator is incorporated into the framework of Bayesian Optimization which iteratively seeks controllable tool parameters under which the outgoing product yield is maximized. The newly proposed yield maximization method is demonstrated in an application involving high-fidelity simulations of a reactive ion etch chamber, a tool component commonly used in semiconductor manufacturing. The aim of these simulations was to rapidly and reliably determine tool parameters that maximize the probability of delivering desired plasma density characteristics under stochastic variations in chamber conditions. The novel yield estimation and optimization methods show superiority when the number of experimental observations is limited and the distributions of outgoing product characteristics can be approximated well by a Gaussian distribution. Full article

This review examines the transformative interplay between computing chips and Artificial Intelligence (AI), driving a revolution across various industries. First, the broader artificial intelligence and semiconductor ecosystem is analyzed, including hardware manufacturers, software frameworks, and system integration. Next, the development prospects are examined, revealing current challenges such as power consumption, manufacturing complexity, supply chain constraints, and ethical considerations. Further discussion focuses on cloud-edge collaboration in relation to system architecture and workload allocation strategies. Then, cutting-edge AI technologies are analyzed, and key insights are summarized. Finally, the overall trends in artificial intelligence and the chip industry are summarized, clearly presenting the findings for the future and making a unique contribution to this review. Full article

In industrial imaging scenarios, semiconductor wafer defect classification is crucial for chip manufacturing yield and reliability. However, numerous challenges persist, including weak imaging responses and detail loss during downsampling, complex backgrounds that interfere with feature extraction, and the trade-off between performance and efficiency on edge devices. Traditional CNNs and ViTs exhibit limitations in modeling long-range dependencies and managing edge deployment costs. To address these issues, we leverage the VMamba architecture, a Visual State Space Model (SSM) that achieves global contextual modeling with linear computational complexity. Based on the VMamba architecture, we propose FCS-VMamba, a domain-adapted model that integrates three core modules, namely Frequency Attention (FA), Cross-Layer Cross-Attention (CLCA), and Saliency Feature Suppression (SFS). The experimental results show that FCS-VMamba achieved $86.06\%$ macro-precision and $87.91\%$ Top-1 accuracy with only $1.2$ M parameters. These results demonstrate that FCS-VMamba provides a practical and parameter-efficient baseline for industrial wafer defect recognition. Full article

Fault Detection and Diagnosis (FDD) in complex industrial systems requires methods that can handle uncertain operating conditions, soft thresholds, evolving sensor behavior, and increasing volumes of heterogeneous data. Traditional model-based or rule-driven approaches offer interpretability but lack adaptability, while purely data-driven and Large Language Model (LLM)-based methods often struggle with consistency, traceability, and causal grounding. Dynamic Master Logic (DML) provides a causal and temporal reasoning structure with fuzzy rules that capture gradual drift, soft limits, and asynchronous sensor signals while preserving traceability and deterministic evidence propagation. Building on this foundation, this paper presents a DML–LLM hybrid architecture that integrates targeted LLM inference to interpret unstructured information such as logs, notes, or retrieved documents under controlled prompts that maintain domain constraints. The combined system integrates Bayesian updating, deterministic routing, and semantic interpretation into a unified FDD pipeline. In a semiconductor manufacturing case study, the proposed framework reduced time to detection (TTD) from 7.4 h to 1.2 h and improved the F1 score from 0.59 to 0.83 when compared with conventional Statistical Process Control (SPC) and Fault Detection and Classification (FDC) workflows. Provenance completeness increased from 18% to 96%, while engineer triage time was reduced from 72 min to 18 min per event. These results demonstrate that the hybrid framework provides a scalable and explainable approach to anomaly detection and fault diagnosis in sensor-rich industrial environments. Full article