Search Results (1,840)

To enhance the reliability of electric propulsion in electric aircraft and address power interruptions caused by current sensor failures, this study proposes a current sensorless fault-tolerant control strategy for permanent magnet synchronous motors (PMSMs) based on a long short-term memory (LSTM) network. First, a hierarchical architecture is constructed to fuse multi-phase electrical signals in the fault diagnosis layer (sliding mode observer). A symbolic function for the reaching law observer is designed based on Lyapunov theory, in order to generate current predictions for fault diagnosis. Second, when a fault occurs, the system switches to the LSTM reconstruction layer. Finally, gating units are used to model nonlinear dynamics to achieve direct mapping of speed/position to phase current. Verification using a physical prototype shows that the proposed method can complete mode switching within 10 ms after a sensor failure, which is 80% faster than EKF, and its speed error is less than 2.5%, fully meeting the high speed error requirements of electric aircraft propulsion systems (i.e., ≤3%). The current reconstruction RMSE is reduced by more than 50% compared with that of the EKF, which ensures continuous and reliable control while maintaining the stable operation of the motor and realizing rapid switching. The intelligent algorithm and sliding mode control fusion strategy meet the requirements of high real-time performance and provide a highly reliable fault-tolerant scheme for electric aircraft propulsion. Full article

Quantum computing, with its foundational principles of superposition and entanglement, has the potential to provide significant quantum advantages, addressing challenges that classical computing may struggle to overcome. As data generation continues to grow exponentially and technological advancements accelerate, classical machine learning algorithms increasingly face difficulties in solving complex real-world problems. The integration of classical machine learning with quantum information processing has led to the emergence of quantum machine learning, a promising interdisciplinary field. This work provides the reader with a bottom-up view of quantum circuits starting from quantum data representation, quantum gates, the fundamental quantum algorithms, and more complex quantum processes. Thoroughly studying the mathematics behind them is a powerful tool to guide scientists entering this domain and exploring their connection to quantum machine learning. Quantum algorithms such as Shor’s algorithm, Grover’s algorithm, and the Harrow–Hassidim–Lloyd (HHL) algorithm are discussed in detail. Furthermore, real-world implementations of quantum machine learning and quantum deep learning are presented in fields such as healthcare, bioinformatics and finance. These implementations aim to enhance time efficiency and reduce algorithmic complexity through the development of more effective quantum algorithms. Therefore, a comprehensive understanding of the fundamentals of these algorithms is crucial. Full article

This paper deals with a standard cell-based analog-in-concept pW-power building block as a comparator and a wake-up oscillator. Both topologies, traditionally conceived as an analog building block made by a custom process and supply voltage-dependent design flow, are designed only by using digital gates, enabling them to be automated and fully synthesizable. This further results in supply voltage scalability and regulator-less operation, allowing direct powering by an energy harvester without additional ancillary circuit blocks (such as current and voltage sources). In particular, the circuit similarities in implementing a rail-to-rail dynamic voltage comparator and a relaxation oscillator using only digital gates are discussed. The building blocks previously reported in the literature by the author will be described, and the common root of their design will be highlighted. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

Accurate wellbore trajectory prediction is of great significance for enhancing the efficiency and safety of directional drilling in coal mines. However, traditional mechanical analysis methods have high computational complexity, and the existing data-driven models cannot fully integrate non-sequential features such as stratum lithology. To solve these problems, this study proposes a parallel input gated recurrent unit (Pi-GRU) model based on the TensorFlow framework. The GRU network captures the temporal dependencies of sequence data (such as dip angle and azimuth angle), while the BP neural network extracts deep correlations from non-sequence features (such as stratum lithology), thereby achieving multi-source data fusion modeling. Orthogonal experimental design was adopted to optimize the model hyperparameters, and the ablation experiment confirmed the necessity of the parallel architecture. The experimental results obtained based on the data of a certain coal mine in Shanxi Province show that the mean square errors (MSE) of the azimuth and dip angle angles of the Pi-GRU model are 0.06° and 0.01°, respectively. Compared with the emerging CNN-BiLSTM model, they are reduced by 66.67% and 76.92%, respectively. To evaluate the generalization performance of the model, we conducted cross-scenario validation on the dataset of the Dehong Coal Mine. The results showed that even under unknown geological conditions, the Pi-GRU model could still maintain high-precision predictions. The Pi-GRU model not only outperforms existing methods in terms of prediction accuracy, with an inference delay of only 0.21 milliseconds, but also requires much less computing power for training and inference than the maximum computing power of the Jetson TX2 hardware. This proves that the model has good practicability and deployability in the engineering field. It provides a new idea for real-time wellbore trajectory correction in intelligent drilling systems and shows strong application potential in engineering applications. Full article

Bacteriophages (phages), the most abundant biological entities on Earth, have long served as both model systems and therapeutic tools. Recent advances in synthetic biology and genetic engineering have revolutionized the capacity to tailor phages with enhanced functionality beyond their natural capabilities. This review outlines the current landscape of synthetic and functional engineering of phages, encompassing both in-vivo and in-vitro strategies. We describe in-vivo approaches such as phage recombineering systems, CRISPR-Cas-assisted editing, and bacterial retron-based methods, as well as synthetic assembly platforms including yeast-based artificial chromosomes, Gibson, Golden Gate, and iPac assemblies. In addition, we explore in-vitro rebooting using TXTL (transcription–translation) systems, which offer a flexible alternative to cell-based rebooting but are less effective for large genomes or structurally complex phages. Special focus is given to the design of customized phages for targeted applications, including host range expansion via receptor-binding protein modifications, delivery of antimicrobial proteins or CRISPR payloads, and the construction of biocontained, non-replicative capsid systems for safe clinical use. Through illustrative examples, we highlight how these technologies enable the transformation of phages into programmable bactericidal agents, precision diagnostic tools, and drug delivery vehicles. Together, these advances establish a powerful foundation for next-generation antimicrobial platforms and synthetic microbiology. Full article

A chili pepper variety and origin detection system that integrates a field-programmable gate array (FPGA) with an electronic nose (e-nose) is proposed in this paper to address the issues of variety confusion and origin ambiguity in the chili pepper market. The system uses the AIRSENSE PEN3 e-nose from Germany to collect gas data from thirteen different varieties of chili peppers and two specific varieties of chili peppers originating from seven different regions. Model training is conducted via the proposed lightweight convolutional neural network ChiliPCNN. By combining the strengths of a convolutional neural network (CNN) and a multilayer perceptron (MLP), the ChiliPCNN model achieves an efficient and accurate classification process, requiring only 268 parameters for chili pepper variety identification and 244 parameters for origin tracing, with 364 floating-point operations (FLOPs) and 340 FLOPs, respectively. The experimental results demonstrate that, compared with other advanced deep learning methods, the ChiliPCNN has superior classification performance and good stability. Specifically, ChiliPCNN achieves accuracy rates of 94.62% in chili pepper variety identification and 93.41% in origin tracing tasks involving Jiaoyang No. 6, with accuracy rates reaching as high as 99.07% for Xianjiao No. 301. These results fully validate the effectiveness of the model. To further increase the detection speed of the ChiliPCNN, its acceleration circuit is designed on the Xilinx Zynq7020 FPGA from the United States and optimized via fixed-point arithmetic and loop unrolling strategies. The optimized circuit reduces the latency to 5600 ns and consumes only 1.755 W of power, significantly improving the resource utilization rate and processing speed of the model. This system not only achieves rapid and accurate chili pepper variety and origin detection but also provides an efficient and reliable intelligent agricultural management solution, which is highly important for promoting the development of agricultural automation and intelligence. Full article

The sustainable integration of Distributed Energy Resources (DER) with the next-generation distribution networks requires robust, adaptive, and accurate hosting capacity (HC) forecasting. Dynamic Operating Envelopes (DOE) provide real-time constraints for power import/export to the grid, ensuring dynamic DER integration and efficient network operation. However, conventional HC analysis and forecasting approaches struggle to capture temporal dependencies, the impact of DOE constraints on network operation, and uncertainty in DER output. This study introduces a dynamic optimization framework that leverages the benefits of the sensitivity gate of the Sensitivity-Enhanced Recurrent Neural Network (SERNN) forecasting model, Particle Swarm Optimization (PSO), and Bayesian Optimization (BO) for HC forecasting. The PSO determines the optimal weights and biases, and BO fine-tunes hyperparameters of the SERNN forecasting model to minimize the prediction error. This approach dynamically adjusts the import/export of the DER output to the grid by integrating the DOE constraints into the SG-PSO-BO architecture. Performance evaluation on the IEEE-123 test network and a real Australian distribution network demonstrates superior HC forecasting accuracy, with an $R^2$ score of 0.97 and 0.98, Mean Absolute Error (MAE) of 0.21 and 0.16, and Root Mean Square Error (RMSE) of 0.38 and 0.31, respectively. The study shows that the model effectively captures the non-linear and time-sensitive interactions between network parameters, DER variables, and weather information. This study offers valuable insights into advancing dynamic HC forecasting under real-time DOE constraints in sustainable DER integration, contributing to the global transition towards net-zero emissions. Full article

The internal combustion process in a boiler in power plants has a direct impact on boiler efficiency and NOx generation. The objective of this study is to propose an intelligent deep learning modeling and multi-objective optimization approach that considers NOx emission concentration and boiler thermal efficiency simultaneously for boiler combustion in power plants. Firstly, a hybrid deep learning model, namely, convolutional neural network–bidirectional gated recurrent unit (CNN-BiGRU), is employed to predict the concentration of NOx emissions and the boiler thermal efficiency. Then, based on the hybrid deep prediction model, variables such as primary and secondary airflow rates are considered as controllable variables. A single-objective optimization model based on an improved flow direction algorithm (IFDA) and a multi-objective optimization model based on NSGA-II are developed. For multi-objective optimization using NSGA-II, the average NOx emission concentration is reduced by 5.01%, and the average thermal efficiency is increased by 0.32%. The objective functions are to minimize the boiler thermal efficiency and the concentration of NOx emissions. Comparative analysis of the experiments shows that the NSGA-II algorithm can provide a Pareto optimal front based on the requirements, resulting in better results than single-objective optimization. The effectiveness of the NSGA-II algorithm is demonstrated, and the obtained results provide reference values for the low-carbon and environmentally friendly operation of coal-fired boilers in power plants. Full article

The increasing demand for high-speed, energy-efficient computing has propelled the development of integrated photonic logic gates, which utilize the speed of light to surpass the limitations of traditional electronic circuits. These gates enable ultrafast, parallel data processing with minimal power consumption, making them ideal for next-generation computing, telecommunications, and quantum applications. Recent advancements in nanofabrication, nonlinear optics, and phase-change materials have facilitated the seamless integration of all-optical logic gates onto compact photonic chips, significantly enhancing performance and scalability. This paper explores the latest breakthroughs in photonic logic gate design, key material innovations, and their transformative applications. While challenges such as fabrication precision and electronic–photonic integration remain, integrated photonic logic gates hold immense promise for revolutionizing optical computing, artificial intelligence, and secure communication. Full article

To address the high false alarm rate of intrusion detection systems based on distributed acoustic sensing (DAS) for power cables in complex underground environments, an innovative GRT-Transformer multimodal deep learning model is proposed. The core of this model lies in its distinctive three-branch parallel collaborative architecture: two branches employ Gramian Angular Summation Field (GASF) and Recursive Pattern (RP) algorithms to convert one-dimensional intrusion waveforms into two-dimensional images, thereby capturing rich spatial patterns and dynamic characteristics and the third branch utilizes a Gated Recurrent Unit (GRU) algorithm to directly focus on the temporal evolution features of the waveform; additionally, a Transformer component is integrated to capture the overall trend and global dependencies of the signals. Ultimately, the terminal employs a Bidirectional Long Short-Term Memory (BiLSTM) network to perform a deep fusion of the multidimensional features extracted from the three branches, enabling a comprehensive understanding of the bidirectional temporal dependencies within the data. Experimental validation demonstrates that the GRT-Transformer achieves an average recognition accuracy of 97.3% across three typical intrusion events—illegal tapping, mechanical operations, and vehicle passage—significantly reducing false alarms, surpassing traditional methods, and exhibiting strong practical potential in complex real-world scenarios. Full article

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with the Kaiser window method, we compare computational efficiency, latency, and energy consumption across the ZYNQ XC7Z020 FPGA, Tesla K80 GPU, and Arm-based CPU, achieving processing times of 0.004 s, 0.008 s, and 0.107 s, respectively, with FPGA power consumption of 1.431 W and comparable energy profiles for GPU and CPU. The FPGA is 27 times faster than the CPU and 2 times faster than the GPU, demonstrating its suitability for low-latency DSP tasks. A detailed analysis of resource utilization and scalability underscores the FPGA’s reconfigurability for optimized DSP implementations. This work provides novel insights into platform-specific optimizations, addressing the demand for energy-efficient solutions in edge computing and IoT applications, with implications for advancing sustainable DSP architectures. Full article

In wireless communications and radio frequency courses, Software-Defined Radios (SDRs) offer students hands-on experience with software-based signal processing on programmable hardware platforms such as Field Programmable Gate Arrays (FPGAs). While some remote SDR laboratories enable students to access real hardware, they typically lack support for Partial Reconfiguration (PR)—a powerful FPGA capability that allows sections of a design to be reconfigured at runtime without disrupting the main system operation. This capability enhances real-time adaptability and optimizes resource utilization, making it highly relevant for modern SDR applications. This study addresses this gap by extending an existing SDR remote lab to support PR, enabling students to explore reconfigurable hardware design within a remote learning environment. Two integration architectures were developed: one based on a graphical user interface (UI) and another utilizing a command-line workflow, both accessible via a web browser. Preliminary experiments using Red Pitaya SDR platforms—reportedly the first use of these devices for educational PR exploration—examined the impact of PR on logic resource utilization and total power consumption across three levels of design complexity. These results were compared to equivalent static FPGA designs performing the same functionality without PR. By making PR experimentation accessible through a remote platform, this work enhances STEM education by bridging advanced FPGA techniques with practical learning. It will equip students with industry-relevant skills for developing agile, resource-efficient wireless systems and foster a deeper understanding of adaptive hardware design. Full article

The diagnosis of open-circuit (OC) faults in power switches is the premise for implementing fault-tolerant control, a critical aspect in ensuring the reliable operation of three-level hybrid active neutral-point-clamped (HANPC) converters in flexible distribution networks. However, existing fault diagnosis methods do not clearly reveal the relationship between the switching-state sequence state and the modulation voltage before and after the fault, which limits their applicability in grid-tied HANPC converters. In this article, a generalized voltage residuals model, taken as the primary diagnostic variable, is proposed for switch OC fault diagnosis in HANPC converters, and the physical meaning is established by introducing the metric of “the variation of the pulse equivalent area”. To distinguish between faulty switches with similar fault characteristics, the neutral current path is reconfigured with a set of rearranged gate sequences. Meanwhile, the auxiliary diagnostic variable, named the current polarity state variable, is developed by means of a sliding window counting algorithm. Additionally, as a case study, a diagnostic criterion for the single-switch fault of HANPC converters is designed by using proposed diagnostic variables. Experimental results are presented to verify the effectiveness of the proposed fault diagnosis method, which achieves accurate faulty switch identification in all tested scenarios within 25 ms. Full article