Optimizing FPGA Resource Allocation in SDR Remote Laboratories via Partial Reconfiguration

Abstract

In wireless communications and radio frequency courses, Software-Defined Radios (SDRs) offer students hands-on experience with software-based signal processing on programmable hardware platforms such as Field Programmable Gate Arrays (FPGAs). While some remote SDR laboratories enable students to access real hardware, they typically lack support for Partial Reconfiguration (PR)—a powerful FPGA capability that allows sections of a design to be reconfigured at runtime without disrupting the main system operation. This capability enhances real-time adaptability and optimizes resource utilization, making it highly relevant for modern SDR applications. This study addresses this gap by extending an existing SDR remote lab to support PR, enabling students to explore reconfigurable hardware design within a remote learning environment. Two integration architectures were developed: one based on a graphical user interface (UI) and another utilizing a command-line workflow, both accessible via a web browser. Preliminary experiments using Red Pitaya SDR platforms—reportedly the first use of these devices for educational PR exploration—examined the impact of PR on logic resource utilization and total power consumption across three levels of design complexity. These results were compared to equivalent static FPGA designs performing the same functionality without PR. By making PR experimentation accessible through a remote platform, this work enhances STEM education by bridging advanced FPGA techniques with practical learning. It will equip students with industry-relevant skills for developing agile, resource-efficient wireless systems and foster a deeper understanding of adaptive hardware design.

1. Introduction

Software-Defined Radios (SDRs) digitize analog signals early in the signal chain, utilizing general-purpose processors or Field Programmable Gate Arrays (FPGAs) to perform digital signal processing (DSP) tasks [1,2]. In contrast, traditional hardware-defined radios (HDRs) rely on fixed-function components—such as modulators, demodulators, and mixers—to implement specific functions in hardware. By converting analog signals to digital and allowing users to reprogram DSP functions in software or HDL, SDRs offer greater flexibility and reconfigurability, making them ideal for a wide range of wireless applications. Figure 1 compares the internal architectures of SDR and HDR receivers; the transmitter architectures follow a mirrored signal flow [3]. Over the past two decades, advancements in radio technology have made SDRs more robust and capable, while simultaneously reducing their cost and size [4].

As a result, an increasing number of educational institutions have integrated telecommunication courses into their curricula to equip students with expertise in areas such as radio frequency (RF), wireless communication, and software-defined radio (SDR) [5]. Many of these courses also require in-person laboratory sections to offer students a comprehensive and hands-on learning experience. This conventional approach has several drawbacks. First, it is not inclusive for students with disabilities, as it requires them to attend in person, which could impact their physical and mental well-being [6]. Second, it increases the risk of equipment damage, such as short circuits or dropped devices [7]. Finally, it places a financial burden on educational institutions due to the need to purchase and maintain numerous lab kits [8]. These kits are often underutilized, as they are not used by all students simultaneously and remain unused outside of lab hours.

These drawbacks have largely been addressed with the introduction of remote laboratories, which allow students to access real hardware devices in dedicated engineering laboratories remotely [9,10,11]. With the rise of the internet, many educational institutions have developed remote labs that allow students to access physical devices from a distance, for courses like chemistry [12] and physics [13,14]. Despite initial doubts, remote laboratories have proven effective, offering significant benefits to both engineering educators and students [15,16]. For example, a study at the University of Washington in an FPGA course found that students using a remote hardware lab demonstrated better analytical skills and higher overall scores compared to those in hands-on labs. The flexibility of remote access also allowed more students to complete their work [17].

To enhance accessibility and broaden the educational impact of SDRs, the RHL-RELIA project was established as a collaborative effort between the Remote Hub Lab (RHLab) and LabsLand. Built on the MELODY model, RHL-RELIA serves as an SDR educational remote laboratory, offering students access to three popular SDR platforms: Red Pitaya STEMlab 125-14 and SDRlab 122-16 from Red Pitaya, Solkan, Slovenia and ADALM-PlUTO (PlutoSDR) from Analog Devices, Wilmington, MA, USA. This setup enables learners to interact with real SDR hardware remotely, anytime, and from anywhere, providing a flexible and equitable learning environment. By integrating SDR technologies into the curriculum, the laboratory not only supports hands-on experimentation but also fosters deeper understanding and engagement in wireless communication and signal processing education.

Many SDRs use the hybrid Zynq-7000 All Programmable SoCs from Xilinx, San Jose, CA, USA, which combine a Processing System (PS) running Linux with Programmable Logic (PL) in the form of an FPGA [18]. The PS, powered by an ARM Cortex A9 processor, interacts with memory and peripherals through the AXI interface, while the PL enables parallel data processing and supports Partial Reconfiguration (PR) [8]. Most educational institutions equipped their laboratories with cost-effective SDRs, under 1000 USD, which often use the Z7010 and Z7020 SoCs. These models offer limited FPGA resources, making them unsuitable for large-scale digital signal processing (DSP) programs. For comparison, the Z7010 provides only about 6% of the logic cells and 4% of the DSP Slices compared to the more advanced Z7100 [19], as shown in Figure 2.

PR offers a powerful solution to enhance the functionality of FPGAs. It is a technique that enables dynamic updates to designated reconfigurable regions of an FPGA while the remainder of the device continues operating uninterrupted [20]. By selectively modifying hardware logic during runtime, PR allows critical functionalities to remain active while auxiliary modules are dynamically swapped based on real-time application demands. This contrasts with traditional FPGA workflows, which require a full reconfiguration to implement functional changes, incurring significant latency and operational downtime. Unlike traditional FPGA reconfiguration, which requires halting the entire system, PR allows specific, predefined regions or slices of the FPGA to be reprogrammed and reconfigured while the rest of the FPGA is uninterrupted. This capability not only optimizes resource utilization but also significantly reduces downtime, enabling rapid prototyping, iterative development, and real-time adaptation.

PR can often lower FPGA power consumption, as PR-enabled designs typically utilize fewer hardware resources, and the unused regions may implement more power-efficient logic [21]. However, the reconfiguration process, shifting configuration bits into the device’s internal memory, incurs an energy overhead, which in some cases may result in higher overall power consumption compared to an equivalent static design without PR.

Figure 3 illustrates a simple PR calculator program that dynamically swaps arithmetic modules on-the-fly. The static region (blue) executes the core program continuously, while the partial reconfigurable region (PRR, green) hosts either an adder or subtractor module, depending on the operational mode. In PR mode, the system seamlessly replaces the adder with the subtractor (or vice versa) without interrupting the static logic—enabling uninterrupted operation, critical for always-on applications. In contrast, traditional FPGA implementations require both modules to reside permanently on the device, inefficiently occupying logic resources even when inactive. Without PR, switching modes necessitates halting the FPGA for full reconfiguration, incurring downtime incompatible with real-time systems.

Dynamic Partial Reconfiguration (DPR) is a specialized form of PR that allows modifying a section of an FPGA while the static region remains operational. Implementing DPR requires careful program design to ensure the main program does not process incorrect data from the PRRs during updates, preventing unintended system behavior. In this paper, all tests and designs were based on DPR. However, for simplicity and consistency with common practice, we will refer to it as PR throughout the paper.

PR offers a powerful solution to enhance the functionality of FPGAs, particularly in resource-constrained, cost-effective SDRs. By dynamically allocating hardware resources more efficiently, PR enables affordable SDRs to handle complex DSP tasks that would otherwise be infeasible. However, based on our research, no SDR remote laboratories currently allow students to explore and apply PR in this context. This paper presents two architectures designed to integrate PR into the existing SDR educational remote laboratory developed under the RHL-RELIA project. These architectures will allow students to remotely explore and experiment with PR on widely used SDR platforms, offering a unique opportunity to test its feasibility and potential applications for their future projects. Additionally, we demonstrate our preliminary tests assessing the viability of performing PR tasks on Red Pitaya SDR platforms, which, to the best of our knowledge, have not previously been utilized for this technology. Our findings highlight the initial successes and challenges of this implementation, providing valuable insights into the potential of PR in an educational context. Finally, we identify key areas that require further investigation to ensure the successful integration of PR capabilities into the remote laboratory, paving the way for its broader adoption and impact.

The paper is structured as follows: Section 2 provides an overview of Partial Reconfiguration (PR) with Zynq SoCs, highlighting its capabilities and existing applications that leverage its potential. Section 3 outlines our approach to implementing PR on established hardware platforms. Section 4 details the progress made thus far in this effort. Section 5 discusses the results, emphasizing how this advanced feature can be integrated into the engineering curriculum and its associated benefits, along with the limitations of the study. Finally, Section 6 concludes the paper and outlines future steps for further development and exploration.

2. Background

2.1. SDR Remote Laboratories

Several educational institutions have developed SDR remote laboratories to enable students to interact with real SDR hardware remotely. Notably, two such labs were created by Huazhong University of Science and Technology and the Technical University of Cluj-Napoca. A comparison of these systems with our RHL-RELIA platform is provided in

Table 1. Comparison of 3 SDR remote laboratories.

SDR Remote Lab	Huazhong University of Science and Technology	Technical University of Cluj-Napoca	RHL-RELIA
Number of SDR Models	2	1	3
Software Tool	MATLAB	GNU Radio	GNU Radio or HDL
Access Method	Web Browser	Virtual Machine	Web Brower
Partial Reconfiguration	No	No	Planned

.

Huazhong University of Science and Technology designed an SDR remote lab using ADALM-PLUTO and USRP-2920 devices. Students access the lab through a web-based interface and program the SDRs by writing MATLAB code in the M language and uploading their files [22,23].

In contrast, the Technical University of Cluj-Napoca developed a remote lab that uses the USRP X310 platform. Students interact with the system via virtual machines connected through a Virtual Private Network (VPN), and use GNU Radio—a widely adopted and user-friendly SDR development environment—for programming [24].

Our system, RHL-RELIA, integrates three SDR models: ADALM-PLUTO, Red Pitaya STEMlab 125-14, and Red Pitaya SDRlab 122-16. They are programmable using GNU Radio 3.8 to 3.10 and are accessible through standard web browsers. Unlike existing labs, RHL-RELIA will support Hardware Description Language (HDL)-based FPGA programming, such as Verilog, and will soon incorporate PR capabilities. This dual focus enables students to explore not only high-level SDR software workflows but also low-level hardware reconfiguration, bridging the gap between software-defined radio and reconfigurable computing.

2.2. Partial Reconfiguration

Some projects [25,26,27,28,29,30] have explored the feasibility of Partial Reconfiguration (PR) and its integration into product design in different fields. Some have incorporated PR into Software-Defined Radios (SDRs) to enhance their capabilities, while others have leveraged PR to improve the functionality of remote laboratories. This section highlights notable PR projects and summarizes their contributions.

2.2.1. Multitasking in Remote Laboratory

In the first project [31], a research team from the University of Brasov developed a remote laboratory for digital hardware design courses. The system consists of a web-based user interface, a web server for scheduling and managing hardware resources, and a network of ZedBoard FPGA development boards. Through PR, the virtual lab enables up to four users to share a single development board simultaneously, enhancing resource efficiency and reducing waiting time. This approach provides students with hands-on experience in digital hardware design and the implementation of mathematical models for renewable energy sources. The study also evaluated the lab’s effectiveness in improving learning outcomes and resource utilization, demonstrating its technical feasibility and educational benefits.

2.2.2. Reconfiguration Time in SDRs

One of the earliest experiments applying PR to SDRs [32] used the USRP E310 SDR. The research team presented their findings in a paper and at a conference, highlighting that integrating PR into their FPGA design significantly sped up the reconfiguration process. Their results showed that PR was more than four times faster than a full reconfiguration, reducing the reconfiguration time from 143 milliseconds to just 33 milliseconds. This improvement enables more dynamic and efficient SDR systems, allowing faster adaptation to changing communication protocols and environmental conditions.

2.2.3. Resource Utilization and Power Consumption in SDRs

In another study [33], the research team evaluated PR in SDRs by implementing five distinct communication technology chains on FPGAs: Wi-Fi, Bluetooth, 2G, 3G, and LTE. They assessed the feasibility of PR in these systems, focusing on resource utilization and power consumption. The findings were promising, showing that PR reduced FPGA area utilization by 10.19% and lowered total power consumption by 76.71% compared to systems without PR. These results highlight the potential of PR to enhance the efficiency of FPGA-based SDRs, making them more power-efficient and cost-effective.

3. Materials and Methods

3.1. Knowledge Gap and Significance of the Research

Despite the growing interest in Partial Reconfiguration (PR) and its integration into Software-Defined Radios (SDRs), there remains a lack of research on applying PR within remote laboratory environments. While previous studies have demonstrated the benefits of PR in terms of reconfiguration speed, resource efficiency, and power consumption, most implementations have been limited to controlled, local settings. No existing SDR remote laboratory provides students with the opportunity to explore and apply PR in a hands-on, interactive manner. This gap highlights the need for a remote educational platform that enables students to experiment with PR on SDRs in a remote setting, fostering deeper understanding and practical experience.

Addressing this gap is significant for both academia and industry. Enabling PR experimentation in remote laboratories can enhance students’ learning outcomes by providing real-world exposure to FPGA-based SDRs and dynamic hardware reconfiguration. Additionally, such a platform would support broader accessibility to PR technology, allowing students from diverse backgrounds to engage with advanced hardware concepts without requiring physical access to FPGA development boards. From an industry perspective, this research can contribute to the development of more adaptable and efficient SDR systems, ultimately benefiting fields such as telecommunications, defense, and wireless communication.

By bridging this knowledge gap, the research not only advances FPGA-based SDR remote laboratories but also aligns with the increasing demand for flexible, software-defined solutions in modern communication systems. The insights gained from this study can pave the way for future innovations in digital hardware education and practical FPGA implementations.

3.2. Design Flow

All PR tests presented in this paper were conducted using the Vivado Design Suite, the official development environment for Zynq FPGAs. Vivado supports programming the Zynq-7000 Series System-on-Chip (SoC), which is commonly used in cost-effective SDRs such as the ADALM-PLUTO (Zynq-7010) and Red Pitaya (Zynq-7010/7020). The standard design process for developing an FPGA program without PR can be summarized as follows [34]:

• Designing the FPGA Program—The program is developed either by writing scripts in a Hardware Description Language (HDL) or by utilizing Intellectual Property (IP) blocks, which are interconnected within a block design. Running the program on a physical FPGA requires both source files, which define the logic and circuitry, and constraint files, which specify pin assignments and other essential details needed for synthesis and implementation.
• Synthesis—The project is synthesized to detect syntax errors and generate a “netlist,” which describes the necessary circuit components and their connections.
• Implementation—The synthesized design is mapped onto the selected FPGA device according to the specified constraints.
• Bitstream Generation—The implemented design is converted into a .bit file, which serves as the final FPGA configuration file.
• Programming—The generated bitstream is loaded onto the FPGA, configuring the device to execute the intended design.

The development process for a partial reconfigurable FPGA program in Vivado Design Suite follows a similar workflow but incorporates additional steps during design, synthesis, and programming to accommodate dynamic reconfiguration, as illustrated in Figure 4 [35].

Before sending the circuit design to the synthesizer, users must enable “Dynamic Function eXchange” from the Tools menu. Next, they can create a partition by right-clicking on any HDL source file and selecting “Create Partition Definition.” After naming the partition, users can access the “Dynamic Function eXchange Wizard” to associate multiple source files with the partition, designating them for the partial reconfigurable region (PRR) during synthesis. The design can then be synthesized.

Once synthesis is complete, users must create a Pblock for each partition using the Floorplanning feature [36], selecting regions on the FPGA for the PR modules. A well-optimized floorplan can reduce hardware resource utilization and power consumption, though it typically requires multiple iterations to achieve the most efficient design. The floorplan must pass a Design Rule Check (DRC) to ensure compliance with Dynamic Function eXchange (DFX) rules. Afterward, the project can be compiled into bitstreams.

After generating the bitstreams, users will find full and partial .bit files in the runs folders or subfolders. These files can be used to program the FPGA; however, attempting to program the FPGA with partial bitstreams before using a full bitstream via Vivado’s Hardware Manager will result in an error.

3.3. Feasibility Assessment of Partial Reconfiguration on Zynq-Based Development Board

To validate the practicality of PR for SDR applications, preliminary experiments were conducted using the Blackboard development platform, developed by Real Digital, Pullman, WA, USA [37]. It is equipped with a Zynq Z-7007S System-on-Chip (SoC) from the Xilinx 7000 series. This device integrates programmable logic with an ARM Cortex-A9 processor, alongside peripherals including LEDs, switches, pushbuttons, XADC, HDMI, and PMOD interfaces. While the Z-7007S offers fewer logic resources than the Z-7010 SoC common in commercial SDRs, its architectural similarity and cost efficiency ($149 for academic users at the time of writing) made it ideal for prototyping PR workflows [19]. This strategic hardware selection balanced scalability constraints in educational SDR deployments while mitigating financial risks during early-stage PR validation.

A modular 8-bit arithmetic unit was developed using the Vivado Design Suite 2023.2 to evaluate PR workflows, supporting four operations: addition, subtraction, multiplication, and division. Operands were set via onboard switches, with results displayed on 7-segment LEDs. Two implementations were compared:

• Dynamic PR Configuration: A single reconfigurable partition (RP) housing one arithmetic module at a time, swapped via Vivado’s Hardware Manager.
• Static Configuration: All four modules implemented concurrently, with operation selection via switch inputs.

Defining the partial reconfigurable region (PRR) required balancing resource efficiency against design flexibility. Initial floorplanning allocated a minimal PRR sized to the largest arithmetic module (multiplier), illustrated in Figure 5. However, Design Rule Checks (DRCs) flagged routing congestion and insufficient buffer resources, as captured in Figure 6, despite Vivado’s block properties window, shown in Figure 7, suggesting feasibility. Figure 8 depicts the final Pblock, which resolves DRC violations while retaining a minimal footprint, balancing resource efficiency and reconfiguration flexibility. This highlights the non-intuitive relationship between logical resource requirements and physical FPGA layout in PR designs, where tool-reported metrics often misalign with practical implementation constraints.

To quantify the benefits of PR, a baseline static implementation of the 8-bit calculator was developed, integrating all four arithmetic modules (adder, subtractor, multiplier, and divider) into a fixed FPGA configuration. Operation selection in this static design was governed by onboard switches, bypassing the dynamic module-swapping enabled by Vivado’s Hardware Manager in the PR variant. Following bitstream generation for both implementations, post-place-and-route analyses compared hardware resource utilization (LUTs, FFs, BRAM, DSP slices) and total power consumption.

As detailed in Figure 9, PR reduced LUT usage by 16.9% (49 vs. 59 LUTs) and total power consumption by 44.3% (10.289 W vs. 18.661 W) at maximum clock speed, despite matching functional performance. Both designs used identical flip-flop (FF) counts (5 FFs), while BRAM and DSP slices remained unused due to the arithmetic modules’ simplicity. These results underscore PR’s ability to conserve reconfigurable resources without sacrificing functionality—a critical advantage for SDR systems requiring dynamic, multi-standard operation in resource-constrained educational environments.

To evaluate PR’s efficacy in signal processing workflows, a second case study implemented a configurable filter chain processing potentiometer data via the Blackboard’s XADC. Two variants were developed:

• PR-Enabled Design: A single partial reconfigurable region (PRR) housed either a low-pass or high-pass FIR filter, dynamically swapped via PR.
• Static Design: Both filters implemented concurrently, with mode switching controlled by register writes to emulate SDR-style software reconfiguration.

As summarized in Figure 10, the PR implementation reduced LUT and FF utilization by 4.1% (212 vs. 221 LUTs) and 6.9% (148 vs. 159 FFs), respectively, while lowering total power by 12.3% (8.2 W vs. 9.3 W). The smaller savings compared to the calculator case study stem from two factors:

• Reduced PR Module Count: Only two filter modules (vs. four arithmetic units) limited resource-sharing opportunities.
• Homogeneous Resource Demands: Both filters required similar LUT/FF counts, diminishing PR’s advantage over static multiplexing.

Notably, BRAM and DSP usage remained unchanged, as neither design employed these resources. This aligns with prior observations: PR delivers maximal resource savings when (1) reconfigurable modules exhibit heterogeneous hardware demands, and (2) multiple underutilized modules share a single PRR. Encouraged by these results, we proceeded to the selection of an SDR platform for PR-driven programming.

3.4. Selecting an SDR

Selecting an SDR platform capable of supporting PR is pivotal to avoid inefficient resource allocation and ensure pedagogical scalability. Our research group, RHL-RELIA—a collaboration between the Remote Hub Lab (RHL) [38] and LabsLand [39]—operates a remote SDR laboratory initially deployed with Analog Devices’ ADALM-PLUTO (PlutoSDR) [40]. While cost-effective and equipped with a Zynq-7010 SoC, early PR implementation efforts exposed critical limitations in the PlutoSDR’s design: the absence of Ethernet connectivity necessitated physical disassembly for Vivado programming, and its closed-case architecture hindered firmware recovery workflows. These constraints contravened the MELODY framework’s usability metrics [41], which prioritize accessibility and adaptability in remote labs.

To address these challenges, we established four criteria for an optimal PR-compatible SDR platform:

• Zynq-7000 SoC Compatibility: Zynq-7010/7020 devices to align with academic SDR affordability while ensuring sufficient logic resources.
• Cost and Accessibility: Sub-$750 pricing with broad adoption for technical support scalability.
• Open-Source Ecosystem: Community-driven documentation and firmware to enable customization.
• Remote-Ready Connectivity: Ethernet for configuration and microSD for firmware recovery.

Commercial SDRs like the USRP N210 [42] were excluded due to prohibitive costs (>$2000) and proprietary constraints. The Red Pitaya platform emerged as the sole candidate meeting all criteria [43]. We evaluated two models:

• STEMlab 125-14 [44]: Lower-cost ($349), Zynq-7010-based, with 14-bit ADC/DAC at 125 MSPS.
• SDRlab 122-16 [45]: Enhanced 16-bit resolution at 122 MSPS but limited documentation.

Initial trials used the SDRlab 122-16 for its superior analog frontend, but sparse community resources prompted a shift to the STEMlab 125-14 for reproducibility. A comparison of the two Red Pitayas is shown in

Table 2. Red Pitaya STEMlab 125-14 and SDRlab 122-16 specification.

	STEMlab 125-14	SDRlab 122-16
SoC	Z-7010	Z-7020
Connectivity	USB 2.0, 1 Gb Ethernet
Number of RF Input Channels	2
Number of RF Output Channels	2
RF Input Bandwidth	DC—60 MHz	300 kHz–550 MHz
RF Output Bandwidth	DC—60 MHz	300 kHz–60 MHz
Input Sampling Rate (MS/s)	125	122.88
Output Sampling Rate (MS/s)	125	122.88
Input Resolution (bit)	14	16
Output Resolution (bit)	14

. This transition highlights the trade-off between cutting-edge hardware and pedagogical practicality in remote lab design—a recurring theme in PR-enabled SDR deployments.

3.5. Integration of the Red Pitaya SDR into the RHL-RELIA SDR Remote Laboratory Framework

Before evaluating PR on the Red Pitaya platform, we integrated it into the RHL-RELIA remote laboratory infrastructure, a modular framework designed to unify heterogeneous hardware and software tools across distributed environments [46,47]. As depicted in Figure 11, the architecture comprises three core layers:

• Centralized Server: Hosts a web-based remote laboratory interface for user interaction, a scheduler for fair hardware access, and a data exchanger that processes configuration files (e.g., bitstreams, filter coefficients) and streams processed signals back to users.
• Edge Devices: Raspberry Pi units deployed as reconfigurable intermediaries, tasked with programming SDRs and retrieving I/O data via low-latency GPIO interfaces.
• Physical Layer: SDR platforms (e.g., Red Pitaya, ADALM-PLUTO) housed in Faraday cages to minimize RF interference, colocated at the University of Washington’s RHL facility.

This layered design decouples control, computation, and physical hardware, enabling scalable integration of new devices like the Red Pitaya without disrupting legacy workflows. By standardizing communication protocols between layers, the framework ensures interoperability across vendor-specific SDR toolchains—a critical requirement for deploying PR-enabled adaptive radios in multi-user educational contexts.

3.5.1. Enclosure Design for Multi-SDR RF Isolation

Transitioning from ADALM-PLUTOs to Red Pitayas necessitated redesigning the RF-shielded enclosure to address cross-platform interoperability and scalability. The original enclosure, designed for dual ADALM-PLUTOs (one transmitter, one receiver), featured full Faraday fabric shielding with a semi-transparent conductive mesh top for visual monitoring, as shown in Figure 12. This approach was adapted for the Red Pitaya platform, with each unit housed in a dedicated compartment to prevent crosstalk. The left Red Pitaya operates as a receiver (RX), while the right unit functions as a transmitter (TX)—roles visually distinguishable via their antenna placement.

For large-scale deployment, the system was integrated into a LabsLand Prism4 chassis, as depicted in Figure 13, a modular enclosure supporting the following:

• 4 Raspberry Pi units for device control;
• 4 SDRs across 2 partitioned Faraday cages;
• Centralized power management;
• Ceiling-mounted cameras with a view through the cages’ semi-transparent mesh tops.

3.5.2. PR Architecture Design for Zynq-Based SDRs

To support diverse pedagogical and technical requirements in remote SDR laboratories, we developed two complementary Partial Reconfiguration (PR) architectures tailored for Zynq-7000-based platforms: a user interface (UI)-driven workflow and a command-line interface (CLI)-centric approach. The UI-driven architecture, depicted in Figure 14, prioritizes accessibility by emulating the Vivado Design Suite experience through a web-based portal. Users upload full or partial bitstreams to dynamically reconfigure SDR pairs (transmitter/receiver) during reserved time slots. This framework relies on an x86 host computer to execute Vivado for FPGA programming via a cost-effective JTAG-HS3 programmer, with Raspberry Pis to capture SDR I/O data and relay signals to the web interface. Ethernet–SSH links enable IP-based communication between Raspberry Pis and Red Pitayas. While intuitive for learners accustomed to Vivado, this architecture incurs higher setup costs due to its dependence on x86 hardware and dedicated JTAG programmers.

In contrast, the CLI-based architecture [48], depicted in Figure 15, streamlines hardware requirements by eliminating Vivado’s GUI dependencies. Users upload pre-synthesized bitstreams to a server, which routes them to Raspberry Pis. A terminal emulator then allows direct FPGA programming via Linux commands, setting a PR flag,

echo 1 > /sys/class/fpga_manager/fpga0/flags

followed by loading the partial bitstream,

cat partial_bitstream.bit > /dev/xdevcfg

Here, Raspberry Pis serve as both programmers and data receivers, bypassing the need for x86 hosts and JTAG hardware—reducing per-station costs by approximately $400. However, this efficiency comes with trade-offs: the CLI approach requires predefined bitstreams, demanding familiarity with low-level FPGA management and Linux command skills.

Both architectures address distinct educational scenarios. The UI-driven model suits introductory courses where visual feedback and Vivado familiarity enhance learning curves, while the CLI approach benefits advanced students exploring resource-constrained or large-scale deployments. By decoupling programming interfaces from core PR workflows, this dual-strategy framework ensures adaptability across institutions with varying budgets and technical infrastructures, a critical consideration for democratizing reconfigurable computing education.

3.6. Feasibility Assessment of Partial Reconfiguration on SDRs

Building on the architectural framework, we established proficiency in Red Pitaya’s FPGA ecosystem by completing vendor-provided tutorials [49], which elucidate interactions between the Zynq SoC and peripherals (e.g., 14-bit ADCs, GPIO-driven LEDs). This foundational expertise enabled the development of PR modules for SDR workflows. Initial trials employed the high-performance SDRlab 122-16, equipped with a Zynq-7020 SoC and 16-bit ADCs (122 MSPS), to explore wideband PR applications. However, sparse documentation and limited community resources hindered the implementation of advanced DSP pipelines, particularly for real-time adaptive filtering.

To prioritize reproducibility and pedagogical scalability, subsequent evaluations shifted to the STEMlab 125-14—a lower-cost ($349), Zynq-7010-based platform with robust open-source support. Despite its reduced specs (14-bit ADCs, 125 MSPS), the STEMlab’s active user community and modular PR toolchain accelerated iterative testing. Three representative PR case studies were conducted on this platform using Vivado 2019.1, demonstrating its efficacy in balancing educational accessibility with reconfigurable computing principles.

3.6.1. Case Study 1: GPIO-Driven Calculator with Partial Reconfiguration

This first case study adapted the GPIO-driven calculator from assessing PR on the Blackboard to validate PR workflows on Red Pitaya. As shown in Figure 16, the design processes two 8-bit operands via GPIO, displaying results on LEDs. A memory module reduced GPIO pin usage by 56% (10 vs. 16 pins), reserving resources for future SDR functionalities. The partial reconfigurable region (PRR), highlighted in pink, dynamically hosted arithmetic modules (adder, subtractor, multiplier, divider), which could be swapped during runtime. Lightly shaded modules in the block diagram represent non-essential infrastructure, such as clock managers or unused I/O buffers, included for completeness but not impacting core functionality.

Initial tests on the SDRlab 122-16 (Zynq-7020) succeeded with the UI architecture but failed under CLI workflows: partial bitstreams froze the FPGA. This issue persisted across multiple firmware versions, including custom GNU Radio builds, disproving initial hypotheses of outdated firmware. Consequently, testing migrated to the STEMlab 125-14 (Zynq-7010), a more cost-effective model with robust community-driven documentation. Transitioning to this platform resolved CLI instability, enabling reliable PR across both architectures while reducing static power consumption by 18% during reconfiguration.

3.6.2. Case Study 2: 1-PRR Scaling Program with Partial Reconfiguration

The second case study advances the exploration of PR by transitioning from basic arithmetic operations to a simple signal processing application directly aligned with core SDR functionalities. This program retains a single PRR but shifts focus to dynamic amplitude scaling modules—critical for managing signal integrity in wireless systems. The PRR hosts two reconfigurable scaling behaviors: an uncapped mode, which applies user-defined gain without constraints, risking overflow-induced clipping (where signals exceeding the system’s maximum amplitude threshold are truncated to zero), and a peak-capped mode, which clamps amplitudes to predefined limits (e.g., ±3.3 V), preserving waveform fidelity during high-gain operations. This duality allows students to experimentally observe trade-offs between signal distortion and computational overhead.

As detailed in Figure 17, the design interfaces directly with the Red Pitaya’s analog frontend. The analog module converts unsigned ADC data into two’s complement formats for signed arithmetic processing in the PRR and reverses the conversion for the DAC output, ensuring compatibility with Red Pitaya’s mixed-signal architecture. The arbitrary signal generator (ASG) initializes the system by preloading test waveforms (e.g., chirp signals) into the DAC buffer, enabling standalone operation without external input—a feature particularly valuable for remote lab environments. Lightly shaded modules in the block diagram represent non-critical infrastructure, such as clock distribution networks or unused I/O buffers, included to satisfy toolchain requirements but omitted from detailed analysis to streamline the pedagogical focus.

3.6.3. Case Study 3: 2-PRR Scaling and Filtering Program with Partial Reconfiguration

The third case study extends the PR assessment by implementing a dual-PRR architecture, enabling simultaneous dynamic scaling and adaptive filtering—an advancement for multi-functional SDR systems. As illustrated in Figure 18, the design integrates two independent PRRs: the first replicates the scalable amplitude module (with/without peak capping) from Section 3.6.2, while the second introduces a reconfigurable 5-tap FIR filter, programmable as a low-pass or high-pass variant with a fixed cutoff frequency. This dual-PRR framework allows students to explore cascaded signal processing workflows, such as amplifying a signal while applying real-time spectral shaping, mirroring real-world SDR tasks like interference suppression or channel equalization.

Figure 19 showcases the floorplanning outcome, with both PRRs constrained to magenta-bounded regions near the FPGA’s periphery to minimize routing delays and isolate reconfigurable logic from static subsystems. While dual-PRR designs can enhance flexibility—enabling resource-efficient, task-specific optimization of scaling and filtering modules—they introduce significant complexity, including PRR synchronization, floorplanning optimization, and debugging overhead.

4. Results

Building on the successful implementation of the three Red Pitaya Partial Reconfigurable case studies in Section 3, this section analyzes hardware resource utilization and power consumption metrics, benchmarking Partial Reconfiguration (PR) against static FPGA configurations.

4.1. Case Study 1: GPIO-Driven Calculator with Partial Reconfiguration Result

The 8-bit calculator program demonstrated efficiency gains when using PR. As Figure 20 illustrates, compared to the static implementation, the PR-enabled design reduced LUT usage by 6.9% and flip-flop (FF) utilization by 13.6%, reflecting PR’s ability to optimize sequential logic in arithmetic modules. However, total power consumption saw only a marginal decrease of 0.2%, suggesting minimal dynamic power savings for low-complexity PR swaps. BRAM and DSP usage remained identical (30.0 BRAM blocks, 24 DSP slices), as these fixed-function resources were unaffected by the arithmetic logic’s reconfiguration. These results underscore PR’s potential to streamline programmable logic in resource-constrained SDRs, though its benefits scale with design complexity—a trend explored further in subsequent case studies.

4.2. Case Study 2: 1-PRR Scaling Program with Partial Reconfiguration Result

Figure 21 displays the resulting waveforms of the scaling program. In part (a), the original transmitted signal (purple) from one of the Red Pitaya’s output channels is shown alongside the digitally processed received signal (yellow). When the scaling factor is increased to induce overflow, part (b) illustrates the effect of the PR module without saturation thresholds: the sine wave’s peaks are clipped to the x-axis. Conversely, part (c) demonstrates the behavior of the PR module with thresholds, where overflowed signals are capped at predefined positive and negative limits. A temporal discrepancy between input and output signals is visible in parts (b) and (c). While the exact cause of this delay remains uncertain, it is hypothesized to originate from network latency (due to the Red Pitaya’s router connection) or internal timing shifts within the device’s oscillators.

Figure 22 compares hardware resource utilization and power consumption between the PR-enabled and static implementations of the program. The PR-enabled design achieves modest reductions in LUT (3.8%) and flip-flop (FF, 1.4%) usage, which may reflect suboptimal floorplanning of the PRR. These minor gains suggest opportunities for further optimization through refined PRR sizing or expanded PR module diversity, as prior studies indicate resource savings scale with the number of interchangeable modules sharing a PRR. Notably, DSP slice utilization decreases by 14.3% (14 to 12 slices), while total power consumption drops by 2.7%. BRAM usage remains unchanged (30.0 blocks), consistent with its role in static memory allocation. The results underscore PR’s potential to streamline compute-intensive resources (e.g., DSPs) in SDR workflows, though maximizing programmable logic efficiency requires deeper floorplanning expertise—a key area for future skill development in reconfigurable computing education.

4.3. Case Study 3: 2-PRR Scaling and Filtering Program with Partial Reconfiguration Result

Prior to integrating both PRRs into a unified program, the standalone filter module was validated on the Red Pitaya. As shown in Figure 23, programming the PRR with a low-pass filter (600 kHz cutoff) preserved the 500 kHz signal while attenuating the 700 kHz input. Conversely, the high-pass filter suppressed the 500 kHz signal but retained the 700 kHz component.

While each PRR functioned independently, combining them introduced instability. For example, Figure 24 reveals anomalies in a 300 kHz signal scaled by 1.78× and filtered (low-pass, 600 kHz), where negative phases erroneously flipped to positive. Glitches intensified for high-frequency inputs, as seen in Figure 25: a 3 MHz signal processed by a high-pass filter (600 kHz cutoff) and scaled by 2.4× exhibited erratic amplitude modulation.

As Figure 26 depicts, post-synthesis timing constraint warnings suggest these issues may stem from suboptimal timing domain synchronization—a challenge requiring advanced FPGA design expertise that we aim to develop in future work. In PR designs, achieving timing closure is especially critical, as the static and dynamic regions must interface correctly at all times. Failure to do so can lead to issues such as data corruption—as observed in our case—metastability, or even complete system crashes. To mitigate these problems, we plan to first address total negative slack (TNS), incorporate pipelining to break long combinational paths, and consider reducing the size of PRRs to ease routing congestion. Additionally, we will investigate whether alternative floorplanning strategies can help further reduce or eliminate timing violations.

Figure 27 quantifies resource savings from PR: LUTs decreased by 4.0% (4843 to 4649), FFs by 2.0% (5313 to 5207), and DSP slices by 14.3% (14 to 12). BRAM usage and total power remained unchanged. While these gains are modest, optimized floorplanning—strategically sizing and placing PRRs—could amplify resource efficiency, particularly in multi-PRR designs. This underscores the need for deeper exploration of PRR optimization techniques to maximize hardware savings in complex SDR applications.

5. Discussion

The integration of Partial Reconfiguration (PR) into an educational Software-Defined Radio (SDR) remote lab bridges a critical gap in reconfigurable hardware computing pedagogy, enabling students to explore dynamic hardware adaptation—a capability absent in existing remote labs that focus solely on static FPGA configurations. Our results demonstrate that PR can achieve measurable hardware resource reduction and greater power efficiency, as summarized in

Table 3. LUT, FF, DSP, and total power saving for all 3 case studies using Red Pitaya SDR.

Program	8-Bit Calculator	1-PRR Scaling	2-PRR Scaling and Filtering
LUT	6.9%	3.8%	4%
FF	13.6%	1.4%	2%
DSP	Not Applicable	14.3%	14.3%
Total Power	0.2%	2.7%	0%

, while introducing complexities such as timing violations and floorplanning challenges. These findings align with prior studies emphasizing PR’s trade-offs: while it enhances flexibility, its efficiency gains depend heavily on design modularity and floorplanning optimization.

5.1. Interpretation in Context of SDR Education

Our remote lab’s PR-enabled framework advances the MELODY model [41] by transforming theoretical concepts like hardware agility and resource-aware design into experiential learning. While PR has recently become a cornerstone of mission-critical systems—such as satellites requiring in-orbit hardware updates and autonomous vehicles adapting to real-time sensor fusion—it remains absent from most Electrical and Computer Engineering (ECE) curricula. By integrating PR into a remote SDR lab, we demystify this advanced capability, enabling students to experimentally validate concepts like dynamic hardware reuse and adaptive signal processing. By training students in these methodologies, the lab bridges academia and industry, preparing learners for emerging wireless ecosystems that demand hardware-level adaptability.

5.2. Broader Implications for Industry and Research

The SDR remote lab’s scalability further democratizes access to PR experimentation, which has historically been restricted to well-funded institutions due to the cost of reconfigurable hardware and proprietary toolchains. By leveraging open-source platforms like Red Pitaya and cost-effective CLI workflows, we reduce barriers to entry, making PR education feasible for institutions with limited budgets. This is particularly impactful given the growing demand for engineers skilled in adaptive hardware design, driven by emerging applications in 6G, AI-driven radios, and edge computing.

5.3. Limitations

This work has several limitations. First, our evaluation was preliminary, focusing on the feasibility of implementing PR within an SDR and integrating it into an existing remote lab. Fully characterizing PR’s potential will require deeper investigation of metrics such as reconfiguration time, energy overhead, and resource-and-power efficiency across varying workloads and application scenarios. Second, all PR-enabled SDR programs were derived from the manufacturer’s basic Red Pitaya FPGA template. To unlock the full benefits of PR, future work should develop custom FPGA designs from the ground up. Third, our experiments were conducted exclusively on Red Pitaya platforms because of their affordability and connectivity. To draw more general conclusions about PR in SDRs, additional testing on diverse hardware—featuring different processors, FPGA families, and toolchains—is essential.

6. Conclusions

This work introduces a novel extension to an existing Software-Defined Radio (SDR) remote laboratory, enabling students to run Partial Reconfiguration (PR) programs on real SDR platforms within our remote lab infrastructure. PR is an advanced FPGA technology that enhances FPGA capabilities by optimizing hardware resource allocation and enabling increased real-time reconfigurability. Unlike existing remote labs that utilize PR primarily for multitasking to improve system resource sharing, our SDR remote lab is designed to provide students with direct, hands-on experience in exploring and implementing PR on widely used SDR platforms, such as the Red Pitayas. This approach fosters a deeper understanding of PR concepts and their practical applications in advanced hardware design.

Preliminary PR tests conducted on Red Pitaya platforms—which, to the best of our knowledge, have not been previously used for this application—demonstrated promising results. These tests highlight PR’s potential to improve the performance of cost-effective SDRs equipped with lower-end FPGAs, offering an exciting feature for student exploration. By addressing the gap in accessible tools for teaching reconfigurable FPGA design, our remote lab provides a unique educational resource that empowers students to engage with cutting-edge FPGA programming techniques remotely and advances STEM pedagogy by integrating innovative technologies into engineering education.

Future work will prioritize three key directions to advance partial reconfigurable SDR education. First, we aim to extend platform compatibility by integrating SDRs with heterogeneous FPGA architectures, validating the framework’s adaptability across vendor-specific toolchains. Second, rigorous benchmarking of PR will quantify its real-world trade-offs, including execution time, reconfiguration latency, and dynamic power overhead compared to static implementations under various workloads and applications. These will help both instructors and students gain a better understanding of how much hardware resources and power efficiency gains PR can provide. Finally, we will develop pedagogical tools—such as web-based PR module builders and pre-verified IP libraries—to lower the barrier to entry for students. These efforts will deepen hands-on learning in adaptive hardware design, empowering learners to prototype latency-sensitive SDR applications while mastering industry-relevant PR workflows. Once the system has been thoroughly tested, we will collaborate with instructors in the Department of Electrical and Computer Engineering (ECE) to deploy it in real classroom settings. Student feedback will be collected to evaluate the system’s educational impact and guide further improvements.