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Electronics
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FPGA-Based Reconfigurable Embedded Systems
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FPGA-Based Reconfigurable Embedded Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (15 April 2025) | Viewed by 7257

Special Issue Editors

Dr. Zonghui Li

E-Mail Website
Guest Editor
School of Computer and Information Technology, Beijing Jiaotong University, Beijing 100044, China
Interests: time-sensitive networking; hardware and software co-design; VLSI design
Dr. Yangdong Deng

E-Mail Website
Guest Editor
School of Software, Tsinghua University, Beijing 100084, China.
Interests: computer architecture; industry data analytics
Dr. Tao Li

E-Mail
Guest Editor
School of Computer, National University of Defense Technology, Changsha 410000, China
Interests: computer network architecture; deterministic network design; high-performance network hardware

Special Issue Information

Dear Colleagues,

Embedded systems are widely used across the entire world today, covering areas such as industrial controls, automotive electronics, medical electronics, consumer electronics, telecom/datacom, military/aerospace, etc. Reconfigurability is pushing embedded systems towards being more flexible, self-adaptive, and efficient. The customizable and programmable nature of FPGAs makes them an excellent alternative to ASICs as efficient hardware platforms for reconfigurable embedded systems. FPGAs provide opportunities for designers to quickly implement and evaluate different functions by reconfiguring the integrated computing logic and memory resources in the embedded systems.

However, FPGA-based reconfigurable embedded systems are very challenging because such systems, and especially the FPGAs, are typically constrained by limited computing, memory resources, bandwidth, power, and extreme environments. To tackle these problems, we need to refocus on the architecture, programming, implementation complexity, hardware and software co-design, etc., to determine the most efficient way to implement FPGA-based reconfigurable embedded systems. This Special Issue invites the submission of original contributions from both academic and industrial areas that focus on all topics related to FPGA-based reconfigurable embedded systems.

Topics

Topics of interests for this Special Issue include, but are not limited to, the following:

  • Novel reconfigurable architectures, including overlay architectures for embedded systems with FPGAs.
  • Resource-efficient/low-power/domain-specific design optimization for FPGA-based embedded systems.
  • Co-design of hardware and software for FPGA-accelerated embedded systems.
  • Abstractions, programming models, interfaces, and runtime management, including virtualization, for FPGA-based embedded systems.
  • New languages and design frameworks for spatial or heterogeneous applications for FPGAs.
  • System resilience/fault tolerance for embedded systems with FPGAs.
  • Self-adaptive/AI embedded systems with FPGAs.
  • Scheduling, management, and reconfiguration for real-time and/or networked embedded systems with FPGAs.
  • Emerging technologies with in-field reconfiguration abilities for embedded systems.
  • Industrial experience or case studies of FPGA-based reconfigurable embedded systems.

Dr. Zonghui Li
Dr. Yangdong Deng
Dr. Tao Li
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • embedded systems
  • FPGAs
  • reconfigurable architecture
  • hardware and software co-design
  • FPGA-accelerated embedded systems
  • real-time/networked embedded systems
  • AI/self-adaptive embedded systems

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Published Papers (5 papers)

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Research

21 pages, 2394 KiB  
Article
AFHRE: An Accurate and Fast Hardware Resources Estimation Method for Convolutional Accelerator with Systolic Array Structure on FPGA
by Yongchang Wang, Hongzhi Zhao and Jinyao Zhao
Electronics 2025, 14(1), 168; https://doi.org/10.3390/electronics14010168 - 3 Jan 2025
Viewed by 733
Abstract
FPGA-based convolutional accelerators have been widely used in image recognition scenarios. Many convolutional accelerators utilize the systolic array structure to enhance parallelism. Developing a method to efficiently estimate the utilized hardware resources of an FPGA for such a structure would be helpful in [...] Read more.
FPGA-based convolutional accelerators have been widely used in image recognition scenarios. Many convolutional accelerators utilize the systolic array structure to enhance parallelism. Developing a method to efficiently estimate the utilized hardware resources of an FPGA for such a structure would be helpful in improving the speed of achieving an optimal systolic array structure with the best performance on a given FPGA device. Currently, most estimations of work have either focused on the evaluation of hardware resources for general structures or have not adequately assessed hardware resources specifically for systolic arrays. To reduce estimation latency, this paper proposes an Accurate and Fast Hardware Resources Estimation method (AFHRE) that addresses these shortcomings by analyzing the structure of systolic arrays and utilizing mathematical formulas to describe their characteristics. Experiments show that the DSP resource occupancy estimated by AFHRE is fully consistent with that by Vivado HLS. The error rates of other three types of hardware resources (BRAM, LUT, and FF) are within 11%. In addition, the speed of resource estimation using this method is 40X to 610X faster than that of Vivado HLS. AFHRE can serve as a preprocessing step for Vivado HLS, achieving some optimal or sub-optimal solutions systolic array parameters much faster than original simulation manners of Vivado HLS. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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11 pages, 1078 KiB  
Article
Field-Programmable Gate Array-Based True Random Number Generator Using Capacitive Oscillators
by Zbigniew Hajduk
Electronics 2024, 13(23), 4819; https://doi.org/10.3390/electronics13234819 - 6 Dec 2024
Viewed by 1046
Abstract
In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A [...] Read more.
In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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23 pages, 1645 KiB  
Article
A Proof-of-Concept FPGA-Based Clock Signal Phase Alignment System
by Andrzej A. Wojciechowski
Electronics 2024, 13(16), 3295; https://doi.org/10.3390/electronics13163295 - 20 Aug 2024
Viewed by 2122
Abstract
Phase alignment of periodic events between multiple systems is required in multiple fields and applications. Most of the existing solutions focus on either low frequency and relatively low accuracy or high complexity, high accuracy and precision. In contrast, this work aimed to develop [...] Read more.
Phase alignment of periodic events between multiple systems is required in multiple fields and applications. Most of the existing solutions focus on either low frequency and relatively low accuracy or high complexity, high accuracy and precision. In contrast, this work aimed to develop an intermediate solution, supporting high frequencies and relatively high accuracy and precision, with relatively low complexity. A hypothetical concept and mathematical model is presented with a hardware test implementation based entirely on FPGA resources. Deliberate resource selection and utilization enables a significant simplification of calculations and, as a result, a reduction in logic resource utilization. The proposed concept was implemented and verified using the AMD/Xilinx Artix 7 35T FPGA platform. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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22 pages, 748 KiB  
Article
CuFP: An HLS Library for Customized Floating-Point Operators
by Fahimeh Hajizadeh, Tarek Ould-Bachir and Jean Pierre David
Electronics 2024, 13(14), 2838; https://doi.org/10.3390/electronics13142838 - 18 Jul 2024
Cited by 1 | Viewed by 1432
Abstract
High-Level Synthesis (HLS) tools have revolutionized FPGA application development by providing a more efficient and streamlined approach, significantly impacting digital design methodologies. Despite the capability of FPGAs to customize numerical representations in data paths, most HLS projects have focused on fixed-point precision, while [...] Read more.
High-Level Synthesis (HLS) tools have revolutionized FPGA application development by providing a more efficient and streamlined approach, significantly impacting digital design methodologies. Despite the capability of FPGAs to customize numerical representations in data paths, most HLS projects have focused on fixed-point precision, while floating-point representations remain limited to vendor-provided single, double, and half-precision formats. This paper proposes a customized floating-point library compatible with HLS to address these limitations. This library allows programmers to define the number of exponent and mantissa bits at compile time, providing greater flexibility and enabling the use of mixed precision. Moreover, this library includes optimized implementations of common components such as vector summation (VSUM), dot-product (DP), and matrix-vector multiplication (MVM). Results demonstrate that the proposed library reduces latency and resource utilization compared to vendor IP blocks, particularly in VSUM, DP, and MVM operations. For example, the mvm operation involving a 32 × 32 matrix, using vendor IP requires 22 clock cycles, whereas CuFP completes the same task in just 7 clock cycles, using approximately 60% fewer DSPs, 10% fewer LUTs, and 60% fewer FFs. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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23 pages, 5565 KiB  
Article
Analysis and Construction of Hardware Accelerators for Calculating the Shortest Path in Real-Time Robot Route Planning
by Linton Thiago Costa Esteves, Wagner Luiz Alvez de Oliveira and Paulo César Machado de Abreu Farias
Electronics 2024, 13(11), 2167; https://doi.org/10.3390/electronics13112167 - 2 Jun 2024
Viewed by 742
Abstract
This study introduces an optimization approach for calculating the shortest path in mobile robot route planning. The proposed solution targets real-time processing requirements by offering a high-performance alternative. This is achieved by embedding in the dedicated hardware an architecture which emphasizes parallelism. Through [...] Read more.
This study introduces an optimization approach for calculating the shortest path in mobile robot route planning. The proposed solution targets real-time processing requirements by offering a high-performance alternative. This is achieved by embedding in the dedicated hardware an architecture which emphasizes parallelism. Through improvements in parallel exploration techniques, our solution aims to present not only a boost in performance but also a dynamic adaptation to graph changes, accommodating randomly occurring edge insertions or deletions as environmental conditions fluctuate. We present the developed architecture alongside its results. Our method efficiently updates obstacle matrices, resulting in a remarkable 120-fold improvement for 1024-node graphs. When utilizing a cost-effective device like the Cyclone IV E, it achieves approximately 12 times the performance of software applications. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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