Search Results (98)

This paper presents the electrical characterization of the on-resistance (R_ON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) configurations. Since on-wafer samples have been characterized, a custom experimental setup was developed to emulate stress conditions experienced by the devices in the half-bridge circuit. A periodic signal (T = 10 µs, T_ON = 2 µs) switching from the OFF to the ON state was applied for a cumulative duration of 1000 s. Different OFF-state stress conditions were applied by varying the gate-source OFF voltage (V_GS,OFF) between 0 V and −10 V. The on-resistance exhibited a positive drift over time for devices in either the LS or the HS configuration, with the latter showing a more pronounced degradation. Measurements at higher temperatures (up to 90 °C) were carried out to characterize the dynamics of the physical mechanism behind the degradation effects. We identified hole emission from C-related acceptor traps in the buffer as the main mechanism for the observed degradation, which is present in both the HS and the LS configurations. The additional degradation observed in the HS case was attributed to the back-gating effect, stemming from the non-null body-to-source voltage. Furthermore, we found that a more negative V_GS,OFF further increases R_ON degradation, likely related to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps. Full article

This work investigates the impact of load-dump stress on p-GaN HEMTs under floating gate condition. The experiments show that preconditioning the device with a small load-dump stress (150 V, @t_d = 100 ms and t_r = 8 ms) enhances its robustness against a larger stress (190 V, @t_d = 100 ms and t_r = 8 ms). If a large load-dump stress (≥160 V, @t_d = 100 ms and t_r = 8 ms) is applied directly to the device’s drain, the device will burn out. This occurs because the rapidly changing drain voltage during a load-dump event can generate a capacitive coupling current, leading to transient positive charge accumulation in the gate region. Consequently, the channel under the gate is turned on, allowing a large current to flow through it. The coexistence of high current and high voltage leads to substantial Joule heating within the device, resulting in eventual burnout. When a small load-dump stress is initially applied, the resulting charging of electron traps in the gate region increases the threshold voltage. As a result, the device can withstand a larger load-dump stress before the channel turns on, which explains the device’s enhanced robustness. This work clarifies the failure threshold of p-GaN HEMTs under the load-dump stress, providing key support for improving the devices’ reliability in the practical applications. It can provide a basis for adding necessary protective measures in device circuit design, and clarify the triggering voltage threshold of protective measures to ensure that they can effectively avoid device damage due to the load-dump stress. Full article

This work first analyzes the failure behaviors of P-GaN HEMTs with different gate structures (Schottky gate vs. Ohmic gate) under both forward and reverse ESD stresses. It reveals that the Schottky gate structure lacks effective electrostatic charge discharge paths, which leads to the accumulation of transient charges generated by ESD stress in the gate terminal, resulting in significant transient overvoltage and ultimately causing breakdown failure. Subsequently, the paper systematically reviews three existing unidirectional ESD protection technologies based on the P-GaN HEMT platform. While these technologies can discharge transient electrostatic charges generated by both forward and reverse ESD stresses, they operate in diode mode during reverse ESD events, exhibiting excessively low reverse triggering voltage. Furthermore, unidirectional ESD protection structures based on resistive voltage division and diode voltage division introduce substantial forward and reverse leakage currents. Finally, the article evaluates four bidirectional GaN ESD protection technologies. These bidirectional structures can likewise discharge transient charges from both forward and reverse ESD stresses. Compared to unidirectional approaches, the key advantage of bidirectional ESD protection lies in its ability to provide an appropriate reverse triggering voltage during reverse ESD events, thereby effectively clamping the reverse potential to the desired level. However, likewise, bidirectional ESD protection schemes based on resistive or diode voltage division also inevitably introduce relatively large forward and reverse leakage currents. Full article

The increasing market demand for high-power and high-frequency applications necessitates the development of highly reliable Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs). While GaN offers superior performance and efficiency over traditional silicon, gate-related defects pose a significant reliability challenge, often leading to premature device failure under stress. Traditional High-Temperature Gate Bias (HTGB) testing is effective but time-consuming and costly, particularly when defects are only identified post-packaging. This study focuses on developing an effective wafer-level screening methodology to mitigate the financial burden and reputational risk associated with late-stage defect discovery. Failure analysis of an HTGB premature failure revealed a gate metal deposition defect characterized by identical elemental composition to the bulk metal, suggesting a small-volume structural anomaly. Crucially, a comparative analysis showed that Forward Gate Current (I_GON) is an insensitive screening metric due to high inherent gate leakage through the passivation layer. In contrast, the Reverse Gate Current (I_GOFF) exhibited sensitivity, particularly under the tensile stress induced by package molding, which is attributed to the piezoelectric effect altering the depletion region width beneath the p-GaN gate. Based on this observation, a multi-pulse I_DSS test was developed as a wafer-level screen. This method successfully amplified the subtle electrical field perturbations caused by the gate defect. After screening 231 dies using the new methodology, zero failures were recorded after 1000 h of HTGB stress, a significant improvement over the initial failure rate of 0.43% (1 out of 231). This work demonstrates that early, sensitive wafer-level screening of gate defects is indispensable for optimizing manufacturing yield and enhancing long-term device reliability. Full article

This study investigates a severe high-temperature reverse bias (HTRB) failure observed in GaN HEMTs, with devices failing in under 24 h. We conducted an in-depth analysis of the electrical and physical failure mechanisms, revealing that unbiased-highly accelerated stress testing (uHAST) can effectively induce dielectric delamination. The electrical and physical characteristics of devices post-delamination demonstrated a strong correlation between delamination at the nitride–polyimide interface and an increase in off-state drain leakage current (I_DSS). Our findings led to the removal of a suspected process step involving the use of the reactive chemical, N-methyl-2-pyrrolidone (NMP), before and after polyimide deposition. This critical process change yielded a significant improvement in reliability; while the initial failure rate was 25% at 24 h, three lots of 260 parts subsequently survived 1000 h of HTRB stress with no failure. In conclusion, uHAST is a valuable reliability testing tool for assessing package and film adhesion, leveraging high pressure and moisture to quickly identify and troubleshoot delamination-related reliability issues. Full article

High-electron-mobility transistors (HEMTs) are characterized by the formation of a two-dimensional electron gas (2DEG) induced by the polarization effects. Considerable studies have been conducted to improve the electrical properties of HEMTs by regulating the 2DEG density. In this study, a Si/GaN heterojunction was fabricated through the transfer of a heavily boron-doped Si nanomembrane. The holes in the p-Si layer integrated on top of the HEMT not only increased the surface positive charge, which eventually increased the density of electrons at the AlGaN/GaN interface, but also acted as a passivation layer to improve the performance of AlGaN/GaN HEMTs. Electrical characterization revealed that the maximum drain current increased from 668 mA/mm to 740 mA/mm, and the maximum transconductance improved from 200.2 mS/mm to 220.4 mS/mm. These results were due to the surface positive charge induced by the p-Si layer, which lowered the energy band diagram and increased the electron concentration at the AlGaN/GaN interface by a factor of 1.4 from 1.52 × 10²⁰ cm⁻³ to 2.11 × 10²⁰ cm⁻³. Full article

In this study, the effects of switching on the two-dimensional electron gas (2-DEG) channel in an E-mode GaN-on-Si HEMT are investigated using a GS-065-004-1-L device that is commercially available for educational practice. A practical prototype with a reduced number of components is proposed, with empirical concepts used to explain its predictive performance when a coreless transformer is series-connected to the E-mode GaN-on-Si HEMT for switching-mode conduction. Conduction modes arising at the p-GaN/n-AlGaN/i-GaN heterojunction in accordance with specifications from the manufacturer’s datasheet were validated using a didactic physical-based model dependent on semiconductor parameters of gallium nitride (GaN). Test circuit-examined waveforms were analyzed, which confirmed that the switching conduction mode of the 2-DEG channel is dependent on physical parameters such as switching operating frequency, temperature, low-field electron mobility, and space charge capacitance. Full article

In this paper, the impact of SiN passivation on dynamic-R_ON degradation of AlGaN/GaN HEMTs devices is put in evidence. To this end, samples showing different SiN passivation stoichiometry are considered, labeled as Sample A and Sample B. For dynamic-R_ON tests, two different experimental setups are employed to investigate the R_ON-drift showing up during conventional switch mode operation by driving the DUTs under both (i) resistive load and (ii) soft-switching trajectory. This allows to discern the impact of hot carriers and off-state drain voltage stress on the R_ON parameter drift. Measurements performed with both switching loci shows similar dynamic-R_ON response, indicating that hot carriers are not involved in the degradation of tested devices. Nevertheless, a significant difference was observed between Sample A and Sample B, with the former showing an additional R_ON-degradation mechanism, not present on the latter. This additional drift is totally ascribed to the SiN passivation layer and is confirmed by the different leakage current measured across the two SiN types. The mechanism is explained by the injection of negative charges from the Source Field-Plate towards the AlGaN surface that are captured by surface/dielectric states and partially depletes the 2DEG underneath. Full article

This work presents a novel Gallium Nitride (GaN) high-electron-mobility transistor (HEMT)-based ultraviolet (UV) photodetector architecture that integrates advanced material and structural design strategies to enhance detection performance and stability under room-temperature operation. This study is conducted as a fully numerical simulation using the Silvaco Atlas platform, providing detailed electrothermal and optoelectronic analysis of the proposed device. The device is constructed on a high-thermal-conductivity silicon carbide (SiC) substrate and incorporates an n-GaN buffer, an indium nitride (InN) channel layer for improved electron mobility and two-dimensional electron gas (2DEG) confinement, and a dual-passivation scheme combining silicon nitride (SiN) and hexagonal boron nitride (h-BN). A p-GaN layer is embedded between the passivation interfaces to deplete the 2DEG in dark conditions. In the device architecture, the metal contacts consist of a 2 nm Nickel (Ni) adhesion layer followed by Gold (Au), employed as source and drain electrodes, while a recessed gate embedded within the substrate ensures improved electric field control and effective noise suppression. Numerical simulations demonstrate that the integration of a hexagonal boron nitride (h-BN) interlayer within the dual passivation stack effectively suppresses the gate leakage current from the typical literature values of the order of ${10}^{-8}$ A to approximately ${10}^{-10}$ A, highlighting its critical role in enhancing interfacial insulation. In addition, consistent with previous reports, the use of a SiC substrate offers significantly improved thermal management over sapphire, enabling more stable operation under UV illumination. The device demonstrates strong photoresponse under 360 nm ultraviolet (UV) illumination, a high photo-to-dark current ratio (PDCR) found at approximately ${10}^6$, and tunable performance via structural optimization of p-GaN width between 0.40 μm and 1.60 μm, doping concentration from $5\times {10}^{16}$ ${\mathrm{cm}}^{-3}$ to $5\times {10}^{18}$ ${\mathrm{cm}}^{-3}$, and embedding depth between 0.060 μm and 0.068 μm. The results underscore the proposed structure’s notable effectiveness in passivation quality, suppression of gate leakage, and thermal management, collectively establishing it as a robust and reliable platform for next-generation UV photodetectors operating under harsh environmental conditions. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage. Full article

In this study, we introduce a high-resolution, high-speed thermal imaging technique using Raman spectroscopy to simultaneously measure the temperature of a substrate and a channel. By modifying the Raman spectrometer, we achieved a measurement speed faster than commercial spectrometers. This system demonstrated a sub-micron spatial resolution and the ability to measure the temperatures of the Si substrate and GaN channel simultaneously. During high-current operation, we observed significant self-heating in the GaN channel, with hotspots 100 °C higher than the surroundings, while the Si substrate showed an even temperature distribution. The ability to detect hotspots can help secure the reliability of devices through early failure analysis and can also be used for improvement research to reduce hotspots. These findings highlight the potential of this technique for early defect inspection and device improvement research. This study provides a novel and effective method for measuring the sub-micron resolution temperature distribution in devices, which can be applied to various semiconductor devices, including SiC-based power devices. Full article

We present THz direct detectors based on an AlGaN/GaN high electron mobility transistor (HEMT), featuring excellent optical sensitivity and low noise-equivalent power (NEP). These detectors are monolithically integrated with various antenna designs and exhibit state-of-the-art performance at room temperature. Their architecture enables straightforward scaling to two-dimensional formats, paving the way for terahertz focal plane arrays (FPAs). In particular, for one detector type, a fully realized THz FPA has been demonstrated in this paper. Theoretical and experimental characterizations are provided for both single-pixel detectors (0.1–1.5 THz) and the FPA (0.1–1.1 THz). The broadband single detectors achieve optical sensitivities exceeding 20 mA/W up to 1 THz and NEP values below 100 pW/$\sqrt{\mathrm{Hz}}$. The best optical NEP is below 10 pW/$\sqrt{\mathrm{Hz}}$ at 175 GHz. The reported sensitivity and NEP values were achieved including antenna and optical coupling losses, underlining the excellent overall performance of the detectors. Full article

We propose a novel ultraviolet (UV) phototransistor (PT) architecture based on an AlGaN/GaN high electron mobility transistor (HEMT) with a buried p-GaN layer. In the dark, the polarization-induced two-dimensional electron gas (2DEG) at the AlGaN/GaN heterojunction interface is depleted by the buried p-GaN and the conduction channel is closed. Under UV illumination, the depletion region shrinks to just beneath the AlGaN/GaN interface and the 2DEG recovers. The retraction distance of the depletion region during device turn-on operation is comparable to the thickness of the AlGaN barrier layer, which is an order of magnitude smaller than that in the conventional p-GaN/AlGaN/GaN PT, whose retraction distance spans the entire GaN channel layer. Consequently, the proposed device demonstrates significantly enhanced weak-light detection capability and improved switching speed. Silvaco Atlas simulations reveal that under a weak UV intensity of 100 nW/cm², the proposed device achieves a photocurrent density of 1.68 × 10⁻³ mA/mm, responsivity of 8.41 × 10⁵ A/W, photo-to-dark-current ratio of 2.0 × 10⁸, UV-to-visible rejection ratio exceeding 10⁸, detectivity above 1 × 10¹⁹ cm·Hz^1/2/W, and response time of 0.41/0.41 ns. The electron concentration distributions, conduction band variations, and 2DEG recovery behaviors in both the conventional and novel structures under dark and weak UV illumination are investigated in depth via simulations. Full article

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future. Full article