Search Results (203)

In this paper, we propose a novel method for fabricating high-thermal-stability Ohmic contacts on 4H-SiC using a low-doping-concentration (2.5 × 10¹⁵ cm⁻³) n-type epitaxial layer. The method employs a tungsten/carbon (W/C) multi-nanolayer stacked structure combined with a 1200 °C rapid thermal process (RTP). The fabricated Ohmic contacts achieve a specific contact resistance ρ_c of 2.53 × 10⁻⁴ Ω·cm² at room temperature (RT) and 1.29 × 10⁻⁵ Ω·cm² at 500 °C. Furthermore, they exhibit excellent long-term operational reliability, maintaining stable performance during a 500 °C high-temperature test for 100 h in air without significant degradation. This method eliminates the need for ion implantation, avoiding lattice damage and reducing fabrication cost. The demonstrated thermal stability is highly desirable for elevated-temperature SiC-based devices and integrated circuits. Full article

Reducing the Schottky barrier at the metal–semiconductor interface and achieving Ohmic contact is crucial for the development of high-performance Schottky field-effect transistors. This paper investigates the stability, interface interactions, interlayer charge transfer, and types of Schottky contacts in the graphene/ZnSe heterostructure structure using first-principles methods. It employs biaxial strain as a control mechanism. The results indicate that applying compressive strain increases the barrier and band gap while maintaining n-type contact; whereas tensile strain reduces the n-type barrier to negative values, inducing Ohmic contact and decreasing the band gap. The findings of this study will provide theoretical references for the design and fabrication of field-effect transistors, photodetectors, and other optoelectronic devices. Full article

Here, we report a facile technique for fabricating inkjet-printed PEDOT:PSS thermally active devices on commercial tattoo paper, subsequently transferred to Kapton substrate with pre-patterned copper tracks, to enable integration with other electronic systems. Printing parameters were investigated for consistent film quality. Electrical and thermal characterization confirmed stable ohmic behavior; after transfer, the device exhibited superior contact performance with lower measured electrical resistance. Temperature coefficient of resistance (TCR) of −0.0164 °C⁻¹ was measured, indicating the device’s capability for accurate temperature sensing. Additionally, a temperature exceeding 37 °C was achieved with a power consumption of approximately 50 mW. This work presents a robust method for passivating and transferring electronics for on-skin applications. Full article

In this paper, we demonstrate a simplified method for fabricating ohmic contacts on 4H-SiC substrates using pulsed UV laser surface modification followed by application of a silver-based conductive adhesive. Even a small number of laser passes significantly improved the contact interface, while ten or more repetitions produced linear I–V characteristics with low voltage drops. SEM analysis revealed surface ablation and an expanded effective area of the contact. Raman spectroscopy proved that laser processing leads to surface amorphization of the SiC sample. DFT simulations showed that the amorphous SiC layer is a material with no band gap, explaining the elimination of the Schottky barrier. Our approach enables the manufacturing of reliable, low-resistive contacts without high-temperature annealing and offers a practical route for rapid SiC device prototyping. Full article

Bow-tie microwave diodes have proven to be effective sensors of electromagnetic radiation across a wide wavelength range, from centimeter-scale radio waves to micrometer-scale mid-infrared radiation. Their operation is based on electron heating by strong electric fields. However, the experimental data obtained so far remain inconclusive, and the exact nature of the voltage detected by bow-tie diodes is not yet fully understood. In this work, we extend the investigation of the electrical properties of bow-tie diodes based on modulation-doped semiconductor structures with a wide spacer. The analysis focuses on the influence of diode metal contact geometry, illumination conditions, and orientation relative to the crystallographic axes. To elucidate the origin of the voltage detected by bow-tie diodes, we compare theoretical predictions of their electrical parameters—including voltage sensitivity, electrical resistance, asymmetry of the I–V characteristic in weak electric fields, and the nonlinearity coefficient of the I–V characteristic in strong electric fields—with corresponding experimental results. The results of our investigations indicate that, for most diodes, the detected voltage originates from electron heating by the microwave electric field, as evidenced by the polarity of the detected voltage matching the thermoelectric emf of hot carriers. Full article

In this study, high-conductivity W-doped Ga₂O₃ thin films were successfully fabricated by directly depositing a composition of Ga₂O₃ with 10.7 at% WO₃ (W:Ga = 12:100) using electron beam evaporation. The resulting thin films were found to be amorphous. Due to the ohmic contact behavior observed between the W-doped Ga₂O₃ film and platinum (Pt), Pt was used as the contact electrode. Current-voltage (J-V) measurements of the W-doped Ga₂O₃ thin films demonstrated that the samples exhibited significant current density even without any post-deposition annealing treatment. To further validate the excellent charge transport characteristics, Hall effect measurements were conducted. Compared to undoped Ga₂O₃ thin films, which showed non-conductive characteristics, the W-doped thin films showed an increased carrier concentration and enhanced electron mobility, along with a substantial decrease in resistivity. The measured Hall coefficient of the W-doped Ga₂O₃ thin films was negative, indicating that these thin films were n-type semiconductors. Energy-Dispersive X-ray Spectroscopy was employed to verify the elemental ratios of Ga, O, and W in the W-doped Ga₂O₃ thin films, while X-ray photoelectron spectroscopy analysis further confirmed these ratios and demonstrated their variation with the depth of the deposited thin films. Furthermore, the W-doped Ga₂O₃ thin films were deposited onto both p-type and heavily doped p⁺-type silicon (Si) substrates to fabricate heterojunction diodes. All resulting devices exhibited good rectifying behavior, highlighting the promising potential of W-doped Ga₂O₃ thin films for use in rectifying electronic components. Full article

To enhance the RF power properties of CMOS-compatible gold-free GaN devices, this work introduces a kind of GaN-on-Si HEMT with a low parasitic regrown ohmic contact technology. Attributed to the highly doped n⁺ InGaN regrown layer and smooth morphology of gold-free ohmic stacks, the lowest ohmic contact resistance (R_c) was presented as 0.072 Ω·mm. More importantly, low RF loss and low total dislocation density (TDD) of the Si-based GaN epitaxy were achieved by a designed two-step-graded (TSG) transition structure for the use of scaling-down devices in high-frequency applications. Finally, the fabricated GaN HEMTs on the Si substrate presented a maximum drain current (I_drain) of 1206 mA/mm, a peak transconductance (G_m) of 391 mS/mm, and a breakdown voltage (V_BR) of 169 V. The outstanding material and DC performances strongly encourage a maximum output power density (P_out) of 10.2 W/mm at 8 GHz and drain voltage (V_drain) of 50 V in active pulse mode, which, to our best knowledge, updates the highest power level for gold-free GaN devices on Si substrates. The power results reflect the reliable potential of low parasitic regrown ohmic contact technology for future large-scale CMOS-integrated circuits in RF applications. Full article

Gallium nitride (GaN) offers exceptional material properties, making it indispensable in communications, defense, and power electronics. With high electron mobility and robust thermal conductivity, GaN-based devices excel in high-frequency, high-power applications. They are vital in wireless communication systems, radar, electronic warfare, and power electronics systems, offering superior performance, efficiency, and reliability. Further research is crucial for optimizing GaN-based devices performance and expanding their applications, driving innovation across industries. The application of ion implantation technology in GaN-based devices is a key process that can be used to improve device performance and characteristics, which enables process aspects such as electrical isolation, ion implantation for ohmic contacts, threshold voltage regulation, and terminal design. In this paper, we will focus on reviewing the principles and issues of the ion implantation process in GaN-based device preparation. This work aims to serve as a guide for ion implantation in future GaN-based devices. Full article

The electrical properties of contacts to p-type nitride semiconductor devices, based on gallium nitride, were simulated by ab initio and drift-diffusion calculations. The electrical properties of the contact are shown to be dominated by the electron-transfer process from the metal to GaN, which is related to the Fermi-level difference, as determined by both ab initio and model calculations. The results indicate a high potential barrier for holes, leading to the non-Ohmic character of the contact. The electrical nature of the Ni–Au contact formed by annealing in an oxygen atmosphere was elucidated. The influence of doping on the potential profile of p-type GaN was calculated using the drift-diffusion model. The energy-barrier height and width for hole transport were determined. Based on these results, a new type of contact is proposed. The contact is created by employing multiple-layer implantation of deep acceptors. The implementation of such a design promises to attain superior characteristics (resistance) compared with other contacts used in bipolar nitride semiconductor devices. The development of such contacts will remove one of the main obstacles in the development of highly efficient nitride optoelectronic devices, both LEDs and LDs: energy loss and excessive heat production close to the multiple-quantum-well system. Full article

In this study we report on the structural, mechanical, and electrical characterization of different structures of vertically aligned zinc oxide (ZnO) nanowires (NWs) synthesized using hydrothermal methods. By optimizing the growth conditions, scanning electron microscopy (SEM) micrographs show that the ZnO NWs could reach an astounding 51.9 ± 0.82 µm in length, 0.7 ± 0.08 µm in diameter, and 3.3 ± 2.1 µm⁻² density of the number of NWs per area within 24 h of growth time, compared with a reported value of ~26.8 µm in length for the same period. The indentation modulus of the as-grown ZnO NWs was determined using contact resonance (CR) measurements using atomic force microscopy (AFM). An indentation modulus of 122.2 ± 2.3 GPa for the NW array sample with an average diameter of ~690 nm was found to be close to the reference bulk ZnO value of 125 GPa. Furthermore, the measurement of the piezoelectric coefficient (d₃₃) using the traceable ESPY33 tool under cyclic compressive stress gave a value of 1.6 ± 0.4 pC/N at 0.02 N with ZnO NWs of 100 ± 10 nm and 2.69 ± 0.05 µm in diameter and length, respectively, which were embedded in an S1818 polymer. Current–voltage (I-V) measurements of the ZnO NWs fabricated on an n-type silicon (Si) substrate utilizing a micromanipulator integrated with a tungsten (W) probe exhibits Ohmic behavior, revealing an important phenomenon which can be attributed to the generated electric field by the tungsten probe, dielectric residue, or conductive material. Full article

Constructing heterojunctions can combine the superior performance of different two-dimensional (2D) materials and eliminate the drawbacks of a single material, and modulating heterojunctions can enhance the capability and extend the application field. Here, we investigate the physical properties of the heterojunctions formed by the contact of different atom planes of Janus MoSSe (JMoSSe) and graphene (Gr), and regulate the Schottky barrier of the Gr/JMoSSe heterojunction by the number of layers and the electric field. Due to the difference in atomic electronegativity and surface work function (WF), the Gr/JSMoSe heterojunction formed by the contact of S atoms with Gr exhibits an n-type Schottky barrier, whereas the Gr/JSeMoS heterojunction formed by the contact of the Se atoms with Gr reveals a p-type Schottky barrier. Increasing the number of layers of JMoSSe allows the Gr/JMoSSe heterojunction to achieve the transition from Schottky contact to Ohmic contact. Moreover, under the control of an external electric field, the Gr/JMoSSe heterojunction can realize the transition among n-type Schottky barrier, p-type Schottky barrier, and Ohmic contact. The physical mechanism of the layer number and electric field modulation effect is analyzed in detail by the change in the interface electron charge transfer. Our results will contribute to the design and application of nanoelectronics and optoelectronic devices based on Gr/JMoSSe heterojunctions in the future. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

Fermi-level pinning (FLP) at metal–semiconductor interfaces remains a key obstacle to achieving low-resistance contacts in two-dimensional (2D) transition metal dichalcogenide (TMDC)-based heterostructures. Here, we present a first-principles study of Schottky barrier formation in WSe₂-MoSe₂ van der Waals heterostructures interfaced with four representative metals (Ag, Al, Au, and Pt). It was found that all metal–WSe₂/MoSe₂ direct contacts induce pronounced metal-induced gap states (MIGSs), leading to significant FLP inside the WSe₂/MoSe₂ band gaps and elevated Schottky barrier heights (SBHs) greater than 0.31 eV. By introducing a 2D metal-doped metallic (mWSe/mMoSe) layer between WSe₂/MoSe₂ and the metal electrodes, the MIGSs can be effectively suppressed, resulting in nearly negligible SBHs for both electrons and holes, with even an SBH of 0 eV observed in the Ag-AgMoSe-MoSe₂ contact, thereby enabling quasi-Ohmic contact behavior. Our results offer a universal and practical strategy to mitigate FLP and achieve high-performance TMDC-based electronic devices with ultralow contact resistance. Full article

In this work, the transport properties of charge carriers in $\beta$-Ga${}_2$O${}_3$ were investigated, along with intrinsic physical mechanisms such as lattice vibrations, impurity scattering, and interfacial effects. The high-field behavior of carrier mobility was characterized using vacuum deposition techniques for the fabrication of electrodes with ohmic contacts, and the Hall effect measurement system was employed to test the temperature-dependent mobility of Sn-doped n-type (100) and (001) $\beta$-Ga${}_2$O${}_3$ samples at a cryogenic temperature. A predictive model for $\beta$-Ga${}_2$O${}_3$ mobility was developed by examining the effects of the temperature on the scattering mechanisms based on a theoretical transport model. The experimental results for $\beta$-Ga${}_2$O${}_3$ mobility, which varied with the temperature and doping concentration, showed good agreement with the theoretical model within the temperature range of 15–300 K. The maximum discrepancy between the predictive model and the experimental data was less than 5%. This study provides valuable theoretical insights for the design and simulation of $\beta$-Ga${}_2$O${}_3$ devices. Full article

Aligned carbon nanotubes (A-CNTs) are emerging as one of the most promising materials for next-generation nanoelectronics. However, achieving reliable ohmic contacts between A-CNTs and metals remains a critical challenge. In this study, we employ rapid thermal annealing (RTA) to facilitate the formation of transition metal carbides at the metal–CNT interface, significantly reducing contact resistance and enhancing stability. Using the transmission line method (TLM), we demonstrate that RTA reduces the contact resistance at the Ti/A-CNT interface from 112.26 k$\mathrm{\Omega }·\mathrm{\mu }$m to 1.57 k$\mathrm{\Omega }·\mathrm{\mu }$m and at the Ni/A-CNT interface from 81.72 k$\mathrm{\Omega }·\mathrm{\mu }$m to 1.17 k$\mathrm{\Omega }·\mathrm{\mu }$m, representing a reduction of over an order of magnitude. Moreover, the Schottky barrier heights (SBHs) for both the Ti/A-CNT and Ni/A-CNT interfaces decreases by approximately 50% after annealing. A comparative analysis with Pd/A-CNT contacts shows that Ti and Ni contacts exhibit superior reliability under harsh conditions. This work provides a viable solution for improving the electrical performance and reliability of CNT-based devices, offering a pathway toward the development of future CMOS technologies. Full article