Search Results (323)

In this study, charge-trapping memory (CTM) transistors were developed using indium gallium zinc oxide (IGZO) as the oxide semiconductor channel and high-k HfO₂ as the charge-trapping layer, aiming for next-generation nonvolatile memory applications. To evaluate the impact of plasma exposure on film quality and device performance, HfO₂ thin films were deposited via atomic layer deposition (ALD) using both direct plasma (DP) and remote plasma (RP) modes. Post-deposition annealing (PDA) was applied to the IGZO and HfO₂ layers, with experiments conducted at various annealing temperatures to enhance the interfacial stability between the HfO₂ layer and the IGZO channel. Electrical characterization results demonstrated that the RP-processed devices exhibited a wider memory window, reduced gate leakage current, and improved threshold voltage stability compared with the DP-processed devices. Thermal treatment effectively reduced the interfacial defect density and enhanced the crystallinity at the dielectric–channel interface. These findings underscore that the selection of the plasma process and annealing conditions is critical in determining the electrical characteristics and reliability of oxide semiconductor-based CTM devices. Full article

Ferroelectric (FE) diodes configured in the metal–ferroelectric–metal (MIFM) structure are promising candidates for non-volatile memory. While recent studies emphasized bulk FE properties, interfacial characteristics have not been carefully considered. In this work, we investigate the HfO₂/Al_0.8Sc_0.2N interface by examining its impact on switching and rectifying characteristics in MIFM FE diodes with variable HfO₂ thicknesses (2/4/6 nm). Electrical characterization reveal that the increased HfO₂ thickness raises the coercive field (E_C) due to enhanced electrostatic effects and progressive interfacial oxidation from Sc-N to Sc-O bonds. This resulting oxygen substitutional defect (O_N) which may contribute to domain-wall pinning and reduced rectifying efficiency. Cycling tests clarify operating regime-dependent phenomena, including O_N redistribution-induced wake-up and eventual breakdown. Moreover, enhanced retention is observed after pre-cycling, originating from the stabilization of the interfacial defects rather than bulk properties. These findings underscore that E_C and device reliability are likely influenced by interfacial engineering, which is critical for the reliable operation of AlScN-based FE diodes. Full article

Processing-in-memory and in-memory computing (PIM/IMC) are increasingly explored to mitigate the von Neumann data-movement bottleneck that limits deep neural network (DNN) performance and energy efficiency. Progress, however, remains fragmented across device substrates, architectural prototypes, mapping and scheduling methods, compiler toolchains, and benchmarking practices, making results hard to compare and slowing deployment. This survey synthesizes developments from 2019–2025 along four coupled axes: (i) memory substrates and architectural design, (ii) mapping, partitioning, and scheduling, including learning- and graph-based strategies, (iii) compilers and end-to-end deployment flows, and (iv) benchmarking datasets, metrics, and reporting norms. Drawing on over twenty representative platforms spanning static random-access memory (SRAM) and dynamic random-access memory (DRAM), emerging non-volatile, capacitive, and photonic substrates, we clarify the trade-offs separating analog/charge-domain IMC from digital SRAM/DRAM-centric PIM, including reported peaks up to 600 TOPS/W and 1.5 TOPS/mm². We organize mapping frameworks into a unified reference taxonomy, identify recurrent evaluation pitfalls that undermine reproducibility, and highlight persistent gaps in training support, robustness under non-idealities, and coverage of large-scale GNN workloads. Finally, we outline a five-phase roadmap from benchmark standardization to industrial validation toward compiler-integrated, GNN-informed PIM/IMC systems validated on production-scale workloads. Full article

Van der Waals (vdW) multiferroic tunnel junctions (MFTJs) based on two-dimensional layered materials have emerged as a promising platform for next-generation non-volatile memory devices. In this work, we propose and theoretically investigate a high-performance all-vdW MFTJ consisting of a sliding ferroelectric bilayer GeC barrier sandwiched between asymmetric ferromagnetic metallic electrodes, Fe₃GaTe₂ and Fe₃GeTe₂. Using first-principles calculations combined with the non-equilibrium Green’s function (NEGF) method, we demonstrate that the bilayer GeC possesses robust vertical ferroelectricity switchable by interlayer sliding. By incorporating monolayer graphene as protective layers to mitigate metal-induced gap states, the device preserves the intrinsic ferroelectric polarization of the barrier. Our results reveal that four distinct non-volatile resistance states can be realized by independently manipulating the ferroelectric polarization and magnetization configurations. Remarkably, the device exhibits a giant Tunneling Magnetoresistance (TMR) ratio of up to 750.95% and a large Tunneling Electroresistance (TER) ratio of 322.97%. Furthermore, we observe perfect spin-filtering efficiency and a significant negative differential resistance (NDR) effect under finite bias voltage. These findings suggest that the Fe₃GaTe₂/graphene/bilayer-GeC/graphene/Fe₃GeTe₂ heterostructure is a compelling candidate for multifunctional spintronic applications in the post-Moore era. Full article

Cycle-to-cycle variability of switching parameters inherent to memristive devices introduces significant problems in the design of neuromorphic systems and non-volatile memory. This study investigates the dynamics of a second-order memristive system incorporating capacitive effects that model parasitic charge within individual memristors, addressing both the technical need for accurate analysis of complex regimes and the demand for exploratory environments. Simulations were performed using CUDAynamics, an interactive software suite developed by the authors, which utilizes parallel computing, primarily via NVIDIA Compute Unified Device Architecture (CUDA). It integrates multiple analysis tools for dynamical systems, including bifurcation diagrams, the largest Lyapunov exponent and periodicity mapping, and interactive navigation in multidimensional parameter spaces. The memristive system was discretized applying multiple integration methods with a fixed time step and various waveforms of the input signal. Analysis tools revealed well-defined regions of chaotic dynamics in the memristor resistance parameter space as functions of input signal properties. Sinusoidal and triangular waveforms produced topologically similar distributions of dynamical regimes, whereas the square waveform, mimicking digital inputs, generated distinct dynamical patterns while still preserving chaotic trajectories under specific conditions. Interactive visualization capabilities of CUDAynamics effectively demonstrate attractor evolution and hysteresis deformation, providing immediate visual feedback that significantly enhances conceptual comprehension of nonlinear feedback mechanisms. Beyond its practical implications for the design of analog and digital memristive devices, CUDAynamics offers a scalable, open-source toolkit to aid researchers and engineers in exploring complex dynamical phenomena. Full article

Reconfigurable radio frequency (RF) attenuators are critical passive components for 5G-Advanced and emerging 6G wireless systems. Conventional tunable attenuators rely on solid-state switches combined with fixed resistor networks, which suffer from unavoidable static power consumption and severe parasitic degradation at high frequencies. Here, we systematically demonstrate HfO₂-based non-volatile memristors as RF switches with tunable ON-state resistance (R_ON), enabling a switching-attenuation-integrated multistate attenuator. The fabricated Au/HfO₂/Ag devices exhibit stable bipolar resistive switching with an ON/OFF ratio exceeding 10⁹, reliable retention of 10⁵ s, and programmable R_ON continuously tuned from 5.8 Ω to 197.5 Ω. On-wafer RF characterizations from 10 MHz to 43.5 GHz reveal low insertion loss (−0.53 dB), high isolation (−26.8 dB), and clear scaling laws governing the effects of device geometry and R_ON on RF performance. Leveraging these unique characteristics, we propose a symmetric π-type programmable all-memristor attenuator architecture with a cascaded 2-unit configuration. The design achieves 12 discrete attenuation levels from 2 dB to 24 dB, a return loss better than 10 dB across the full band, and zero static power consumption without additional passive components or bias networks. This work establishes the fundamental material-device-RF performance relationship in HfO₂-based RF switches and provides a compact, low-power, and highly integrable solution for next-generation reconfigurable RF front-ends. Full article

The development of novel information-functional devices based on emergent physical phenomena is crucial for integrated circuit technology in the post-Moore era. Two-dimensional magnetic materials present an ideal platform for spintronic devices; however, regulating their room temperature magnetism poses significant challenges. Traditional methods like ionic liquid gating and strain control face issues such as poor stability and complex processes, complicating compatibility with standard silicon technology. Here, we demonstrate a straightforward and robust approach for dielectric layer-engineered room temperature ferromagnetism in 2D metallic magnets by leveraging metal–insulator–semiconductor (MIS) structures. Using surface-oxidized Fe₃GeTe₂ as a model system, we systematically investigate how SiO_x dielectric layer thickness (50–300 nm) modulates magnetic properties. Thin dielectric layers significantly enhance room temperature ferromagnetism through boosted interfacial charge transfer, whereas thick layers maintain the material near its intrinsic state due to dielectric screening effects. Furthermore, reversible optical modulation of magnetism is achieved under ultraviolet illumination, with photoresponse capability diminishing as dielectric thickness increases. This work establishes a scalable, silicon-compatible strategy for controlling 2D magnetism and provides critical insights for developing optically tunable spintronic devices and non-volatile memory applications. Full article

Memristors, as transformative electronic devices designed to transcend the von Neumann architecture, enable the physical unification of information storage and computation, thereby offering a foundational hardware pathway toward energy-efficient, brain-inspired computing. Their intrinsic analog resistive switching, non-volatility, and history-dependent learning capabilities allow them to natively implement in-memory computing and emulate synaptic plasticity, addressing the critical bottlenecks of energy and speed in conventional systems. Notably, the evolution from electrically controlled memristors to optoelectronic memristors marks a paradigm shift from pure computing to integrated sensing-processing, opening new dimensions for high-speed, parallel, and adaptive signal processing. In recent years, significant progress has been made in the development of memristor-based neuromorphic vision and tactile systems, on-chip signal processors, and dynamic trajectory trackers, demonstrating their potential in edge intelligence, adaptive robotics, and real-time perceptual tasks. This review systematically summarizes the latest advances in memristor technology, providing a comprehensive analysis of their operating mechanisms, material and structural innovations, and cutting-edge applications in neuromorphic perception and computing. Furthermore, it discusses the key challenges and future directions for the development and integration of memristor-based systems in the post-von Neumann era. Full article

Low-dimensional van der Waals (vdW) ferroelectrics are promising for next-generation low-power, non-volatile electronics and brain-inspired computing. Among them, CuInP₂S₆ (CIPS) has emerged as one of the most intensively explored systems. Distinct from conventional ferroelectrics, CIPS features a strong “ferroionic” coupling between ferroelectric order and long-range Cu⁺ migration, unlocking unique properties such as multiple polarization states, negative capacitance, and richly tunable conductance states. To date, however, a comprehensive review centered on this ferroionic coupling remains lacking. This review aims to fill that gap by systematically elucidating the ferroionic coupling mechanism, summarizing its manipulation through chemical composition engineering and external fields, and clarifying the dynamic conductive responses and related mechanism. This review further surveys the high-performance CIPS-based nanoelectronic devices enabled by unique properties and concludes with an outlook on future challenges and research directions. Full article

The proliferation of intelligent edge devices demands compact, low-power hardware capable of dynamically switching between sensing, logic, and learning tasks—a versatility that traditional multi-chip solutions fundamentally lack. Here, we demonstrate a reconfigurable spin–orbit torque (SOT) device based on an FeTb/Ru/Co synthetic antiferromagnetic (SAF) heterostructure. By modulating the input current amplitude, the device dynamically switches between two distinct operating modes: saturation and activation. In the saturation regime (>80 mA), deterministic magnetization reversal enables Boolean logic operations (AND, NOR). In the activation regime (<80 mA), gradual, non-volatile conductance modulation emulates synaptic plasticity. Benefiting from the strong antiferromagnetic coupling and near-zero net magnetization of the SAF structure, all operations are achieved without external magnetic fields. This single-device, dual-mode reconfigurable architecture establishes a new paradigm for high-density, low-power, multifunctional in-memory computing units, with promise for advancing adaptive edge computing chips. Full article

Charge-trapping memory (CTM) exhibits significant potential in high-density memory, yet reliability degradation resulting from the coupling of program/erase (P/E) cycles and electrical stress remains a key bottleneck for large-scale commercialization. This study focuses on a Au/Al₂O₃/TiO₂/p-Si CTM device, systematically investigating the device failure mechanism under continuously operating P/E cycles and constant voltage stress (CVS), with emphasis on elucidating the synergistic effect of bulk and interface defects on performance decay. Mechanistically, oxygen vacancies in TiO₂ serve as defect precursors, which form Frenkel pairs under electric field stress and further promote the formation of new defect precursors, thereby driving a self-sustaining defect evolution process. Interface traps, by contrast, arise from the cleavage of interfacial Si-H bonds triggered by electric field stress, resulting in a net elevation of the interface state density. The passive effects from the bulk and interface defects may give rise to issues, such as threshold voltage drift and decreased P/E speed. This work provides in-depth insights into the device failure mechanism of CTM, offering critical theoretical support for optimizing fabrication processes and enhancing long-term reliability. Full article

Additive engineering has become a critical strategy for optimizing the morphology and performance of bulk heterojunction (BHJ) organic solar cells (OSCs), while volatile solid additives have been widely employed to control nanoscale phase separation during film formation. Concerns regarding reproducibility, residual solvent effects, and long-term stability have stimulated increasing interest in non-volatile solid additives. In recent years, solid additive engineering has emerged as a promising approach for modulating molecular packing, regulating phase separation, enhancing charge transport, and improving device stability. However, a systematic analysis of its material design principles and performance impact remains limited. This review summarizes recent progress in solid additive engineering for OSCs, categorizing reported additives into non-volatile, volatile and nanomaterials. The effects of these additives on key photovoltaic parameters, including open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor (FF), and power conversion efficiency (PCE), are comparatively analyzed based on the reported data. Particular emphasis is placed on morphology and structural performance relationships and stability enhancement mechanisms. Finally, current challenges, including the lack of universal molecular design rules and limited mechanistic understanding of additive host interactions, are discussed, and future research directions are proposed. This review aims to provide a comprehensive perspective on the material-level role of solid additives and to guide the rational design of next-generation high-performance and stable organic solar cells. Full article

As emerging nonvolatile memory devices, ferroelectric field-effect transistors (FeFETs) have attracted significant attention for memory applications. However, due to the stochastic nature of fabrication processes and material properties, FeFETs exhibit pronounced device-to-device (DTD) variations, leading to threshold voltage dispersion and inconsistency in memory window (MW), which severely constrain array-level performance and reliability. In this study, a compact model-based variability analysis methodology for FeFETs has been proposed. Specifically, the Preisach ferroelectric (FE) hysteresis model was combined with the MIT Virtual Source (MVS) physical compact model to establish a macro-model for FeFETs, and statistical simulations were performed to evaluate device-level variations. Using the proposed framework, how fluctuations in two key FE parameters, film thickness (t_FE) and coercive field (E_C), affect FeFET transfer characteristics, threshold voltage (V_TH), and MW was systematically investigated. Monte Carlo (MC) simulations were further conducted to quantify the distribution width and statistical features of V_TH under different variability scenarios. The results indicate that random fluctuations in process-related parameters broaden the FeFET I_d-V_g characteristics, induce shifts in high/low threshold voltages, and cause MW variations. Moreover, when t_FE and E_C fluctuate simultaneously, the dispersions of V_TH and MW become significantly larger than those induced by a single-parameter fluctuation. The proposed compact-modeling framework and variability analysis approach enables the efficient evaluation of parameter tolerance and performance margin in FeFET arrays, providing guidance for storage-array design. Full article

Here, the resistive switching characteristics in a Cu/a-SiC/P+-Si sandwiched structure are systematically investigated for multilevel nonvolatile memory applications. The formation of Cu conducting filaments is believed to be the switching mechanism through temperature-dependent testing. Four distinguished resistance states can be achieved in the Cu/a-SiC/P+-Si memory device through the modulation of suitable compliance current, which could be attributed to the formation of more conductive filaments when applying a higher compliance current during the Set process. In addition, these different resistance values can be easily distinguished and show reliable retention (~105 s), with the temperature even reaching 85 °C, which offers considerable potential for high-density RRAM applications. Full article

Emerging non-volatile memories based on ferroelectric materials are currently under development to be integrated in the back-end-of-line of advanced complementary metal-oxide-semiconductor (CMOS) nodes. A life cycle assessment (LCA) over 16 impact categories has been carried out to compare planar (2D) and vertical (3D) integration strategies for the manufacturing of Hf_0.5Zr_0.5O₂-based ferroelectric capacitors on a 22 nm CMOS technology node. The LCA demonstrates that the 3D approach allows us to reduce the environmental impacts by up to 20% over several impact categories. The device isolation by a single chemical–mechanical polishing (CMP) step instead of the standard photolithography and plasma etching processes proved to be the main source of reduction on the overall environmental footprint. Full article