A Preisach–MVS Compact-Modeling Framework for Investigating Device Variability in Ferroelectric FETs Under Ferroelectric Thickness and Coercive-Field Fluctuations

Abstract

As emerging nonvolatile memory devices, ferroelectric field-effect transistors (FeFETs) have attracted significant attention for memory applications. However, due to the stochastic nature of fabrication processes and material properties, FeFETs exhibit pronounced device-to-device (DTD) variations, leading to threshold voltage dispersion and inconsistency in memory window (MW), which severely constrain array-level performance and reliability. In this study, a compact model-based variability analysis methodology for FeFETs has been proposed. Specifically, the Preisach ferroelectric (FE) hysteresis model was combined with the MIT Virtual Source (MVS) physical compact model to establish a macro-model for FeFETs, and statistical simulations were performed to evaluate device-level variations. Using the proposed framework, how fluctuations in two key FE parameters, film thickness (t_FE) and coercive field (E_C), affect FeFET transfer characteristics, threshold voltage (V_TH), and MW was systematically investigated. Monte Carlo (MC) simulations were further conducted to quantify the distribution width and statistical features of V_TH under different variability scenarios. The results indicate that random fluctuations in process-related parameters broaden the FeFET I_d-V_g characteristics, induce shifts in high/low threshold voltages, and cause MW variations. Moreover, when t_FE and E_C fluctuate simultaneously, the dispersions of V_TH and MW become significantly larger than those induced by a single-parameter fluctuation. The proposed compact-modeling framework and variability analysis approach enables the efficient evaluation of parameter tolerance and performance margin in FeFET arrays, providing guidance for storage-array design.

1. Introduction

As rapid advancements have been made in ferroelectric (FE) materials in microelectronics, emerging FE memories based on nanoscale thin films such as doped or alloyed HfO₂ have attracted extensive attention [1,2,3,4,5]. In particular, ferroelectric field-effect transistors (FeFETs) exploit the switchable spontaneous polarization of an FE gate stack to achieve nonvolatile storage, offering key advantages including improved endurance, multilevel storage capability, and CMOS process compatibility [4,6,7,8]. Nevertheless, similar to conventional transistors, FeFETs are susceptible to stochastic process perturbations during fabrication, which can lead to pronounced device-to-device (DTD) variations in threshold voltage (V_TH) [9,10,11,12]. More broadly, recent reviews focused on emerging thin-film device technologies have emphasized that scalable fabrication and device reproducibility under process tolerances are critical bottlenecks for practical deployment, rather than factors that merely contribute to achieving record performance [13,14]. This perspective directly motivates researchers to perform variability-aware FeFET modeling, where realistic process/material fluctuations in the ferroelectric gate stack must be translated into the statistical dispersions of key memory metrics such as V_TH and MW. Early studies further indicate that the complex microstructure of polycrystalline FE films in the gate dielectric introduces additional randomness: the FE layer typically consists of grains with diverse sizes and orientations, local regions may reside in FE or non-FE phases, and grain-boundary vicinities are often accompanied by charge trapping and localized phase transitions. As a result, spatially nonuniform energy barriers and domain-structure fluctuations can emerge during polarization switching [15,16,17,18]. As the device footprint shrinks, the number of switchable ferroelectric (FE) domains (or grains) participating in switching is reduced, so the inherently stochastic nucleation and growth process translates into markedly larger DTD dispersions in both threshold voltage (V_TH) and memory window (MW) [19]. This DTD variability has been repeatedly reported in experiments and TCAD studies, and is generally linked to the statistical nature of multi-domain switching in polycrystalline FE films, compounded by intrinsic microstructural and material inhomogeneity [20,21].

Despite the fact that meaningful progress has been made in terms of modeling randomness-induced variations in FeFET characteristics, most prior studies either (i) keep the FE layer thickness fixed and perturb only a limited subset of parameters, or (ii) approximate the FE as an effectively homogeneous dielectric and introduce variability predominantly at the interface and/or in the underlying channel stack. As a result, the scientific community still lacks a systematic understanding of how simultaneous fluctuations of multiple intrinsic FE parameters jointly shape both the static behavior and the statistical (distribution-level) characteristics of FeFETs. To address this research gap, our study provides a unified variability framework that co-considers coupled FE–parameter fluctuations and quantifies their combined impact on V_TH and MW evolution under scaling, thereby offering clearer physical attribution and more actionable design guidance for variability-aware FeFET optimization. In particular, since our primary objective is to perform large-sample DTD statistical evaluation and sensitivity analysis with manageable computational cost, we concentrate on quasi-static I_d-V_g characteristics and the resulting V_TH and MW distributions, which are the most direct metrics for read/write margin assessment in FeFET arrays. Incorporating switching dynamics and reliability metrics, such as endurance and retention, would typically require additional time-dependent parameters and degradation models, and also rely on more extensive experimental calibration data. Therefore, this is absent from our study and should be the subject of future work.

2. Modeling Methodology

To investigate the influence of the two ferroelectric parameters, t_FE and E_C, on the transport characteristics of FeFETs and inter-device variations, this study constructs a FeFET model based on a combination of the Preisach ferroelectric model and the MIT Virtual Source (MVS) model. Figure 1a illustrates the two variation sources of interest in this study: the ferroelectric layer thickness, t_FE, and the coercive field, E_C. Figure 1b shows the three scenarios discussed in this paper: the two ferroelectric parameters fluctuating individually and both fluctuating simultaneously, together with the corresponding assumed Gaussian probability density functions (pdfs) used for Monte Carlo sampling, where both parameters are modeled as Gaussian random variables with standard deviations set to 20% of their mean values. Figure 2 presents the baseline MOSFET structure used in this study and its equivalent modeling framework. The remainder of this article is organized as follows: Section 2 details the device structure and the Preisach–MVS joint modeling method; Section 3 presents the I_d-V_g characteristics of FeFET under different ferroelectric parameters, and Monte Carlo statistical analysis is conducted accordingly; and Section 4 summarizes the main conclusions and discusses the application prospects of this modeling in FeFET memory array design.

2.1. Individual MVS and FE Model

In this study, all FeFET simulations were built upon a common set of baseline metal–oxide–semiconductor field-effect transistor (MOSFET) parameters. To establish a reliable reference at the compact model level, the MVS model [22,23,24,25] was adopted to describe channel transport and calibrate its parameters under the condition of a non-FE gate dielectric to ensure that the simulated I_d-V_g characteristics match those of the target device. Although Preisach-type ferroelectric models can be embedded in TCAD platforms for physics-rich simulations, TCAD-based statistical variability analysis becomes computationally prohibitive when hundreds or even thousands of samples are required; therefore, compact Preisach–MVS coupling enables fast DTD statistical evaluation while preserving key physical knobs within a compact model framework. Figure 3 summarizes the calibration results: Figure 3a,b shows the I_d-V_g curves in linear and logarithmic scales, respectively. As can be observed, the MVS model agrees well with the reference data [26] in the subthreshold regime, the transition region around the threshold, and the strong inversion regime, thereby accurately capturing key metrics such as turn-on voltage and subthreshold slope.

In subsequent FeFET simulations, the calibrated MVS model is treated as the standard compact model of an ideal MOSFET in the absence of FE effects. Additional variability was not introduced into the baseline transistor. Instead, the focus was put on variations in FE layer parameters. This setup ensures that DTD differences in FeFET characteristics can be attributed to extrinsic variability induced by fluctuations in FE parameters, thereby highlighting the dominant roles played by FE layer thickness and coercive field in the overall DTD variation.

2.2. Preisach–MVS Coupled Model

After obtaining the reference MOSFET, an FE thin film was introduced into the gate stack to construct the target FeFET device, as illustrated in Figure 4a. The gate stack from top to bottom consists of a metal gate, an FE layer, a dielectric layer, and the channel. The FE layer thickness, t_FE, and coercive field, E_C, are considered to be two key variability parameters in this study, which primarily determine the available polarization charge and the threshold electric field required for polarization switching, respectively.

To capture the impact of FE hysteresis on channel conduction within a compact model framework, the Preisach–MVS coupled model was employed, as shown in Figure 4b. The core idea is to represent the FE layer as a multi-domain system composed of a large number of switching units, where each unit switches under a distinct electric field, and the superposition yields a macroscopic hysteresis loop. In the stacked structure, the FE layer is modeled as a nonlinear capacitor in series with the dielectric layer and the channel, and polarization charge is coupled to channel charge via charge conservation. For a given gate voltage, the effective voltage across the FE layer and the corresponding polarization state were first computed, and then the effective voltage was fed into the MVS model to obtain the drain current. In this way, the compact model consistently links polarization switching to variations in surface potential and channel current [27,28,29]. To ensure quantitative fidelity of the ferroelectric stack before performing variability analysis, we calibrate the Preisach ferroelectric parameters against the measured Q_FE–V_FE hysteresis loop of a metal–ferroelectric–metal (MFM) capacitor. Figure 5 compares the measured loop with the fitted Preisach result, showing that the loop shape and switching characteristics are well reproduced. This calibration strategy first fits the FE capacitor hysteresis, and then uses the calibrated FE response in the coupled device model. It is also consistent with experimentally calibrated FeFET compact-modeling studies reported in the literature, where calibrated models are validated against measured device-level trends and variability behaviors [18].

Then, the low-threshold voltage V_TH_L and high-threshold voltage V_TH_H were extracted from the two curves using the constant-current method, and MW was defined as follows:

$$\mathrm{M}\mathrm{W}={\mathrm{V}}_{\mathrm{T}\mathrm{H}}\text{\_}\mathrm{H}-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\text{\_}\mathrm{L}.$$

(1)

For each set of FE parameters, a full bidirectional sweep is conducted to extract V_TH_H, V_TH_L, and MW. In the subsequent sensitivity analysis, only one FE parameter is varied at a time to evaluate its impact. In the variability analysis, t_FE and E_C are simultaneously perturbed following Gaussian distributions, and MC simulations are performed to obtain the statistical distributions of V_TH and MW. Accordingly, throughout this study we extract the MW from quasi-static DC I_d-V_g hysteresis sweeps. This MW corresponds to the saturated window under the implicit assumption that the applied gate bias amplitude and sweep condition are sufficient to complete polarization switching in the ferroelectric layer. Under finite-duration programming pulses, the apparent MW additionally depends on pulse amplitude and pulse width through switching dynamics; such time-dependent effects are not considered here because this study focuses on static characteristics. In addition to t_FE and E_C, remanent polarization can also influence MW. However, in this study we do not treat polarization amplitude as an independent random variable, because it is strongly correlated with FE thickness in HfO₂-based thin films. For example, experimental studies on ultrathin doped HfO₂ report a pronounced thickness dependence of polarization switching, including a sharp reduction in switchable polarization when the film thickness is scaled below a critical value [30]. Therefore, in our Monte Carlo setup, varying t_FE naturally serves as a practical proxy that implicitly captures the correlated fluctuation in polarization amplitude, avoiding potential double counting of strongly coupled parameters.

3. Results

3.1. Parameter Dependence on FeFET Performance

Figure 6 shows the simulated FeFET I_d-V_g characteristics under different FE layer thicknesses (t_FE), where Figure 6a,b is plotted in linear and logarithmic scales, respectively. As t_FE increases, the drain current exhibits a clear change in both the turn-on region and the strong inversion region. Specifically, a thicker FE layer shifts the V_TH_H branch toward more positive gate bias, while shifting the V_TH_L branch toward more negative gate bias. This enlarges the horizontal separation between the two branches, i.e., a wider MW. Meanwhile, in the strong inversion regime, the on-current difference between the two branches becomes increasingly pronounced with t_FE. In contrast, the subthreshold slope shows only minor variations across different t_FE, indicating that within the considered parameter range the impact of t_FE on subthreshold swing is limited. This behavior can be understood as t_FE primarily modulates the threshold position by altering the effective input voltage coupled with the MVS channel model.

To quantify these trends more explicitly, Figure 7 summarizes the extracted threshold voltages and MW as functions of t_FE based on Figure 5. As shown in Figure 6a, V_TH_L decreases slightly with increasing t_FE, whereas V_TH_H increases markedly; consequently, their difference (MW) increases approximately linearly, as shown in Figure 6b. Physically, under the same gate–voltage sweep range, a thicker FE layer can support a larger accumulated polarization charge. After coupling through the gate stack, this leads to a larger effective modulation of channel charge, thereby producing a more pronounced separation of the two switching branches and ultimately a wider MW. However, further increasing t_FE also raises the gate voltage required to complete polarization switching. This not only increases power consumption but may also elevate the electric field stress in the dielectric layer, potentially introducing reliability concerns such as dielectric breakdown. Therefore, practical design requires a trade-off between achieving a sufficiently large MW and maintaining an acceptable operating voltage.

Figure 8 presents the FeFET I_d-V_g characteristics under different coercive fields (E_C). Similar to the effect of t_FE, increasing E_C enlarges the hysteresis width: the V_TH_H branch shifts toward more positive gate bias, while the V_TH_L branch shifts toward more negative gate bias, resulting in an expanded MW. Different from thickness scaling, E_C mainly determines the critical voltage required for polarization switching, and thus more directly affects the overall position of the hysteresis loop along the gate–voltage axis. With a larger E_C, the FE layer tends to remain in its initial polarization state over a wider gate–voltage range; switching occurs only after the applied bias exceeds the new critical value, which manifests as a systematic shift in the I_d-V_g curves.

Figure 9 further shows the extracted V_TH and MW as functions of E_C from Figure 7. The trends are similar across different t_FE cases: V_TH_L changes with a relatively small slope, whereas V_TH_H increases with a much larger slope; correspondingly, MW increases approximately linearly with E_C, as shown in Figure 8b. Compared with E_C sweeping, varying t_FE within a similar relative range produces a more pronounced change in MW, indicating that MW is more sensitive to t_FE than to E_C under the conditions considered. Overall, both t_FE and E_C can substantially influence the static characteristics of FeFETs: increasing either parameter can enlarge MW, but this also shifts the threshold-voltage positions and modifies the drain-current levels. These observations serve as the basis for the subsequent DTD variability analysis.

3.2. Analysis of DTD Variations

In this section, MC simulations were conducted to analyze three variability scenarios: (i) t_FE variation only; (ii) E_C variation only; and (iii) simultaneous variations in both t_FE and E_C. For each scenario, the nominal values of the FE parameters are used as the means, while the standard deviation is set to 20% of the mean. This 20% fluctuation range is a commonly used setting in TCAD or compact model-based variability studies to represent a reasonable level of process-induced variations. For example, researchers explicitly target lithography-induced gate-length dispersion and take $L_g$ fluctuation as the sole random variable; they apply a ±10% variation around the nominal $L_g$ and propagate this process variation through Monte Carlo sampling to evaluate circuit-level robustness. Under this setting, the simulated NOR gate still shows correct logic functionality and no observable hysteresis within the target window, enabling a meaningful statistical assessment of propagation-delay variability [31]. This study randomly generated 100 samples, simulated a complete hysteretic I_d-V_g characteristic for each sample, and extracted V_TH_L, V_TH_H, and MW. Although 100 samples may appear modest, this already falls into the “hundred-level statistics” regime that is commonly adopted for DTD variability benchmarking, where distribution-level metrics such as the coefficient of variation are extracted to draw robust conclusions and guide optimization. As discussed by Lanza et al., variability studies of key FET figures of merit, such as threshold voltage and subthreshold swing, are typically carried out on hundreds of devices to obtain statistically meaningful trends [32]. In this context, using N = 100 Monte Carlo samples in each scenario provides an effective and computationally efficient basis for comparing the extracted mean, standard-deviation and COV across different variation cases; meanwhile, larger N can be used in a straightforward way if tighter confidence bounds are required.

Figure 10a,b shows the I_d-V_g hysteresis curves of 100 samples when only t_FE varies, plotted in linear and logarithmic scales, respectively. It can be observed that the curves largely overlap in the subthreshold regime, whereas a certain horizontal spread appears near the threshold region and in strong inversion; however, the overall dispersion remains limited. Figure 10 further presents the corresponding statistical histograms of threshold voltages and MW. In Figure 11a, both V_TH_L and V_TH_H approximately follow Gaussian distributions, with mean values of ~0.01 V and ~1.51 V and standard deviations of 25 mV and 30 mV, respectively. Figure 11b shows that MW also follows an approximately Gaussian distribution, with a mean of 1.49 V and a standard deviation of 54 mV. These results indicate that even with a 20% fluctuation in thickness, the high/low threshold voltages and MW exhibit observable DTD dispersions, while the overall spread is constrained to the order of tens of millivolts.

Next, this study considered the scenario where only E_C varies. Figure 12a,b show the I_d-V_g hysteresis curves of 100 samples under E_C variation in linear and logarithmic scales. The random fluctuation in E_C primarily manifests as a translation of the hysteresis curves along the V_g axis. When E_C is smaller, the V_TH_L branch shifts toward more positive gate bias while the V_TH_H branch shifts toward more negative gate bias, leading to a reduced MW. Conversely, when E_C is larger, the V_TH_L branch shifts toward more negative gate bias and the V_TH_H branch shifts toward more positive gate bias, resulting in an enlarged MW. Importantly, the turn-on behavior and the drain current in strong inversion remain largely unchanged across samples. Figure 13a,b summarizes the extracted statistics: V_TH_L and V_TH_H still follow approximately Gaussian distributions with mean values of 0.013 V and 1.51 V and standard deviations of 18 mV and 32 mV, respectively, while MW has a mean of 1.49 V and a standard deviation of ~50 mV. Overall, within the prescribed 20% variability range, t_FE-only and E_C-only cases lead to DTD dispersions of comparable magnitude in both threshold voltage and MW.

When t_FE and E_C vary simultaneously, DTD variability is further amplified. Figure 14a,b show the I_d-V_g hysteresis curves of 100 samples when both parameters fluctuate with a 20% standard deviation. The envelope of curves near the threshold region becomes substantially wider: the locations of the V_TH_H and V_TH_L branches exhibit pronounced scattering across samples, and the branch separation (i.e., MW) also shows a larger fluctuation. The corresponding histograms in Figure 15a,b indicate that V_TH_L and V_TH_H have mean values of 0.006 V and 1.51 V, with standard deviations of 18 mV and 61 mV, respectively, while MW has a mean of 1.50 V and a standard deviation of 78 mV. Therefore, when thickness and coercive-field variations coexist, the dispersions of threshold voltage and MW become significantly larger than those induced by either single-parameter variation, exceeding the expectation from a simple linear superposition and indicating a synergistic amplification of DTD variability. This observed synergistic amplification originates from the fact that t_FE and E_C affect the two hysteresis branches through coupled mechanisms in the Preisach–MVS stack. On the one hand, varying t_FE changes the amount of polarization charge that can be accumulated and coupled to the channel, thereby modulating the effective input voltage seen by the MVS channel model and shifting the extracted threshold positions. On the other hand, E_C mainly sets the critical bias required for polarization switching, which manifests as a translation of the hysteresis loop along the V_g axis. Importantly, these effects are not independent: in a series-stacked gate, the branch transition points that define V_TH_H and V_TH_L are governed simultaneously by how strongly polarization charge shifts the channel and how much gate bias is needed to complete the branch switching. Therefore, when t_FE and E_C fluctuate together, the branch positions can be perturbed in a correlated manner, producing a broader spread than the simple linear superposition of single-parameter cases. This is consistent with the extracted statistics, where the joint-variation case yields a much larger standard deviation of V_TH and MW compared with the $t_{\mathrm{F}\mathrm{E}}$-only and $E_{\mathrm{C}}$-only cases, while the mean values remain almost unchanged. Figure 16a,b summarize the extracted dispersion metrics across the three scenarios. In terms of the standard deviation and coefficient of variation (COV) [33,34], the joint-variation case exhibits a substantially larger spread than either single-variation case. In summary, under the statistical range considered in this study, FeFET DTD variability is dominated by the coupled fluctuations of t_FE and E_C. This suggests that, at both the device and circuit levels, reducing the statistical dispersions of tFE and EC is essential for improving the reliability of large-scale FeFET arrays.

4. Conclusions

This study develops a coupled compact model for FeFETs by integrating the Preisach FE model with the MVS MOSFET model. The impacts of FE layer thickness, t_FE, and coercive field, E_C, on device performance and DTD variations have been systematically investigated. The results show that increasing either t_FE or E_C can significantly enlarge the MW. Under a 20% relative fluctuation, the case where t_FE and E_C vary simultaneously leads to substantially larger dispersions in V_TH and MW than (i) either single variability source alone and (ii) the direct superposition of their individual effects, indicating a pronounced synergistic amplification. Owing to its low computational cost and clear physical interpretability, the proposed model provides an efficient approach to evaluating V_TH distributions and read/write margins in FeFET arrays under realistic process fluctuations. It also serves as a foundation for incorporating additional process-variation sources to further optimize next-generation FE memory arrays.