Interface-Engineered, Low-Damage IGZO/HfO₂ Charge-Trapping Memory Devices Fabricated Using a Remote Plasma ALD Process

Abstract

In this study, charge-trapping memory (CTM) transistors were developed using indium gallium zinc oxide (IGZO) as the oxide semiconductor channel and high-k HfO₂ as the charge-trapping layer, aiming for next-generation nonvolatile memory applications. To evaluate the impact of plasma exposure on film quality and device performance, HfO₂ thin films were deposited via atomic layer deposition (ALD) using both direct plasma (DP) and remote plasma (RP) modes. Post-deposition annealing (PDA) was applied to the IGZO and HfO₂ layers, with experiments conducted at various annealing temperatures to enhance the interfacial stability between the HfO₂ layer and the IGZO channel. Electrical characterization results demonstrated that the RP-processed devices exhibited a wider memory window, reduced gate leakage current, and improved threshold voltage stability compared with the DP-processed devices. Thermal treatment effectively reduced the interfacial defect density and enhanced the crystallinity at the dielectric–channel interface. These findings underscore that the selection of the plasma process and annealing conditions is critical in determining the electrical characteristics and reliability of oxide semiconductor-based CTM devices.

1. Introduction

The increasing integration of artificial intelligence (AI) into modern electronic systems—including autonomous vehicles, smart devices, wearables, and Internet of Things (IoT) platforms—has driven the demand for high-density, low-power, and fast-operating memory technologies with long-term data retention capabilities [1,2,3,4,5]. These next-generation applications require memory devices that can simultaneously support continuous scaling, low energy consumption, and stable endurance. However, conventional Si-based flash memory technologies are approaching their physical and electrical limits [6,7,8,9,10,11]. As device dimensions continue to shrink into the deep sub-10 nm region, several critical issues arise: the exacerbation of the short channel effect (SCE), including drain-induced barrier lowering and gate-induced drain leakage, increased gate leakage due to thinner dielectric layers, and poor interface reliability. These challenges have prompted the exploration of novel materials and memory architectures to replace or augment the conventional charge storage mechanisms employed in flash memory devices [12,13,14,15,16].

Among various alternatives, charge-trapping memory (CTM) devices that utilize high-k dielectric materials as charge storage layers have emerged as potential candidates for nonvolatile memory (NVM) applications. In particular, hafnium oxide (HfO₂) has gained considerable attention owing to its wide bandgap (5.5–6.0 eV), high dielectric constant (20–25), high thermal and chemical stabilities, and compatibility with complementary metal–oxide–semiconductor (CMOS) processes. HfO₂ inherently accommodates oxygen vacancies, which serve as trap sites for charge storage and enable fast program/erase (P/E) operations. Recent studies have further demonstrated that the crystallographic phase of HfO₂ can be engineered to exhibit ferroelectric or perovskite-like behavior, opening new pathways for multilevel cell operation and low-voltage switching, which are essential in emerging applications such as neuromorphic computing, embedded NVM, and in-memory computing [17,18,19,20,21,22,23,24].

Parallel to the development of high-k dielectrics, the need for improved channel materials has become increasingly important. As conventional Si channels experience mobility degradation and enhanced surface scattering under continuous scaling, metal oxide semiconductors have emerged as viable alternatives. In particular, indium gallium zinc oxide (IGZO) has shown promise as a next-generation channel material owing to its high electron mobility, wide bandgap, low off-state leakage current, and favorable interface characteristics [25,26,27,28,29]. These advantages make IGZO a suitable candidate for advanced low-power and high-performance NVM devices [30,31,32,33,34,35].

A key factor in achieving reliable CTM operation lies in the quality of the interface formed between the charge-trapping layer and the semiconductor channel. Interface defects, interfacial oxides, and plasma-induced damage can degrade charge transport, reduce threshold voltage stability, and shorten data retention times. Therefore, careful control over thin-film deposition processes is essential. Among various deposition techniques, atomic layer deposition (ALD) is a widely adopted method for fabricating ultra-thin, conformal dielectric layers in advanced semiconductor devices [36,37,38,39].

ALD offers atomic-scale thickness control and uniform step coverage in high-aspect-ratio structures, making it advantageous for emerging 3D memory architectures such as 3D-NAND and vertical NVM arrays. Plasma-enhanced ALD has been widely adopted for high-k film deposition at low temperatures, as it can provide a high film density and a relatively high growth rate. However, the use of direct plasma (DP) ALD introduces energetic ions that can physically bombard the substrate surface, generating interface traps, inducing sub-gap states, and degrading the channel–dielectric interface. These adverse effects become particularly pronounced in ultrathin films and multi-layer stacks, limiting the scalability and reliability of DP-ALD processes [40,41,42,43,44]. Consequently, remote plasma ALD (RP-ALD) has emerged as a potential alternative. In RP-ALD, plasma is generated in a region separate from the deposition chamber, and only neutral radicals are introduced into the process area. This separation suppresses ion-induced damage and directional bombardment while still enabling effective precursor activation and stable film growth [45,46,47,48,49].

In this study, CTM transistors were fabricated using IGZO as the channel layer and HfO₂ as the charge-trapping layer. To investigate the impact of plasma-induced damage on device performance, HfO₂ thin films were deposited using both DP-ALD and RP-ALD processes. The IGZO channel layer was deposited via RF magnetron sputtering, after which both layers were simultaneously subjected to post-deposition annealing (PDA) at various temperatures to observe the resulting interfacial reactions. The electrical characteristics of the devices, including memory window, threshold voltage stability, and leakage current behavior, were evaluated and compared. Further, structural and chemical analyses, such as X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and transmission electron microscopy (TEM), were conducted to examine possible differences in film crystallinity and interface quality between the two ALD methods. The advantages of RP-ALD over DP-ALD in terms of suppressing plasma-induced interface degradation and enhancing charge-trapping efficiency were evaluated. We demonstrate how RP-ALD enables more stable and reliable CTM operation, making it an effective deposition technique for fabricating advanced oxide semiconductor-based NVM devices [50,51,52,53,54].

2. Materials and Methods

2.1. CTM Device Fabrication Using IGZO and HfO₂

Figure 1 outlines the experimental setups and process timing sequences used in this study. Schematic diagrams of the DP-ALD and RP-ALD systems are presented in Figure 1a,b, while the corresponding valve switching sequences are shown in Figure 1c. Unlike DP-ALD, in which the substrate is directly exposed to the plasma discharge, RP-ALD spatially separates the plasma generation region from the main chamber using a remote inductively coupled plasma source and an Ar carrier gas. This dual-mode capability was integrated into a unified ALD system to isolate the distinct effects of the plasma mechanisms while maintaining identical critical parameters, such as chamber design, flow dynamics, and precursor delivery profiles. Consequently, the RP configuration employs a mesh to safeguard the substrate from direct ion bombardment by allowing only neutral radicals to reach the surface, whereas the DP mode allows direct interaction of all plasma species with the substrate surface. As shown in the timing sequence in Figure 1c, the DP-ALD process was conducted with an oxygen injection time of 4 s and a plasma exposure time of 2 s, whereas the RP-ALD process employed an optimized sequence consisting of 10 s oxidation and 15 s plasma generation.

Bottom-gated flash memory thin-film transistors (TFTs) with an IGZO channel (In:Ga:Zn = 1:1:1 atomic ratio) were fabricated, as shown in Figure 2a. As the control bottom gate of the charge-trapping flash memory device, a heavily doped n-type silicon substrate (resistivity < 0.005 Ω·cm) was employed. The substrate was cleaned using the SC-1 process, followed by a 30 s dilute hydrofluoric acid (HF) dip to remove the native oxide layer. The dielectric stack comprised a blocking layer (Al₂O₃, 10 nm), a charge-trapping layer (HfO₂, 10 nm), and a tunneling layer (Al₂O₃, 3 nm), sequentially deposited using both direct plasma ALD (DP-ALD) and remote plasma ALD (RP-ALD). For Al₂O₃ deposition, TMA (trimethylaluminum, iChems, Hwaseong, Republic of Korea) was used as the precursor, and the films were deposited at 240 °C in an O₂ plasma atmosphere with Ar carrier gas (600 sccm) and O₂ flow (150 sccm). For HfO₂ deposition, TEMAHf (Tetrakis(ethylmethylamino) hafnium, iChems) was used as the precursor under the same conditions (240 °C, O₂ plasma ambient).

In the DP-ALD process, plasma directly interacted with the substrate during discharge, whereas in the RP-ALD system, plasma was generated using an inductively coupled plasma method in a region separate from the substrate and then transported via a carrier gas. For a direct comparison under identical conditions, the ALD system (iOV-dx2, iSAC Research, Daejeon, Republic of Korea) was modified to incorporate both DP-ALD and RP-ALD within a single apparatus. In the RP-ALD mode, only neutral plasma radicals could pass through the mesh, whereas in the DP-ALD mode, all the plasma radicals can interact with the substrate. DP-ALD was performed using a built-in plasma generator with O₂ as the reactive gas and under a plasma power of 150 W, whereas RP-ALD was performed using a remote plasma source (En2ra-RPS, EN2CORE Technology, Daejeon, Republic of Korea) with a plasma power of 2600 W. After deposition of the dielectric stack, a 50-nm-thick amorphous IGZO (a-IGZO) channel layer was deposited using a metal shadow mask. The IGZO channel was deposited by RF magnetron sputtering at room temperature in an Ar atmosphere, with channel dimensions of 100 μm (width) and 300 μm (length). PDA was subsequently performed in a N₂ ambient at 300, 500, and 700 °C for 20 min to impart the IGZO channel with crystallinity. The source/drain electrodes deposited by DC magnetron sputtering (Sputtering System, BLS, Hwaseong, Republic of Korea) at 100 W for 4 min in an Ar atmosphere. Electrode patterning was achieved using a photolithography process.

Figure 2b presents an optical microscopy (top-view) image of the fabricated IGZO channel device. Figure 2c illustrates a representative energy band diagram of the a-IGZO CTM device in the programming state. As shown, the application of a positive gate voltage induces the injection of electrons from the a-IGZO channel into the HfO₂ charge-trapping layer through the thin Al₂O₃ tunneling oxide. These injected electrons are stored within the HfO₂ layer, which governs the core operation of the CTM device.

2.2. Electrical and Structural Characterization of DP- and RP-ALD Devices

The electrical characteristics of the fabricated three-terminal CTM devices were evaluated using a semiconductor characterization system (4200A-SCS, Keithley, Cleveland, OH, USA) integrated with a microprobe station (APX-6B, WIT Co., Suwon, Republic of Korea). Memory operations were performed within a pulse voltage range of approximately ±15 V and a pulse duration of 1 ms. The electrical characteristics, including charge-trapping capability and reliability, were evaluated for the CTM devices annealed at 300, 500, and 700 °C. Additionally, a UV-erasing process was conducted using a UV LED (λ = 395 nm, power = 0.5 W) to reset the memory state by neutralizing trapped charges before each characterization cycle. The structural and morphological properties were analyzed through multistep characterization. The top-view images of the devices were captured using optical microscopy. The thicknesses of the HfO₂ films deposited using the DP and RP-ALD were measured using spectroscopic ellipsometry (Elli-SE-U, Ellipso Technology, Suwon-si, Republic of Korea). The crystalline structure and interfacial characteristics were confirmed using high-resolution XRD (SmartLab, Rigaku, Tokyo, Japan) and high-resolution transmission electron microscopy (HR-TEM; JEM-2100F (HR), JEOL, Suwon-si, Republic of Korea). The elemental composition of each layer was analyzed via energy-dispersive X-ray spectroscopy (EDS) equipped with the TEM system. Furthermore, the chemical composition and defect states of the HfO₂ films were analyzed using X-ray photoelectron spectroscopy (Sigma Probe, Thermo Fisher Scientific, Suwon-si, Republic of Korea) with a monochromatic Al Kα source. These comprehensive analyses allowed for the systematic evaluation of the electrical performance and long-term reliability of IGZO-based memory devices.

3. Results

3.1. Structural and Chemical Characterizations of HfO₂ Films (DP vs. RP)

An XRD analysis was performed to investigate the effects of the plasma mode (DP vs. RP) and annealing temperature on the device characteristics. Figure 3 presents the XRD patterns of the HfO₂/IGZO stacked structure and the single IGZO layer under various thermal conditions. For the samples processed in the direct plasma (DP) mode (Figure 3a), no distinct diffraction peaks were observed at 300 °C, indicating that the film remained in an amorphous state. At 500 °C, a HfO₂ (111) peak near 28.5° began to emerge, and at 700 °C, both the HfO₂ (111) peak and a weak IGZO (009) peak near 30.5° were clearly observed. Notably, the crystallization peak of IGZO only emerged at the high temperature of 700 °C in the DP mode.

Figure 3b shows the XRD patterns of the HfO₂/IGZO thin films deposited using the RP mode. Unlike the DP mode, no distinct HfO₂ (111) peak was observed at 500 °C, suggesting that the RP-ALD process delays HfO₂ grain growth in the intermediate temperature range, likely due to the reduced ion bombardment energy during deposition. Under the RP 700 °C condition, a clear and sharp peak was observed at 30.5°, corresponding to the IGZO (009) crystal plane, with a significantly higher intensity compared with the DP 700 °C condition. The presence of this peak indicates that the RP 700 °C process promotes crystalline growth with a strong preferred orientation along the (009) direction.

Figure 3c presents the XRD patterns of the single-layer IGZO film, where only very small peaks can be observed without distinct crystallinity when IGZO exists alone. These results demonstrate that the stacked structure of IGZO and HfO₂ contributes to enhancing the crystallinity of the IGZO layer, as evidenced by the improved diffraction characteristics within the stack compared with the single-layer film.

Figure 4 presents the cross-sectional TEM images of the IGZO/HfO₂ devices annealed at DP 700 °C and RP 700 °C. The DP 700 °C sample was selected based on the preliminary XRD results, which identified it as having the most optimized IGZO diffraction peaks. In contrast, the RP 700 °C sample was chosen to visually verify the c-axis aligned (009) crystallinity previously observed in the RP-mode XRD data.

As shown in Figure 4a,c, both devices exhibit a well-defined vertical stack comprising an IGZO channel layer (~30 nm) and an HfO₂ charge-trapping layer (~10 nm). The interfaces between the IGZO, HfO₂, and the adjacent dielectric layers are distinct, with no observable physical defects such as voids or undesirable interfacial reactions. To identify each layer, EDS elemental mapping was performed, and the results are provided below each corresponding image. The EDS analysis confirmed that the In, Ga, and Zn components were clearly distinguished from the Hf and Si elements, demonstrating sharp and well-defined interfaces. For the DP 700 °C device (Figure 4b), the fast Fourier transform (FFT) pattern revealed diffused halo rings along with faint crystalline features, indicating that the IGZO layer maintains a polycrystalline state without a specific preferred orientation. Conversely, the RP 700 °C device (Figure 4d) showed clearly ordered lattice fringes aligned in a specific direction within the IGZO layer. The distinct diffraction spots in the FFT pattern confirmed the formation of crystalline IGZO with a preferred (009) orientation.

The chemical bonding states of the HfO₂ thin films fabricated via DP- and RP-ALD were compared using XPS as a function of the ALD mode and annealing temperature. Figure 5a,b present the Hf 4f and O 1s spectra of the film deposited by DP-ALD after annealing at 500 °C, while Figure 5c,d show the corresponding spectra of the RP-ALD-deposited film at the same annealing temperature.

A comparison of the Hf 4f spectra reveals that the combined ratio of Hf7/2 and Hf5/2 (corresponding to the stoichiometric Hf4+ state in HfO₂) was 73.1% for the DP mode, whereas it increased to 80.37% for the RP mode at 500 °C. This indicates a higher concentration of the stoichiometric HfO₂ phase in the RP-processed film. Additionally, the DP-processed sample exhibited a sub-oxide (Hf–O–M) ratio of 26.9%, which decreased to 19.63% in the RP-processed sample.

This structural improvement is further supported by the O 1s spectral analysis. The ratio of oxygen vacancies (VO) decreased from 29.3% in the DP process to 25.33% in the RP process. Conversely, the ratio of lattice oxygen (M–O), which indicates stronger atomic bonding, increased from 55.99% to 57.7%.

The influence of a higher annealing temperature was further investigated for the RP-ALD process at 700 °C (Figure 5e,f). At 700 °C, the stoichiometric Hf4+ ratio remained consistently high at 80.77%, while the lattice oxygen (M–O) ratio further increased to 60.98%, which was the highest among all conditions. This enhancement suggests that the RP-ALD process not only provides a low-damage deposition environment but also facilitates the formation of a more chemically stable and denser thin film during high-temperature thermal treatment.

These results indicate that the RP-ALD process minimizes plasma-induced damage compared with the DP mode, thereby facilitating the formation of chemically stable thin films with reduced defects and enhanced thermal stability.

3.2. Electrical Characteristics of IGZO/HfO₂ TFTs

To evaluate the effects of the plasma mode (DP vs. RP) and annealing temperature on the reliability of gate dielectrics, the leakage current and breakdown voltage (V_BD) characteristics were analyzed using Figure 6. The RP-processed devices (solid lines) exhibited enhanced insulation properties compared with the DP devices (dashed lines). Across all annealing temperatures, the RP samples maintained a stable, low leakage current prior to a distinct hard breakdown. In contrast, the DP samples demonstrated a tendency toward soft breakdown or premature failure, with the leakage current gradually increasing at lower voltages.

The DP 500 °C and DP 700 °C samples exhibited earlier instability, showing an increase in leakage current at applied voltages below approximately 15 V. Conversely, the RP-processed devices recorded higher breakdown voltages. The RP 500 °C condition achieved a maximum V_BD of approximately 24.5 V. Under the RP 700 °C condition, V_BD decreased slightly to approximately 19.5 V, yet it remained higher than those under all DP conditions.

In summary, the RP process improves the insulation characteristics of the device by minimizing plasma-induced damage and reducing interface defects across the constituent layers [55,56].

Figure 7 illustrates the transfer characteristics of the fabricated devices in their initial, programmed, and erased states. The programming operation was performed by applying a voltage pulse of 15 V for 1 ms, while the erase operation utilized UV irradiation instead of a negative gate bias. Under these conditions, the DP-processed devices (Figure 7a,c,e) exhibited instability, characterized by a negative shift in the threshold voltage (V_th) during programming and erasing operations.

In contrast, the RP-processed devices (Figure 7b,d,f) demonstrated stable initial V_th values near 0 V. For CTM operations, the memory window (ΔV_th) improved significantly in the RP devices compared with the DP devices, increasing from 2.0 to 10.4 V at 300 °C, from 2.2 to 9.6 V at 500 °C, and from 4.2 to 7.8 V at 700 °C. Notably, the RP 500 °C condition (Figure 7d) secured a broad memory window while maintaining stable switching behavior.

Consequently, by controlling surface defects and enhancing charge storage performance, the RP process presents potential applicability for realizing future NVM devices [57,58].

To characterize the electrical properties of the fabricated CTM devices, the field-effect mobility (μ_FE), memory window (ΔV_th), subthreshold swing (SS), threshold voltage (V_th), and interface trap density (D_it) were extracted from the transfer characteristics and are presented in

Table 1. Summary of electrical parameters for CTM devices fabricated using DP and RP processes at different annealing temperatures.

Temperature [°C]	Deposition Type	Mobility [cm2/V·s]	Memory Window [V]	SS [V/dec]	Vth [V]	Ion/Ioff	Dit [1013 eV−1 cm−2]
300	DP	11.46	2	0.211	4	4.04 × 107	2.46
	RP	11.95	10.4	0.212	1.4	8.38 × 106	1.41
500	DP	16.16	2.2	0.274	−7.0	4.31 × 107	1.38
	RP	17.3	9.6	0.219	1.2	2.56 × 107	1.03
700	DP	6.37	4.2	0.324	−2.8	7.19 × 106	1.31
	RP	19.8	7.8	0.228	0.6	5.26 × 107	1.09

and Figure 8. The overall operational characteristics of the RP devices are compared with those of recently reported IGZO-based CTM devices in

Table 2. Comparison of memory performance with recent IGZO-based CTM devices.

Channel /Trap Layer	Mobility [cm2/V·s]	Memory Window [V]	SS [V/dec]	Ion/Ioff	Reference
IGZO/HfO2	11.95	10.4	0.212	8.38 × 106	This Work (RP 300 °C)
IGZO/HfO2	17.30	9.6	0.219	2.56 × 107	This Work (RP 500 °C)
IGZO/HfO2	19.80	7.8	0.228	5.26 × 107	This Work (RP 700 °C)
IGZO/SiNx	11.6	5.8	0.300	~107	[29]
IGZO/HfO2-x	12.0	6.5	0.280	>108	[59]
IGZO/ZnO	7.1	7.2	0.670	~107	[60]

.

First, μ_FE exhibited contrasting trends between the two processes as a function of temperature (Figure 8a). For the RP devices, the mobility increased from 11.95 to 19.8 cm²/V·s with an increase in annealing temperature from 300 to 700 °C. In contrast, the DP devices showed an initial increase in mobility up to 500 °C, reaching 16.16 cm²/V·s, followed by a decrease to 6.37 cm²/V·s at 700 °C.

Second, ΔV_th and operational stability further distinguished the two processes (Figure 8b,d). Specifically, the RP 500 °C condition demonstrated a balanced performance, achieving a memory window of 9.6 V and the lowest D_it of 1.03 × 10¹³ eV⁻¹ cm⁻².

The RP devices maintained consistently low SS values ranging from 0.212 to 0.228 V/dec.

To analyze the correlation between the threshold voltage (V_th) variation and electrical performance with respect to the annealing temperature in the DP and RP processes, the variations in the transfer curves and the distributions of key parameters (I_on, V_th) are illustrated in Figure 9.

Figure 9a shows the evolution of the transfer characteristics for the DP and RP devices with an increase in the annealing temperature from 300 to 700 °C. The DP-processed devices (dotted lines) exhibited a shift in the threshold voltage (V_th) and an increased variance with temperature. In contrast, the RP-processed devices (solid lines) demonstrated thermal stability, with the transfer curves remaining largely consistent despite the temperature changes.

Figure 9b presents the I_on and V_th distributions under each process condition. While the parameters for the DP devices are widely dispersed, those for the RP devices are concentrated in the region of high I_on and a V_th value near 0 V. This narrow distribution under the RP conditions indicates a uniform and structurally stable film.

To clarify the discrepancy in the transconductance (G_m), which governs the driving performance of the devices, the channel intrinsic mobility (μ₀), contact resistance (R_c), and interface trap density (D_it) were decoupled and analyzed. For this purpose, the Y-function method was adopted, and each parameter was extracted using the following mathematical derivations.

First, to evaluate the inherent charge transport capability of the channel, μ₀ was extracted using the slope of the Y-function (slope_Y), as expressed in Equation (1):

$${\mu }_0={\displaystyle \frac{{\left({slope}_Y\right)}^2}{\begin{array}{c}\left(W/L\right)\cdot C_{ox}\cdot V_{ds}\end{array}}}$$

(1)

As illustrated in Figure 10c, the trend in the extracted μ₀ contrasts with that observed in G_m. Specifically, a relatively high μ₀ was extracted under the DP 700 °C condition, indicating that although crystallization within the channel had progressed, it did not translate into a proportional increase in G_m. This suggests that external factors, rather than the intrinsic channel properties, impeded carrier transport.

To investigate the cause of this discrepancy between μ₀ and G_m, the contact resistance (R_c) was calculated based on the difference between the peak transconductance (g_peak) and the theoretical intrinsic transconductance (g_intrinsic), as expressed in Equation (2):

$$R_c={\displaystyle \frac{1}{2}}({\displaystyle \frac{1}{g_{peak}}}-{\displaystyle \frac{1}{g_{intrinsic}}}), \mathrm{where} g_{intrinsic}={\displaystyle \frac{W}{L}}{C}_{ox}{\mu }_0{V}_{ds}$$

(2)

Generally, a transfer length method with varying channel lengths is required to precisely determine contact resistance. However, due to the single-device configuration employed in this study, R_c was estimated using Equation (2). The reliability of this extraction is supported by the correlated trends in μ₀ (Figure 10c) and D_it (Figure 10d).

As shown in Figure 10b, a significant increase in R_c can be observed under the DP 700 °C condition. This explains the low G_m despite the high μ₀. The resistance generated at the electrode–channel interface (extrinsic), rather than within the channel itself (intrinsic), acts as a primary limiting factor for current flow, thereby degrading overall device performance. In contrast, the RP devices maintained a low R_c across all temperature ranges, allowing the high μ₀ to contribute to G_m enhancement without substantial degradation.

Finally, to evaluate the impact of interface quality on switching efficiency, the interface trap density D_it was derived from the SS according to Equation (3):

$$D_{it}={\displaystyle \frac{C_{ox}}{q}}({\displaystyle \frac{SS}{{SS}_{ideal}}}-1)$$

(3)

As illustrated in Figure 10d, the RP devices exhibited lower D_it values overall compared with the DP devices. According to Equation (3), the lower SS values correlate with a reduced D_it, implying that charge loss induced by interface traps is minimized during gate operation.

Consequently, the RP process proves to be an effective approach for realizing high-performance memory devices. By concurrently achieving low R_c and low D_it, the intrinsic performance of the channel is effectively translated into G_m with minimized parasitic loss.

To evaluate the long-term reliability and operational stability of the fabricated CTM devices, data retention and P/E endurance tests were conducted, as shown in Figure 11. For the reliability measurements, the programming operation was performed using a 15 V voltage pulse for 1 ms, and the erase operation was conducted using UV irradiation.

Figure 11a,c,e present the data retention characteristics of the devices extrapolated to 10 years at room temperature. The RP-processed devices exhibited consistent charge retention across all annealing temperatures. Specifically, the RP devices annealed at 300, 500, and 700 °C retained approximately 96%, 98%, and 95% of their initial memory windows after 10 years, respectively. In comparison, the DP-processed devices showed a decrease in charge retention over time, with retention rates of 49%, 81%, and 29% under the 300, 500, and 700 °C conditions, respectively.

Figure 11b,d,f show the P/E endurance characteristics over 10³ cycles. The RP-processed devices demonstrated stable cyclic endurance. The RP 500 °C device maintained its initial memory window of approximately 9.6 V with minimal V_th shift throughout the 10³ cycles. Conversely, the DP-processed devices displayed a continuous negative shift in the programmed V_th. In particular, the memory window of the DP 700 °C device decreased from its initial 4.2 V as the cycles progressed.

These endurance and retention properties suggest that the HfO₂/IGZO interface, formed via the combination of RP-ALD and thermal annealing, can trap and maintain electrons while suppressing the generation of stress-induced trap sites.

4. Conclusions

Bottom-gate HfO₂/IGZO CTM devices were fabricated to investigate the effects of the deposition mode (DP-ALD vs. RP-ALD) of the HfO₂ charge-trapping layer on the crystallization of the overlying IGZO channel and the resulting memory performance.

The analysis revealed that, unlike the DP-ALD process involving high-energy ion bombardment, the RP-ALD process formed a smooth interface without causing physical damage to the HfO₂ surface. The devices deposited via the RP mode maintained operational stability and exhibited improved performance even after thermal annealing in the range of 300–700 °C.

To decouple the mechanistic effects of these plasma modes on device performance, an electrical analysis using the Y-function method was applied. Although the DP devices exhibited high intrinsic mobility at 700 °C, the actual transconductance decreased due to an increase in contact resistance (R_c) and a high interface trap density (D_it) originating from interface defects. Conversely, the RP devices maintained low R_c and D_it owing to the undamaged interface, which facilitated the translation of the IGZO transport characteristics without significant parasitic loss.

The RP-ALD devices exhibited a broadened memory window (ΔV_th), which is a key performance metric for CTM applications. This enhancement is attributed to the increased charge-trapping efficiency and the suppressed leakage of stored charges achieved by the RP process.

In conclusion, the RP-ALD technique maintains a stable memory window and switching reliability even in high-temperature environments. Therefore, the proposed RP-ALD-based HfO₂/IGZO structure serves as a reliable approach for securing stable memory characteristics in ALD processes, provided that appropriate plasma processing conditions are adopted.